mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-09-16 01:03:31 +00:00
Hexagon (target/hexagon) Enable more short-circuit packets (HVX)
Look for read-after-write instead of overlap of reads and writes HVX instructions with helpers have pass-by-reference semantics, so we check for overlaps of reads and writes within the same instruction. Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20240201103340.119081-4-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
This commit is contained in:
parent
bd983f68ac
commit
763d2ce7c4
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@ -43,6 +43,16 @@ def gen_analyze_func(f, tag, regs, imms):
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f.write("{\n")
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f.write("{\n")
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f.write(" Insn *insn G_GNUC_UNUSED = ctx->insn;\n")
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f.write(" Insn *insn G_GNUC_UNUSED = ctx->insn;\n")
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if (hex_common.is_hvx_insn(tag)):
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if hex_common.has_hvx_helper(tag):
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f.write(
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" const bool G_GNUC_UNUSED insn_has_hvx_helper = true;\n"
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)
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f.write(" ctx_start_hvx_insn(ctx);\n")
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else:
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f.write(
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" const bool G_GNUC_UNUSED insn_has_hvx_helper = false;\n"
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)
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## Declare all the registers
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## Declare all the registers
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for regno, register in enumerate(regs):
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for regno, register in enumerate(regs):
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@ -64,15 +74,6 @@ def gen_analyze_func(f, tag, regs, imms):
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if reg.is_written():
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if reg.is_written():
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reg.analyze_write(f, tag, regno)
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reg.analyze_write(f, tag, regno)
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has_generated_helper = not hex_common.skip_qemu_helper(
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tag
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) and not hex_common.is_idef_parser_enabled(tag)
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## Mark HVX instructions with generated helpers
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if (has_generated_helper and
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"A_CVI" in hex_common.attribdict[tag]):
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f.write(" ctx->has_hvx_helper = true;\n")
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f.write("}\n\n")
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f.write("}\n\n")
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@ -241,6 +241,16 @@ def is_idef_parser_enabled(tag):
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return tag in idef_parser_enabled
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return tag in idef_parser_enabled
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def is_hvx_insn(tag):
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return "A_CVI" in attribdict[tag]
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def has_hvx_helper(tag):
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return (is_hvx_insn(tag) and
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not skip_qemu_helper(tag) and
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not is_idef_parser_enabled(tag))
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def imm_name(immlett):
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def imm_name(immlett):
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return f"{immlett}iV"
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return f"{immlett}iV"
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@ -704,7 +714,8 @@ def analyze_write(self, f, tag, regno):
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newv = hvx_newv(tag)
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newv = hvx_newv(tag)
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predicated = "true" if is_predicated(tag) else "false"
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predicated = "true" if is_predicated(tag) else "false"
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated});
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ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated},
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insn_has_hvx_helper);
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"""))
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"""))
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class VRegSource(Register, Hvx, OldSource):
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class VRegSource(Register, Hvx, OldSource):
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@ -724,7 +735,7 @@ def helper_hvx_desc(self, f):
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"""))
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"""))
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def analyze_read(self, f, regno):
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def analyze_read(self, f, regno):
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_vreg_read(ctx, {self.reg_num});
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ctx_log_vreg_read(ctx, {self.reg_num}, insn_has_hvx_helper);
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"""))
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"""))
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class VRegNewSource(Register, Hvx, NewSource):
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class VRegNewSource(Register, Hvx, NewSource):
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@ -741,7 +752,7 @@ def helper_hvx_desc(self, f):
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"""))
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"""))
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def analyze_read(self, f, regno):
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def analyze_read(self, f, regno):
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_vreg_read_new(ctx, {self.reg_num});
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ctx_log_vreg_read_new(ctx, {self.reg_num}, insn_has_hvx_helper);
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"""))
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"""))
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class VRegReadWrite(Register, Hvx, ReadWrite):
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class VRegReadWrite(Register, Hvx, ReadWrite):
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@ -767,13 +778,14 @@ def helper_hvx_desc(self, f):
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"""))
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"""))
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def analyze_read(self, f, regno):
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def analyze_read(self, f, regno):
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_vreg_read(ctx, {self.reg_num});
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ctx_log_vreg_read(ctx, {self.reg_num}, insn_has_hvx_helper);
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"""))
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"""))
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def analyze_write(self, f, tag, regno):
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def analyze_write(self, f, tag, regno):
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newv = hvx_newv(tag)
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newv = hvx_newv(tag)
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predicated = "true" if is_predicated(tag) else "false"
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predicated = "true" if is_predicated(tag) else "false"
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated});
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ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated},
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insn_has_hvx_helper);
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"""))
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"""))
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class VRegTmp(Register, Hvx, ReadWrite):
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class VRegTmp(Register, Hvx, ReadWrite):
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@ -801,13 +813,14 @@ def helper_hvx_desc(self, f):
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"""))
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"""))
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def analyze_read(self, f, regno):
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def analyze_read(self, f, regno):
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_vreg_read(ctx, {self.reg_num});
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ctx_log_vreg_read(ctx, {self.reg_num}, insn_has_hvx_helper);
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"""))
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"""))
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def analyze_write(self, f, tag, regno):
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def analyze_write(self, f, tag, regno):
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newv = hvx_newv(tag)
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newv = hvx_newv(tag)
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predicated = "true" if is_predicated(tag) else "false"
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predicated = "true" if is_predicated(tag) else "false"
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated});
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ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated},
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insn_has_hvx_helper);
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"""))
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"""))
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class VRegPairDest(Register, Hvx, Dest):
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class VRegPairDest(Register, Hvx, Dest):
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@ -832,7 +845,8 @@ def analyze_write(self, f, tag, regno):
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newv = hvx_newv(tag)
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newv = hvx_newv(tag)
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predicated = "true" if is_predicated(tag) else "false"
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predicated = "true" if is_predicated(tag) else "false"
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicated});
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ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicated},
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insn_has_hvx_helper);
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"""))
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"""))
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class VRegPairSource(Register, Hvx, OldSource):
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class VRegPairSource(Register, Hvx, OldSource):
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@ -859,7 +873,7 @@ def helper_hvx_desc(self, f):
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"""))
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"""))
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def analyze_read(self, f, regno):
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def analyze_read(self, f, regno):
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_vreg_read_pair(ctx, {self.reg_num});
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ctx_log_vreg_read_pair(ctx, {self.reg_num}, insn_has_hvx_helper);
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"""))
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"""))
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class VRegPairReadWrite(Register, Hvx, ReadWrite):
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class VRegPairReadWrite(Register, Hvx, ReadWrite):
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@ -891,13 +905,14 @@ def helper_hvx_desc(self, f):
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"""))
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"""))
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def analyze_read(self, f, regno):
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def analyze_read(self, f, regno):
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_vreg_read_pair(ctx, {self.reg_num});
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ctx_log_vreg_read_pair(ctx, {self.reg_num}, insn_has_hvx_helper);
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"""))
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"""))
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def analyze_write(self, f, tag, regno):
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def analyze_write(self, f, tag, regno):
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newv = hvx_newv(tag)
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newv = hvx_newv(tag)
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predicated = "true" if is_predicated(tag) else "false"
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predicated = "true" if is_predicated(tag) else "false"
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicated});
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ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicated},
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insn_has_hvx_helper);
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"""))
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"""))
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class QRegDest(Register, Hvx, Dest):
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class QRegDest(Register, Hvx, Dest):
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@ -920,7 +935,7 @@ def helper_hvx_desc(self, f):
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"""))
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"""))
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def analyze_write(self, f, tag, regno):
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def analyze_write(self, f, tag, regno):
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_qreg_write(ctx, {self.reg_num});
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ctx_log_qreg_write(ctx, {self.reg_num}, insn_has_hvx_helper);
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"""))
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"""))
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class QRegSource(Register, Hvx, OldSource):
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class QRegSource(Register, Hvx, OldSource):
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"""))
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"""))
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def analyze_read(self, f, regno):
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def analyze_read(self, f, regno):
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_qreg_read(ctx, {self.reg_num});
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ctx_log_qreg_read(ctx, {self.reg_num}, insn_has_hvx_helper);
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"""))
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"""))
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class QRegReadWrite(Register, Hvx, ReadWrite):
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class QRegReadWrite(Register, Hvx, ReadWrite):
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@ -967,11 +982,11 @@ def helper_hvx_desc(self, f):
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"""))
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"""))
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def analyze_read(self, f, regno):
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def analyze_read(self, f, regno):
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_qreg_read(ctx, {self.reg_num});
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ctx_log_qreg_read(ctx, {self.reg_num}, insn_has_hvx_helper);
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"""))
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"""))
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def analyze_write(self, f, tag, regno):
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def analyze_write(self, f, tag, regno):
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f.write(code_fmt(f"""\
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f.write(code_fmt(f"""\
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ctx_log_qreg_write(ctx, {self.reg_num});
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ctx_log_qreg_write(ctx, {self.reg_num}, insn_has_hvx_helper);
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"""))
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"""))
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def init_registers():
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def init_registers():
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@ -380,60 +380,10 @@ static bool need_commit(DisasContext *ctx)
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return true;
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return true;
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}
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}
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if (pkt->num_insns == 1) {
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if (ctx->read_after_write || ctx->has_hvx_overlap) {
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if (pkt->pkt_has_hvx) {
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/*
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* The HVX instructions with generated helpers use
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* pass-by-reference, so they need the read/write overlap
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* check below.
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* The HVX instructions with overrides are OK.
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*/
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if (!ctx->has_hvx_helper) {
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return false;
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}
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} else {
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return false;
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}
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}
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if (ctx->read_after_write) {
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return true;
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return true;
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}
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}
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/* Check for overlap between HVX reads and writes */
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for (int i = 0; i < ctx->vreg_log_idx; i++) {
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int vnum = ctx->vreg_log[i];
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if (test_bit(vnum, ctx->vregs_read)) {
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return true;
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}
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}
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if (!bitmap_empty(ctx->vregs_updated_tmp, NUM_VREGS)) {
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int i = find_first_bit(ctx->vregs_updated_tmp, NUM_VREGS);
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while (i < NUM_VREGS) {
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if (test_bit(i, ctx->vregs_read)) {
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return true;
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}
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i = find_next_bit(ctx->vregs_updated_tmp, NUM_VREGS, i + 1);
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}
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}
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if (!bitmap_empty(ctx->vregs_select, NUM_VREGS)) {
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int i = find_first_bit(ctx->vregs_select, NUM_VREGS);
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while (i < NUM_VREGS) {
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if (test_bit(i, ctx->vregs_read)) {
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return true;
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}
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i = find_next_bit(ctx->vregs_select, NUM_VREGS, i + 1);
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}
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}
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/* Check for overlap between HVX predicate reads and writes */
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for (int i = 0; i < ctx->qreg_log_idx; i++) {
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int qnum = ctx->qreg_log[i];
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if (test_bit(qnum, ctx->qregs_read)) {
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return true;
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}
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}
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return false;
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return false;
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}
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}
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@ -455,8 +405,8 @@ static void mark_implicit_pred_reads(DisasContext *ctx)
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static void analyze_packet(DisasContext *ctx)
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static void analyze_packet(DisasContext *ctx)
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{
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{
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Packet *pkt = ctx->pkt;
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Packet *pkt = ctx->pkt;
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ctx->has_hvx_helper = false;
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ctx->read_after_write = false;
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ctx->read_after_write = false;
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ctx->has_hvx_overlap = false;
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for (int i = 0; i < pkt->num_insns; i++) {
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for (int i = 0; i < pkt->num_insns; i++) {
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Insn *insn = &pkt->insn[i];
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Insn *insn = &pkt->insn[i];
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ctx->insn = insn;
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ctx->insn = insn;
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@ -487,13 +437,13 @@ static void gen_start_packet(DisasContext *ctx)
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ctx->future_vregs_idx = 0;
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ctx->future_vregs_idx = 0;
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ctx->tmp_vregs_idx = 0;
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ctx->tmp_vregs_idx = 0;
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ctx->vreg_log_idx = 0;
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ctx->vreg_log_idx = 0;
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bitmap_zero(ctx->vregs_written, NUM_VREGS);
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bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS);
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bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS);
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bitmap_zero(ctx->vregs_updated, NUM_VREGS);
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bitmap_zero(ctx->vregs_updated, NUM_VREGS);
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bitmap_zero(ctx->vregs_select, NUM_VREGS);
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bitmap_zero(ctx->vregs_select, NUM_VREGS);
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bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS);
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bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS);
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bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS);
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bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS);
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bitmap_zero(ctx->vregs_read, NUM_VREGS);
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bitmap_zero(ctx->qregs_written, NUM_QREGS);
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bitmap_zero(ctx->qregs_read, NUM_QREGS);
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ctx->qreg_log_idx = 0;
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ctx->qreg_log_idx = 0;
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for (i = 0; i < STORES_MAX; i++) {
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for (i = 0; i < STORES_MAX; i++) {
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ctx->store_width[i] = 0;
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ctx->store_width[i] = 0;
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@ -50,23 +50,27 @@ typedef struct DisasContext {
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int tmp_vregs_num[VECTOR_TEMPS_MAX];
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int tmp_vregs_num[VECTOR_TEMPS_MAX];
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int vreg_log[NUM_VREGS];
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int vreg_log[NUM_VREGS];
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int vreg_log_idx;
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int vreg_log_idx;
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DECLARE_BITMAP(vregs_written, NUM_VREGS);
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DECLARE_BITMAP(insn_vregs_written, NUM_VREGS);
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DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
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DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
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DECLARE_BITMAP(vregs_updated, NUM_VREGS);
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DECLARE_BITMAP(vregs_updated, NUM_VREGS);
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DECLARE_BITMAP(vregs_select, NUM_VREGS);
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DECLARE_BITMAP(vregs_select, NUM_VREGS);
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DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS);
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DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS);
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DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS);
|
DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS);
|
||||||
DECLARE_BITMAP(vregs_read, NUM_VREGS);
|
DECLARE_BITMAP(insn_vregs_read, NUM_VREGS);
|
||||||
int qreg_log[NUM_QREGS];
|
int qreg_log[NUM_QREGS];
|
||||||
int qreg_log_idx;
|
int qreg_log_idx;
|
||||||
DECLARE_BITMAP(qregs_read, NUM_QREGS);
|
DECLARE_BITMAP(qregs_written, NUM_QREGS);
|
||||||
|
DECLARE_BITMAP(insn_qregs_written, NUM_QREGS);
|
||||||
|
DECLARE_BITMAP(insn_qregs_read, NUM_QREGS);
|
||||||
bool pre_commit;
|
bool pre_commit;
|
||||||
bool need_commit;
|
bool need_commit;
|
||||||
TCGCond branch_cond;
|
TCGCond branch_cond;
|
||||||
target_ulong branch_dest;
|
target_ulong branch_dest;
|
||||||
bool is_tight_loop;
|
bool is_tight_loop;
|
||||||
bool short_circuit;
|
bool short_circuit;
|
||||||
bool has_hvx_helper;
|
|
||||||
bool read_after_write;
|
bool read_after_write;
|
||||||
|
bool has_hvx_overlap;
|
||||||
TCGv new_value[TOTAL_PER_THREAD_REGS];
|
TCGv new_value[TOTAL_PER_THREAD_REGS];
|
||||||
TCGv new_pred_value[NUM_PREGS];
|
TCGv new_pred_value[NUM_PREGS];
|
||||||
TCGv pred_written;
|
TCGv pred_written;
|
||||||
|
@ -146,10 +150,25 @@ intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
|
||||||
intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
|
intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
|
||||||
int num, bool alloc_ok);
|
int num, bool alloc_ok);
|
||||||
|
|
||||||
|
static inline void ctx_start_hvx_insn(DisasContext *ctx)
|
||||||
|
{
|
||||||
|
bitmap_zero(ctx->insn_vregs_written, NUM_VREGS);
|
||||||
|
bitmap_zero(ctx->insn_vregs_read, NUM_VREGS);
|
||||||
|
bitmap_zero(ctx->insn_qregs_written, NUM_QREGS);
|
||||||
|
bitmap_zero(ctx->insn_qregs_read, NUM_QREGS);
|
||||||
|
}
|
||||||
|
|
||||||
static inline void ctx_log_vreg_write(DisasContext *ctx,
|
static inline void ctx_log_vreg_write(DisasContext *ctx,
|
||||||
int rnum, VRegWriteType type,
|
int rnum, VRegWriteType type,
|
||||||
bool is_predicated)
|
bool is_predicated, bool has_helper)
|
||||||
{
|
{
|
||||||
|
if (has_helper) {
|
||||||
|
set_bit(rnum, ctx->insn_vregs_written);
|
||||||
|
if (test_bit(rnum, ctx->insn_vregs_read)) {
|
||||||
|
ctx->has_hvx_overlap = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
set_bit(rnum, ctx->vregs_written);
|
||||||
if (type != EXT_TMP) {
|
if (type != EXT_TMP) {
|
||||||
if (!test_bit(rnum, ctx->vregs_updated)) {
|
if (!test_bit(rnum, ctx->vregs_updated)) {
|
||||||
ctx->vreg_log[ctx->vreg_log_idx] = rnum;
|
ctx->vreg_log[ctx->vreg_log_idx] = rnum;
|
||||||
|
@ -175,42 +194,77 @@ static inline void ctx_log_vreg_write(DisasContext *ctx,
|
||||||
|
|
||||||
static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
|
static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
|
||||||
int rnum, VRegWriteType type,
|
int rnum, VRegWriteType type,
|
||||||
bool is_predicated)
|
bool is_predicated, bool has_helper)
|
||||||
{
|
{
|
||||||
ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated);
|
ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated, has_helper);
|
||||||
ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated);
|
ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated, has_helper);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void ctx_log_vreg_read(DisasContext *ctx, int rnum)
|
static inline void ctx_log_vreg_read(DisasContext *ctx, int rnum,
|
||||||
|
bool has_helper)
|
||||||
{
|
{
|
||||||
set_bit(rnum, ctx->vregs_read);
|
if (has_helper) {
|
||||||
|
set_bit(rnum, ctx->insn_vregs_read);
|
||||||
|
if (test_bit(rnum, ctx->insn_vregs_written)) {
|
||||||
|
ctx->has_hvx_overlap = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (test_bit(rnum, ctx->vregs_written)) {
|
||||||
|
ctx->read_after_write = true;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void ctx_log_vreg_read_new(DisasContext *ctx, int rnum)
|
static inline void ctx_log_vreg_read_new(DisasContext *ctx, int rnum,
|
||||||
|
bool has_helper)
|
||||||
{
|
{
|
||||||
g_assert(is_gather_store_insn(ctx) ||
|
g_assert(is_gather_store_insn(ctx) ||
|
||||||
test_bit(rnum, ctx->vregs_updated) ||
|
test_bit(rnum, ctx->vregs_updated) ||
|
||||||
test_bit(rnum, ctx->vregs_select) ||
|
test_bit(rnum, ctx->vregs_select) ||
|
||||||
test_bit(rnum, ctx->vregs_updated_tmp));
|
test_bit(rnum, ctx->vregs_updated_tmp));
|
||||||
set_bit(rnum, ctx->vregs_read);
|
if (has_helper) {
|
||||||
|
set_bit(rnum, ctx->insn_vregs_read);
|
||||||
|
if (test_bit(rnum, ctx->insn_vregs_written)) {
|
||||||
|
ctx->has_hvx_overlap = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (is_gather_store_insn(ctx)) {
|
||||||
|
ctx->read_after_write = true;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum)
|
static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum,
|
||||||
|
bool has_helper)
|
||||||
{
|
{
|
||||||
ctx_log_vreg_read(ctx, rnum ^ 0);
|
ctx_log_vreg_read(ctx, rnum ^ 0, has_helper);
|
||||||
ctx_log_vreg_read(ctx, rnum ^ 1);
|
ctx_log_vreg_read(ctx, rnum ^ 1, has_helper);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void ctx_log_qreg_write(DisasContext *ctx,
|
static inline void ctx_log_qreg_write(DisasContext *ctx,
|
||||||
int rnum)
|
int rnum, bool has_helper)
|
||||||
{
|
{
|
||||||
|
if (has_helper) {
|
||||||
|
set_bit(rnum, ctx->insn_qregs_written);
|
||||||
|
if (test_bit(rnum, ctx->insn_qregs_read)) {
|
||||||
|
ctx->has_hvx_overlap = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
set_bit(rnum, ctx->qregs_written);
|
||||||
ctx->qreg_log[ctx->qreg_log_idx] = rnum;
|
ctx->qreg_log[ctx->qreg_log_idx] = rnum;
|
||||||
ctx->qreg_log_idx++;
|
ctx->qreg_log_idx++;
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void ctx_log_qreg_read(DisasContext *ctx, int qnum)
|
static inline void ctx_log_qreg_read(DisasContext *ctx,
|
||||||
|
int qnum, bool has_helper)
|
||||||
{
|
{
|
||||||
set_bit(qnum, ctx->qregs_read);
|
if (has_helper) {
|
||||||
|
set_bit(qnum, ctx->insn_qregs_read);
|
||||||
|
if (test_bit(qnum, ctx->insn_qregs_written)) {
|
||||||
|
ctx->has_hvx_overlap = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (test_bit(qnum, ctx->qregs_written)) {
|
||||||
|
ctx->read_after_write = true;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
|
extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
|
||||||
|
|
Loading…
Reference in a new issue