mirror of
https://gitlab.com/qemu-project/qemu
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target/xtensa updates:
- add libisa to the xtensa target; - change xtensa instruction translator to use it; - switch existing xtensa cores to use it; - add support for a number of instructions: salt/saltu, const16, GPIO32 group, debug mode and MMU-related; - add disassembler for Xtensa. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJaVQW2AAoJEFH5zJH4P6BEQ4EP/01BnD+SoHkDDRx8O59RgvUa r4kkJIqRNpObzzjhoHmh9RbGstir9r1u3ZYKbdlhPgZWK/ItUVzS8yJp8KcQ8x4B Z+4JzwX82PwAvvVdP7TD6iB23jqgUcoEdCtpaUb1jsK0tyvVHwIHnwF3qINY6Nsn yIzmupdIc47MEFlQNSxF/ZuvQI6CT8uDFuRJlK02dv8lEozUXCi9UHotICnqOybY ezgXCoMrOv7UqBdSEX7SQHvs5CD8zRbfhrwpeMc59YsbWp4j5JmQi1QI2ihFHyDN wp5vBDMI31SRdIqpEJiNEP5J+VnVg2oaJZcFP12JGXfTvSyB2WWSfqvQX+go394r 4NbWu1rA/a0vQVUfI7xVqY9mXqGnRbDS01ILYHbjRl14o7kZY0IpX2UIoGXI2eO9 toC+shIv/yNIJoaTlQf3ER+0nUvNFEGbBq3LNB+dlom8yqv7UY2LgpRy4zGqEfyL bB4pfEkaZVqP8vAJeq0TALMTmpvPjgFs1XxnHJAcpoAF3NM8dHiuGpO3li1jPiVu ZxN/8rWSWdJX7IvXFmu3Cy2ogLpdTxsTPIdtpKc+OLHNW6b5wx28Godig7JlfNil 8p9F1t6ZNvs4fPM2JFWP9VTXhzSuynWYz/UEr1+OF7vxni/x7dgrX2h9Houx36/e 3fn34SXgQUqhgtN+8BFR =PNwZ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/xtensa/tags/20180109-xtensa' into staging target/xtensa updates: - add libisa to the xtensa target; - change xtensa instruction translator to use it; - switch existing xtensa cores to use it; - add support for a number of instructions: salt/saltu, const16, GPIO32 group, debug mode and MMU-related; - add disassembler for Xtensa. # gpg: Signature made Tue 09 Jan 2018 18:11:02 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180109-xtensa: target/xtensa: implement disassembler target/xtensa: implement const16 target/xtensa: implement GPIO32 target/xtensa: implement salt/saltu target/xtensa: add internal/noop SRs and opcodes target/xtensa: drop DisasContext::litbase target/xtensa: tests: fix memctl SR test target/xtensa: use libisa for instruction decoding target/xtensa: switch fsf to libisa target/xtensa: switch dc233c to libisa target/xtensa: switch dc232b to libisa target/xtensa: update import_core.sh script for libisa target/xtensa: extract FPU2000 opcode translators target/xtensa: extract core opcode translators target/xtensa: import libisa source target/xtensa: pass actual frame size to the entry helper Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
76302a95e7
|
@ -259,6 +259,7 @@ S: Maintained
|
|||
F: target/xtensa/
|
||||
F: hw/xtensa/
|
||||
F: tests/tcg/xtensa/
|
||||
F: disas/xtensa.c
|
||||
|
||||
TriCore
|
||||
M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
|
||||
|
|
|
@ -21,6 +21,7 @@ common-obj-$(CONFIG_S390_DIS) += s390.o
|
|||
common-obj-$(CONFIG_SH4_DIS) += sh4.o
|
||||
common-obj-$(CONFIG_SPARC_DIS) += sparc.o
|
||||
common-obj-$(CONFIG_LM32_DIS) += lm32.o
|
||||
common-obj-$(CONFIG_XTENSA_DIS) += xtensa.o
|
||||
|
||||
# TODO: As long as the TCG interpreter and its generated code depend
|
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# on the QEMU target, we cannot compile the disassembler here.
|
||||
|
|
133
disas/xtensa.c
Normal file
133
disas/xtensa.c
Normal file
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
* Copyright (c) 2017, Max Filippov, Open Source and Linux Lab.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of the Open Source and Linux Lab nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "disas/bfd.h"
|
||||
#include "hw/xtensa/xtensa-isa.h"
|
||||
|
||||
int print_insn_xtensa(bfd_vma memaddr, struct disassemble_info *info)
|
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{
|
||||
xtensa_isa isa = info->private_data;
|
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xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc(isa);
|
||||
xtensa_insnbuf slotbuf = xtensa_insnbuf_alloc(isa);
|
||||
bfd_byte *buffer = g_malloc(1);
|
||||
int status = info->read_memory_func(memaddr, buffer, 1, info);
|
||||
xtensa_format fmt;
|
||||
unsigned slot, slots;
|
||||
unsigned len;
|
||||
|
||||
if (status) {
|
||||
info->memory_error_func(status, memaddr, info);
|
||||
len = -1;
|
||||
goto out;
|
||||
}
|
||||
len = xtensa_isa_length_from_chars(isa, buffer);
|
||||
if (len == XTENSA_UNDEFINED) {
|
||||
info->fprintf_func(info->stream, ".byte 0x%02x", buffer[0]);
|
||||
len = 1;
|
||||
goto out;
|
||||
}
|
||||
buffer = g_realloc(buffer, len);
|
||||
status = info->read_memory_func(memaddr + 1, buffer + 1, len - 1, info);
|
||||
if (status) {
|
||||
info->fprintf_func(info->stream, ".byte 0x%02x", buffer[0]);
|
||||
info->memory_error_func(status, memaddr + 1, info);
|
||||
len = 1;
|
||||
goto out;
|
||||
}
|
||||
|
||||
xtensa_insnbuf_from_chars(isa, insnbuf, buffer, len);
|
||||
fmt = xtensa_format_decode(isa, insnbuf);
|
||||
if (fmt == XTENSA_UNDEFINED) {
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < len; ++i) {
|
||||
info->fprintf_func(info->stream, "%s 0x%02x",
|
||||
i ? ", " : ".byte ", buffer[i]);
|
||||
}
|
||||
goto out;
|
||||
}
|
||||
slots = xtensa_format_num_slots(isa, fmt);
|
||||
|
||||
if (slots > 1) {
|
||||
info->fprintf_func(info->stream, "{ ");
|
||||
}
|
||||
|
||||
for (slot = 0; slot < slots; ++slot) {
|
||||
xtensa_opcode opc;
|
||||
unsigned opnd, vopnd, opnds;
|
||||
|
||||
if (slot) {
|
||||
info->fprintf_func(info->stream, "; ");
|
||||
}
|
||||
xtensa_format_get_slot(isa, fmt, slot, insnbuf, slotbuf);
|
||||
opc = xtensa_opcode_decode(isa, fmt, slot, slotbuf);
|
||||
if (opc == XTENSA_UNDEFINED) {
|
||||
info->fprintf_func(info->stream, "???");
|
||||
continue;
|
||||
}
|
||||
opnds = xtensa_opcode_num_operands(isa, opc);
|
||||
|
||||
info->fprintf_func(info->stream, "%s", xtensa_opcode_name(isa, opc));
|
||||
|
||||
for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
|
||||
if (xtensa_operand_is_visible(isa, opc, opnd)) {
|
||||
uint32_t v = 0xbadc0de;
|
||||
int rc;
|
||||
|
||||
info->fprintf_func(info->stream, vopnd ? ", " : "\t");
|
||||
xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
|
||||
slotbuf, &v);
|
||||
rc = xtensa_operand_decode(isa, opc, opnd, &v);
|
||||
if (rc == XTENSA_UNDEFINED) {
|
||||
info->fprintf_func(info->stream, "???");
|
||||
} else if (xtensa_operand_is_register(isa, opc, opnd)) {
|
||||
xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd);
|
||||
|
||||
info->fprintf_func(info->stream, "%s%d",
|
||||
xtensa_regfile_shortname(isa, rf), v);
|
||||
} else if (xtensa_operand_is_PCrelative(isa, opc, opnd)) {
|
||||
xtensa_operand_undo_reloc(isa, opc, opnd, &v, memaddr);
|
||||
info->fprintf_func(info->stream, "0x%x", v);
|
||||
} else {
|
||||
info->fprintf_func(info->stream, "%d", v);
|
||||
}
|
||||
++vopnd;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (slots > 1) {
|
||||
info->fprintf_func(info->stream, " }");
|
||||
}
|
||||
|
||||
out:
|
||||
g_free(buffer);
|
||||
xtensa_insnbuf_free(isa, insnbuf);
|
||||
xtensa_insnbuf_free(isa, slotbuf);
|
||||
|
||||
return len;
|
||||
}
|
|
@ -428,6 +428,7 @@ int print_insn_ia64 (bfd_vma, disassemble_info*);
|
|||
int print_insn_lm32 (bfd_vma, disassemble_info*);
|
||||
int print_insn_big_nios2 (bfd_vma, disassemble_info*);
|
||||
int print_insn_little_nios2 (bfd_vma, disassemble_info*);
|
||||
int print_insn_xtensa (bfd_vma, disassemble_info*);
|
||||
|
||||
#if 0
|
||||
/* Fetch the disassembler for a given BFD, if that support is available. */
|
||||
|
|
838
include/hw/xtensa/xtensa-isa.h
Normal file
838
include/hw/xtensa/xtensa-isa.h
Normal file
|
@ -0,0 +1,838 @@
|
|||
/* Interface definition for configurable Xtensa ISA support.
|
||||
*
|
||||
* Copyright (c) 2001-2013 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef XTENSA_LIBISA_H
|
||||
#define XTENSA_LIBISA_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Version number: This is intended to help support code that works with
|
||||
* versions of this library from multiple Xtensa releases.
|
||||
*/
|
||||
|
||||
#define XTENSA_ISA_VERSION 7000
|
||||
|
||||
/*
|
||||
* This file defines the interface to the Xtensa ISA library. This
|
||||
* library contains most of the ISA-specific information for a
|
||||
* particular Xtensa processor. For example, the set of valid
|
||||
* instructions, their opcode encodings and operand fields are all
|
||||
* included here.
|
||||
*
|
||||
* This interface basically defines a number of abstract data types.
|
||||
*
|
||||
* . an instruction buffer - for holding the raw instruction bits
|
||||
* . ISA info - information about the ISA as a whole
|
||||
* . instruction formats - instruction size and slot structure
|
||||
* . opcodes - information about individual instructions
|
||||
* . operands - information about register and immediate instruction operands
|
||||
* . stateOperands - information about processor state instruction operands
|
||||
* . interfaceOperands - information about interface instruction operands
|
||||
* . register files - register file information
|
||||
* . processor states - internal processor state information
|
||||
* . system registers - "special registers" and "user registers"
|
||||
* . interfaces - TIE interfaces that are external to the processor
|
||||
* . functional units - TIE shared functions
|
||||
*
|
||||
* The interface defines a set of functions to access each data type.
|
||||
* With the exception of the instruction buffer, the internal
|
||||
* representations of the data structures are hidden. All accesses must
|
||||
* be made through the functions defined here.
|
||||
*/
|
||||
|
||||
typedef struct xtensa_isa_opaque { int unused; } *xtensa_isa;
|
||||
|
||||
|
||||
/*
|
||||
* Most of the Xtensa ISA entities (e.g., opcodes, regfiles, etc.) are
|
||||
* represented here using sequential integers beginning with 0. The
|
||||
* specific values are only fixed for a particular instantiation of an
|
||||
* xtensa_isa structure, so these values should only be used
|
||||
* internally.
|
||||
*/
|
||||
|
||||
typedef int xtensa_opcode;
|
||||
typedef int xtensa_format;
|
||||
typedef int xtensa_regfile;
|
||||
typedef int xtensa_state;
|
||||
typedef int xtensa_sysreg;
|
||||
typedef int xtensa_interface;
|
||||
typedef int xtensa_funcUnit;
|
||||
|
||||
|
||||
/* Define a unique value for undefined items. */
|
||||
|
||||
#define XTENSA_UNDEFINED -1
|
||||
|
||||
|
||||
/*
|
||||
* Overview of using this interface to decode/encode instructions:
|
||||
*
|
||||
* Each Xtensa instruction is associated with a particular instruction
|
||||
* format, where the format defines a fixed number of slots for
|
||||
* operations. The formats for the core Xtensa ISA have only one slot,
|
||||
* but FLIX instructions may have multiple slots. Within each slot,
|
||||
* there is a single opcode and some number of associated operands.
|
||||
*
|
||||
* The encoding and decoding functions operate on instruction buffers,
|
||||
* not on the raw bytes of the instructions. The same instruction
|
||||
* buffer data structure is used for both entire instructions and
|
||||
* individual slots in those instructions -- the contents of a slot need
|
||||
* to be extracted from or inserted into the buffer for the instruction
|
||||
* as a whole.
|
||||
*
|
||||
* Decoding an instruction involves first finding the format, which
|
||||
* identifies the number of slots, and then decoding each slot
|
||||
* separately. A slot is decoded by finding the opcode and then using
|
||||
* the opcode to determine how many operands there are. For example:
|
||||
*
|
||||
* xtensa_insnbuf_from_chars
|
||||
* xtensa_format_decode
|
||||
* for each slot {
|
||||
* xtensa_format_get_slot
|
||||
* xtensa_opcode_decode
|
||||
* for each operand {
|
||||
* xtensa_operand_get_field
|
||||
* xtensa_operand_decode
|
||||
* }
|
||||
* }
|
||||
*
|
||||
* Encoding an instruction is roughly the same procedure in reverse:
|
||||
*
|
||||
* xtensa_format_encode
|
||||
* for each slot {
|
||||
* xtensa_opcode_encode
|
||||
* for each operand {
|
||||
* xtensa_operand_encode
|
||||
* xtensa_operand_set_field
|
||||
* }
|
||||
* xtensa_format_set_slot
|
||||
* }
|
||||
* xtensa_insnbuf_to_chars
|
||||
*/
|
||||
|
||||
|
||||
/* Error handling. */
|
||||
|
||||
/*
|
||||
* Error codes. The code for the most recent error condition can be
|
||||
* retrieved with the "errno" function. For any result other than
|
||||
* xtensa_isa_ok, an error message containing additional information
|
||||
* about the problem can be retrieved using the "error_msg" function.
|
||||
* The error messages are stored in an internal buffer, which should
|
||||
* not be freed and may be overwritten by subsequent operations.
|
||||
*/
|
||||
|
||||
typedef enum xtensa_isa_status_enum {
|
||||
xtensa_isa_ok = 0,
|
||||
xtensa_isa_bad_format,
|
||||
xtensa_isa_bad_slot,
|
||||
xtensa_isa_bad_opcode,
|
||||
xtensa_isa_bad_operand,
|
||||
xtensa_isa_bad_field,
|
||||
xtensa_isa_bad_iclass,
|
||||
xtensa_isa_bad_regfile,
|
||||
xtensa_isa_bad_sysreg,
|
||||
xtensa_isa_bad_state,
|
||||
xtensa_isa_bad_interface,
|
||||
xtensa_isa_bad_funcUnit,
|
||||
xtensa_isa_wrong_slot,
|
||||
xtensa_isa_no_field,
|
||||
xtensa_isa_out_of_memory,
|
||||
xtensa_isa_buffer_overflow,
|
||||
xtensa_isa_internal_error,
|
||||
xtensa_isa_bad_value
|
||||
} xtensa_isa_status;
|
||||
|
||||
xtensa_isa_status xtensa_isa_errno(xtensa_isa isa);
|
||||
|
||||
char *xtensa_isa_error_msg(xtensa_isa isa);
|
||||
|
||||
|
||||
|
||||
/* Instruction buffers. */
|
||||
|
||||
typedef uint32_t xtensa_insnbuf_word;
|
||||
typedef xtensa_insnbuf_word *xtensa_insnbuf;
|
||||
|
||||
|
||||
/* Get the size in "insnbuf_words" of the xtensa_insnbuf array. */
|
||||
|
||||
int xtensa_insnbuf_size(xtensa_isa isa);
|
||||
|
||||
|
||||
/* Allocate an xtensa_insnbuf of the right size. */
|
||||
|
||||
xtensa_insnbuf xtensa_insnbuf_alloc(xtensa_isa isa);
|
||||
|
||||
|
||||
/* Release an xtensa_insnbuf. */
|
||||
|
||||
void xtensa_insnbuf_free(xtensa_isa isa, xtensa_insnbuf buf);
|
||||
|
||||
|
||||
/*
|
||||
* Conversion between raw memory (char arrays) and our internal
|
||||
* instruction representation. This is complicated by the Xtensa ISA's
|
||||
* variable instruction lengths. When converting to chars, the buffer
|
||||
* must contain a valid instruction so we know how many bytes to copy;
|
||||
* thus, the "to_chars" function returns the number of bytes copied or
|
||||
* XTENSA_UNDEFINED on error. The "from_chars" function first reads the
|
||||
* minimal number of bytes required to decode the instruction length and
|
||||
* then proceeds to copy the entire instruction into the buffer; if the
|
||||
* memory does not contain a valid instruction, it copies the maximum
|
||||
* number of bytes required for the longest Xtensa instruction. The
|
||||
* "num_chars" argument may be used to limit the number of bytes that
|
||||
* can be read or written. Otherwise, if "num_chars" is zero, the
|
||||
* functions may read or write past the end of the code.
|
||||
*/
|
||||
|
||||
int xtensa_insnbuf_to_chars(xtensa_isa isa, const xtensa_insnbuf insn,
|
||||
unsigned char *cp, int num_chars);
|
||||
|
||||
void xtensa_insnbuf_from_chars(xtensa_isa isa, xtensa_insnbuf insn,
|
||||
const unsigned char *cp, int num_chars);
|
||||
|
||||
|
||||
|
||||
/* ISA information. */
|
||||
|
||||
/* Initialize the ISA information. */
|
||||
|
||||
xtensa_isa xtensa_isa_init(void *xtensa_modules, xtensa_isa_status *errno_p,
|
||||
char **error_msg_p);
|
||||
|
||||
|
||||
/* Deallocate an xtensa_isa structure. */
|
||||
|
||||
void xtensa_isa_free(xtensa_isa isa);
|
||||
|
||||
|
||||
/* Get the maximum instruction size in bytes. */
|
||||
|
||||
int xtensa_isa_maxlength(xtensa_isa isa);
|
||||
|
||||
|
||||
/*
|
||||
* Decode the length in bytes of an instruction in raw memory (not an
|
||||
* insnbuf). This function reads only the minimal number of bytes
|
||||
* required to decode the instruction length. Returns
|
||||
* XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_isa_length_from_chars(xtensa_isa isa, const unsigned char *cp);
|
||||
|
||||
|
||||
/*
|
||||
* Get the number of stages in the processor's pipeline. The pipeline
|
||||
* stage values returned by other functions in this library will range
|
||||
* from 0 to N-1, where N is the value returned by this function.
|
||||
* Note that the stage numbers used here may not correspond to the
|
||||
* actual processor hardware, e.g., the hardware may have additional
|
||||
* stages before stage 0. Returns XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_isa_num_pipe_stages(xtensa_isa isa);
|
||||
|
||||
|
||||
/* Get the number of various entities that are defined for this processor. */
|
||||
|
||||
int xtensa_isa_num_formats(xtensa_isa isa);
|
||||
|
||||
int xtensa_isa_num_opcodes(xtensa_isa isa);
|
||||
|
||||
int xtensa_isa_num_regfiles(xtensa_isa isa);
|
||||
|
||||
int xtensa_isa_num_states(xtensa_isa isa);
|
||||
|
||||
int xtensa_isa_num_sysregs(xtensa_isa isa);
|
||||
|
||||
int xtensa_isa_num_interfaces(xtensa_isa isa);
|
||||
|
||||
int xtensa_isa_num_funcUnits(xtensa_isa isa);
|
||||
|
||||
|
||||
|
||||
/* Instruction formats. */
|
||||
|
||||
/* Get the name of a format. Returns null on error. */
|
||||
|
||||
const char *xtensa_format_name(xtensa_isa isa, xtensa_format fmt);
|
||||
|
||||
|
||||
/*
|
||||
* Given a format name, return the format number. Returns
|
||||
* XTENSA_UNDEFINED if the name is not a valid format.
|
||||
*/
|
||||
|
||||
xtensa_format xtensa_format_lookup(xtensa_isa isa, const char *fmtname);
|
||||
|
||||
|
||||
/*
|
||||
* Decode the instruction format from a binary instruction buffer.
|
||||
* Returns XTENSA_UNDEFINED if the format is not recognized.
|
||||
*/
|
||||
|
||||
xtensa_format xtensa_format_decode(xtensa_isa isa, const xtensa_insnbuf insn);
|
||||
|
||||
|
||||
/*
|
||||
* Set the instruction format field(s) in a binary instruction buffer.
|
||||
* All the other fields are set to zero. Returns non-zero on error.
|
||||
*/
|
||||
|
||||
int xtensa_format_encode(xtensa_isa isa, xtensa_format fmt,
|
||||
xtensa_insnbuf insn);
|
||||
|
||||
|
||||
/*
|
||||
* Find the length (in bytes) of an instruction. Returns
|
||||
* XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_format_length(xtensa_isa isa, xtensa_format fmt);
|
||||
|
||||
|
||||
/*
|
||||
* Get the number of slots in an instruction. Returns XTENSA_UNDEFINED
|
||||
* on error.
|
||||
*/
|
||||
|
||||
int xtensa_format_num_slots(xtensa_isa isa, xtensa_format fmt);
|
||||
|
||||
|
||||
/*
|
||||
* Get the opcode for a no-op in a particular slot.
|
||||
* Returns XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
xtensa_opcode xtensa_format_slot_nop_opcode(xtensa_isa isa, xtensa_format fmt,
|
||||
int slot);
|
||||
|
||||
|
||||
/*
|
||||
* Get the bits for a specified slot out of an insnbuf for the
|
||||
* instruction as a whole and put them into an insnbuf for that one
|
||||
* slot, and do the opposite to set a slot. Return non-zero on error.
|
||||
*/
|
||||
|
||||
int xtensa_format_get_slot(xtensa_isa isa, xtensa_format fmt, int slot,
|
||||
const xtensa_insnbuf insn, xtensa_insnbuf slotbuf);
|
||||
|
||||
int xtensa_format_set_slot(xtensa_isa isa, xtensa_format fmt, int slot,
|
||||
xtensa_insnbuf insn, const xtensa_insnbuf slotbuf);
|
||||
|
||||
|
||||
|
||||
/* Opcode information. */
|
||||
|
||||
/*
|
||||
* Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if
|
||||
* the name is not a valid opcode mnemonic.
|
||||
*/
|
||||
|
||||
xtensa_opcode xtensa_opcode_lookup(xtensa_isa isa, const char *opname);
|
||||
|
||||
|
||||
/*
|
||||
* Decode the opcode for one instruction slot from a binary instruction
|
||||
* buffer. Returns the opcode or XTENSA_UNDEFINED if the opcode is
|
||||
* illegal.
|
||||
*/
|
||||
|
||||
xtensa_opcode xtensa_opcode_decode(xtensa_isa isa, xtensa_format fmt, int slot,
|
||||
const xtensa_insnbuf slotbuf);
|
||||
|
||||
|
||||
/*
|
||||
* Set the opcode field(s) for an instruction slot. All other fields
|
||||
* in the slot are set to zero. Returns non-zero if the opcode cannot
|
||||
* be encoded.
|
||||
*/
|
||||
|
||||
int xtensa_opcode_encode(xtensa_isa isa, xtensa_format fmt, int slot,
|
||||
xtensa_insnbuf slotbuf, xtensa_opcode opc);
|
||||
|
||||
|
||||
/* Get the mnemonic name for an opcode. Returns null on error. */
|
||||
|
||||
const char *xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
|
||||
/* Check various properties of opcodes. These functions return 0 if
|
||||
* the condition is false, 1 if the condition is true, and
|
||||
* XTENSA_UNDEFINED on error. The instructions are classified as
|
||||
* follows:
|
||||
*
|
||||
* branch: conditional branch; may fall through to next instruction (B*)
|
||||
* jump: unconditional branch (J, JX, RET*, RF*)
|
||||
* loop: zero-overhead loop (LOOP*)
|
||||
* call: unconditional call; control returns to next instruction (CALL*)
|
||||
*
|
||||
* For the opcodes that affect control flow in some way, the branch
|
||||
* target may be specified by an immediate operand or it may be an
|
||||
* address stored in a register. You can distinguish these by
|
||||
* checking if the instruction has a PC-relative immediate
|
||||
* operand.
|
||||
*/
|
||||
|
||||
int xtensa_opcode_is_branch(xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
int xtensa_opcode_is_jump(xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
int xtensa_opcode_is_loop(xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
int xtensa_opcode_is_call(xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
|
||||
/*
|
||||
* Find the number of ordinary operands, state operands, and interface
|
||||
* operands for an instruction. These return XTENSA_UNDEFINED on
|
||||
* error.
|
||||
*/
|
||||
|
||||
int xtensa_opcode_num_operands(xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
int xtensa_opcode_num_stateOperands(xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
int xtensa_opcode_num_interfaceOperands(xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
|
||||
/*
|
||||
* Get functional unit usage requirements for an opcode. Each "use"
|
||||
* is identified by a <functional unit, pipeline stage> pair. The
|
||||
* "num_funcUnit_uses" function returns the number of these "uses" or
|
||||
* XTENSA_UNDEFINED on error. The "funcUnit_use" function returns
|
||||
* a pointer to a "use" pair or null on error.
|
||||
*/
|
||||
|
||||
typedef struct xtensa_funcUnit_use_struct {
|
||||
xtensa_funcUnit unit;
|
||||
int stage;
|
||||
} xtensa_funcUnit_use;
|
||||
|
||||
int xtensa_opcode_num_funcUnit_uses(xtensa_isa isa, xtensa_opcode opc);
|
||||
|
||||
xtensa_funcUnit_use *xtensa_opcode_funcUnit_use(xtensa_isa isa,
|
||||
xtensa_opcode opc, int u);
|
||||
|
||||
|
||||
|
||||
/* Operand information. */
|
||||
|
||||
/* Get the name of an operand. Returns null on error. */
|
||||
|
||||
const char *xtensa_operand_name(xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
|
||||
/*
|
||||
* Some operands are "invisible", i.e., not explicitly specified in
|
||||
* assembly language. When assembling an instruction, you need not set
|
||||
* the values of invisible operands, since they are either hardwired or
|
||||
* derived from other field values. The values of invisible operands
|
||||
* can be examined in the same way as other operands, but remember that
|
||||
* an invisible operand may get its value from another visible one, so
|
||||
* the entire instruction must be available before examining the
|
||||
* invisible operand values. This function returns 1 if an operand is
|
||||
* visible, 0 if it is invisible, or XTENSA_UNDEFINED on error. Note
|
||||
* that whether an operand is visible is orthogonal to whether it is
|
||||
* "implicit", i.e., whether it is encoded in a field in the
|
||||
* instruction.
|
||||
*/
|
||||
|
||||
int xtensa_operand_is_visible(xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
|
||||
/*
|
||||
* Check if an operand is an input ('i'), output ('o'), or inout ('m')
|
||||
* operand. Note: The output operand of a conditional assignment
|
||||
* (e.g., movnez) appears here as an inout ('m') even if it is declared
|
||||
* in the TIE code as an output ('o'); this allows the compiler to
|
||||
* properly handle register allocation for conditional assignments.
|
||||
* Returns 0 on error.
|
||||
*/
|
||||
|
||||
char xtensa_operand_inout(xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
|
||||
/*
|
||||
* Get and set the raw (encoded) value of the field for the specified
|
||||
* operand. The "set" function does not check if the value fits in the
|
||||
* field; that is done by the "encode" function below. Both of these
|
||||
* functions return non-zero on error, e.g., if the field is not defined
|
||||
* for the specified slot.
|
||||
*/
|
||||
|
||||
int xtensa_operand_get_field(xtensa_isa isa, xtensa_opcode opc, int opnd,
|
||||
xtensa_format fmt, int slot,
|
||||
const xtensa_insnbuf slotbuf, uint32_t *valp);
|
||||
|
||||
int xtensa_operand_set_field(xtensa_isa isa, xtensa_opcode opc, int opnd,
|
||||
xtensa_format fmt, int slot,
|
||||
xtensa_insnbuf slotbuf, uint32_t val);
|
||||
|
||||
|
||||
/*
|
||||
* Encode and decode operands. The raw bits in the operand field may
|
||||
* be encoded in a variety of different ways. These functions hide
|
||||
* the details of that encoding. The result values are returned through
|
||||
* the argument pointer. The return value is non-zero on error.
|
||||
*/
|
||||
|
||||
int xtensa_operand_encode(xtensa_isa isa, xtensa_opcode opc, int opnd,
|
||||
uint32_t *valp);
|
||||
|
||||
int xtensa_operand_decode(xtensa_isa isa, xtensa_opcode opc, int opnd,
|
||||
uint32_t *valp);
|
||||
|
||||
|
||||
/*
|
||||
* An operand may be either a register operand or an immediate of some
|
||||
* sort (e.g., PC-relative or not). The "is_register" function returns
|
||||
* 0 if the operand is an immediate, 1 if it is a register, and
|
||||
* XTENSA_UNDEFINED on error. The "regfile" function returns the
|
||||
* regfile for a register operand, or XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_operand_is_register(xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
xtensa_regfile xtensa_operand_regfile(xtensa_isa isa, xtensa_opcode opc,
|
||||
int opnd);
|
||||
|
||||
|
||||
/*
|
||||
* Register operands may span multiple consecutive registers, e.g., a
|
||||
* 64-bit data type may occupy two 32-bit registers. Only the first
|
||||
* register is encoded in the operand field. This function specifies
|
||||
* the number of consecutive registers occupied by this operand. For
|
||||
* non-register operands, the return value is undefined. Returns
|
||||
* XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_operand_num_regs(xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
|
||||
/*
|
||||
* Some register operands do not completely identify the register being
|
||||
* accessed. For example, the operand value may be added to an internal
|
||||
* state value. By definition, this implies that the corresponding
|
||||
* regfile is not allocatable. Unknown registers should generally be
|
||||
* treated with worst-case assumptions. The function returns 0 if the
|
||||
* register value is unknown, 1 if known, and XTENSA_UNDEFINED on
|
||||
* error.
|
||||
*/
|
||||
|
||||
int xtensa_operand_is_known_reg(xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
|
||||
/*
|
||||
* Check if an immediate operand is PC-relative. Returns 0 for register
|
||||
* operands and non-PC-relative immediates, 1 for PC-relative
|
||||
* immediates, and XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_operand_is_PCrelative(xtensa_isa isa, xtensa_opcode opc, int opnd);
|
||||
|
||||
|
||||
/*
|
||||
* For PC-relative offset operands, the interpretation of the offset may
|
||||
* vary between opcodes, e.g., is it relative to the current PC or that
|
||||
* of the next instruction? The following functions are defined to
|
||||
* perform PC-relative relocations and to undo them (as in the
|
||||
* disassembler). The "do_reloc" function takes the desired address
|
||||
* value and the PC of the current instruction and sets the value to the
|
||||
* corresponding PC-relative offset (which can then be encoded and
|
||||
* stored into the operand field). The "undo_reloc" function takes the
|
||||
* unencoded offset value and the current PC and sets the value to the
|
||||
* appropriate address. The return values are non-zero on error. Note
|
||||
* that these functions do not replace the encode/decode functions; the
|
||||
* operands must be encoded/decoded separately and the encode functions
|
||||
* are responsible for detecting invalid operand values.
|
||||
*/
|
||||
|
||||
int xtensa_operand_do_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd,
|
||||
uint32_t *valp, uint32_t pc);
|
||||
|
||||
int xtensa_operand_undo_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd,
|
||||
uint32_t *valp, uint32_t pc);
|
||||
|
||||
|
||||
|
||||
/* State Operands. */
|
||||
|
||||
/*
|
||||
* Get the state accessed by a state operand. Returns XTENSA_UNDEFINED
|
||||
* on error.
|
||||
*/
|
||||
|
||||
xtensa_state xtensa_stateOperand_state(xtensa_isa isa, xtensa_opcode opc,
|
||||
int stOp);
|
||||
|
||||
|
||||
/*
|
||||
* Check if a state operand is an input ('i'), output ('o'), or inout
|
||||
* ('m') operand. Returns 0 on error.
|
||||
*/
|
||||
|
||||
char xtensa_stateOperand_inout(xtensa_isa isa, xtensa_opcode opc, int stOp);
|
||||
|
||||
|
||||
|
||||
/* Interface Operands. */
|
||||
|
||||
/*
|
||||
* Get the external interface accessed by an interface operand.
|
||||
* Returns XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
xtensa_interface xtensa_interfaceOperand_interface(xtensa_isa isa,
|
||||
xtensa_opcode opc,
|
||||
int ifOp);
|
||||
|
||||
|
||||
|
||||
/* Register Files. */
|
||||
|
||||
/*
|
||||
* Regfiles include both "real" regfiles and "views", where a view
|
||||
* allows a group of adjacent registers in a real "parent" regfile to be
|
||||
* viewed as a single register. A regfile view has all the same
|
||||
* properties as its parent except for its (long) name, bit width, number
|
||||
* of entries, and default ctype. You can use the parent function to
|
||||
* distinguish these two classes.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Look up a regfile by either its name or its abbreviated "short name".
|
||||
* Returns XTENSA_UNDEFINED on error. The "lookup_shortname" function
|
||||
* ignores "view" regfiles since they always have the same shortname as
|
||||
* their parents.
|
||||
*/
|
||||
|
||||
xtensa_regfile xtensa_regfile_lookup(xtensa_isa isa, const char *name);
|
||||
|
||||
xtensa_regfile xtensa_regfile_lookup_shortname(xtensa_isa isa,
|
||||
const char *shortname);
|
||||
|
||||
|
||||
/*
|
||||
* Get the name or abbreviated "short name" of a regfile.
|
||||
* Returns null on error.
|
||||
*/
|
||||
|
||||
const char *xtensa_regfile_name(xtensa_isa isa, xtensa_regfile rf);
|
||||
|
||||
const char *xtensa_regfile_shortname(xtensa_isa isa, xtensa_regfile rf);
|
||||
|
||||
|
||||
/*
|
||||
* Get the parent regfile of a "view" regfile. If the regfile is not a
|
||||
* view, the result is the same as the input parameter. Returns
|
||||
* XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
xtensa_regfile xtensa_regfile_view_parent(xtensa_isa isa, xtensa_regfile rf);
|
||||
|
||||
|
||||
/*
|
||||
* Get the bit width of a regfile or regfile view.
|
||||
* Returns XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_regfile_num_bits(xtensa_isa isa, xtensa_regfile rf);
|
||||
|
||||
|
||||
/*
|
||||
* Get the number of regfile entries. Returns XTENSA_UNDEFINED on
|
||||
* error.
|
||||
*/
|
||||
|
||||
int xtensa_regfile_num_entries(xtensa_isa isa, xtensa_regfile rf);
|
||||
|
||||
|
||||
|
||||
/* Processor States. */
|
||||
|
||||
/* Look up a state by name. Returns XTENSA_UNDEFINED on error. */
|
||||
|
||||
xtensa_state xtensa_state_lookup(xtensa_isa isa, const char *name);
|
||||
|
||||
|
||||
/* Get the name for a processor state. Returns null on error. */
|
||||
|
||||
const char *xtensa_state_name(xtensa_isa isa, xtensa_state st);
|
||||
|
||||
|
||||
/*
|
||||
* Get the bit width for a processor state.
|
||||
* Returns XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_state_num_bits(xtensa_isa isa, xtensa_state st);
|
||||
|
||||
|
||||
/*
|
||||
* Check if a state is exported from the processor core. Returns 0 if
|
||||
* the condition is false, 1 if the condition is true, and
|
||||
* XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_state_is_exported(xtensa_isa isa, xtensa_state st);
|
||||
|
||||
|
||||
/*
|
||||
* Check for a "shared_or" state. Returns 0 if the condition is false,
|
||||
* 1 if the condition is true, and XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_state_is_shared_or(xtensa_isa isa, xtensa_state st);
|
||||
|
||||
|
||||
|
||||
/* Sysregs ("special registers" and "user registers"). */
|
||||
|
||||
/*
|
||||
* Look up a register by its number and whether it is a "user register"
|
||||
* or a "special register". Returns XTENSA_UNDEFINED if the sysreg does
|
||||
* not exist.
|
||||
*/
|
||||
|
||||
xtensa_sysreg xtensa_sysreg_lookup(xtensa_isa isa, int num, int is_user);
|
||||
|
||||
|
||||
/*
|
||||
* Check if there exists a sysreg with a given name.
|
||||
* If not, this function returns XTENSA_UNDEFINED.
|
||||
*/
|
||||
|
||||
xtensa_sysreg xtensa_sysreg_lookup_name(xtensa_isa isa, const char *name);
|
||||
|
||||
|
||||
/* Get the name of a sysreg. Returns null on error. */
|
||||
|
||||
const char *xtensa_sysreg_name(xtensa_isa isa, xtensa_sysreg sysreg);
|
||||
|
||||
|
||||
/* Get the register number. Returns XTENSA_UNDEFINED on error. */
|
||||
|
||||
int xtensa_sysreg_number(xtensa_isa isa, xtensa_sysreg sysreg);
|
||||
|
||||
|
||||
/*
|
||||
* Check if a sysreg is a "special register" or a "user register".
|
||||
* Returns 0 for special registers, 1 for user registers and
|
||||
* XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_sysreg_is_user(xtensa_isa isa, xtensa_sysreg sysreg);
|
||||
|
||||
|
||||
|
||||
/* Interfaces. */
|
||||
|
||||
/*
|
||||
* Find an interface by name. The return value is XTENSA_UNDEFINED if
|
||||
* the specified interface is not found.
|
||||
*/
|
||||
|
||||
xtensa_interface xtensa_interface_lookup(xtensa_isa isa, const char *ifname);
|
||||
|
||||
|
||||
/* Get the name of an interface. Returns null on error. */
|
||||
|
||||
const char *xtensa_interface_name(xtensa_isa isa, xtensa_interface intf);
|
||||
|
||||
|
||||
/*
|
||||
* Get the bit width for an interface.
|
||||
* Returns XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_interface_num_bits(xtensa_isa isa, xtensa_interface intf);
|
||||
|
||||
|
||||
/*
|
||||
* Check if an interface is an input ('i') or output ('o') with respect
|
||||
* to the Xtensa processor core. Returns 0 on error.
|
||||
*/
|
||||
|
||||
char xtensa_interface_inout(xtensa_isa isa, xtensa_interface intf);
|
||||
|
||||
|
||||
/*
|
||||
* Check if accessing an interface has potential side effects.
|
||||
* Currently "data" interfaces have side effects and "control"
|
||||
* interfaces do not. Returns 1 if there are side effects, 0 if not,
|
||||
* and XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_interface_has_side_effect(xtensa_isa isa, xtensa_interface intf);
|
||||
|
||||
|
||||
/*
|
||||
* Some interfaces may be related such that accessing one interface
|
||||
* has side effects on a set of related interfaces. The interfaces
|
||||
* are partitioned into equivalence classes of related interfaces, and
|
||||
* each class is assigned a unique identifier number. This function
|
||||
* returns the class identifier for an interface, or XTENSA_UNDEFINED
|
||||
* on error. These identifiers can be compared to determine if two
|
||||
* interfaces are related; the specific values of the identifiers have
|
||||
* no particular meaning otherwise.
|
||||
*/
|
||||
|
||||
int xtensa_interface_class_id(xtensa_isa isa, xtensa_interface intf);
|
||||
|
||||
|
||||
/* Functional Units. */
|
||||
|
||||
/*
|
||||
* Find a functional unit by name. The return value is XTENSA_UNDEFINED if
|
||||
* the specified unit is not found.
|
||||
*/
|
||||
|
||||
xtensa_funcUnit xtensa_funcUnit_lookup(xtensa_isa isa, const char *fname);
|
||||
|
||||
|
||||
/* Get the name of a functional unit. Returns null on error. */
|
||||
|
||||
const char *xtensa_funcUnit_name(xtensa_isa isa, xtensa_funcUnit fun);
|
||||
|
||||
|
||||
/*
|
||||
* Functional units may be replicated. See how many instances of a
|
||||
* particular function unit exist. Returns XTENSA_UNDEFINED on error.
|
||||
*/
|
||||
|
||||
int xtensa_funcUnit_num_copies(xtensa_isa isa, xtensa_funcUnit fun);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* XTENSA_LIBISA_H */
|
|
@ -3,5 +3,6 @@ obj-y += core-dc232b.o
|
|||
obj-y += core-dc233c.o
|
||||
obj-y += core-fsf.o
|
||||
obj-$(CONFIG_SOFTMMU) += monitor.o
|
||||
obj-y += xtensa-isa.o
|
||||
obj-y += translate.o op_helper.o helper.o cpu.o
|
||||
obj-y += gdbstub.o
|
||||
|
|
|
@ -34,6 +34,9 @@
|
|||
#include "core-dc232b/core-isa.h"
|
||||
#include "overlay_tool.h"
|
||||
|
||||
#define xtensa_modules xtensa_modules_dc232b
|
||||
#include "core-dc232b/xtensa-modules.c"
|
||||
|
||||
static XtensaConfig dc232b __attribute__((unused)) = {
|
||||
.name = "dc232b",
|
||||
.gdb_regmap = {
|
||||
|
@ -43,6 +46,7 @@ static XtensaConfig dc232b __attribute__((unused)) = {
|
|||
#include "core-dc232b/gdb-config.c"
|
||||
}
|
||||
},
|
||||
.isa_internal = &xtensa_modules,
|
||||
.clock_freq_khz = 10000,
|
||||
DEFAULT_SECTIONS
|
||||
};
|
||||
|
|
14105
target/xtensa/core-dc232b/xtensa-modules.c
Normal file
14105
target/xtensa/core-dc232b/xtensa-modules.c
Normal file
File diff suppressed because it is too large
Load diff
|
@ -35,6 +35,9 @@
|
|||
#include "core-dc233c/core-isa.h"
|
||||
#include "overlay_tool.h"
|
||||
|
||||
#define xtensa_modules xtensa_modules_dc233c
|
||||
#include "core-dc233c/xtensa-modules.c"
|
||||
|
||||
static XtensaConfig dc233c __attribute__((unused)) = {
|
||||
.name = "dc233c",
|
||||
.gdb_regmap = {
|
||||
|
@ -44,6 +47,7 @@ static XtensaConfig dc233c __attribute__((unused)) = {
|
|||
#include "core-dc233c/gdb-config.c"
|
||||
}
|
||||
},
|
||||
.isa_internal = &xtensa_modules,
|
||||
.clock_freq_khz = 10000,
|
||||
DEFAULT_SECTIONS
|
||||
};
|
||||
|
|
15232
target/xtensa/core-dc233c/xtensa-modules.c
Normal file
15232
target/xtensa/core-dc233c/xtensa-modules.c
Normal file
File diff suppressed because it is too large
Load diff
|
@ -29,11 +29,15 @@
|
|||
#include "cpu.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "exec/gdbstub.h"
|
||||
#include "qemu-common.h"
|
||||
#include "qemu/host-utils.h"
|
||||
|
||||
#include "core-fsf/core-isa.h"
|
||||
#include "overlay_tool.h"
|
||||
|
||||
#define xtensa_modules xtensa_modules_fsf
|
||||
#include "core-fsf/xtensa-modules.c"
|
||||
|
||||
static XtensaConfig fsf __attribute__((unused)) = {
|
||||
.name = "fsf",
|
||||
.gdb_regmap = {
|
||||
|
@ -42,6 +46,7 @@ static XtensaConfig fsf __attribute__((unused)) = {
|
|||
XTREG_END
|
||||
},
|
||||
},
|
||||
.isa_internal = &xtensa_modules,
|
||||
.clock_freq_khz = 10000,
|
||||
DEFAULT_SECTIONS
|
||||
};
|
||||
|
|
9841
target/xtensa/core-fsf/xtensa-modules.c
Normal file
9841
target/xtensa/core-fsf/xtensa-modules.c
Normal file
File diff suppressed because it is too large
Load diff
|
@ -93,6 +93,14 @@ static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
|
|||
return oc;
|
||||
}
|
||||
|
||||
static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
|
||||
{
|
||||
XtensaCPU *cpu = XTENSA_CPU(cs);
|
||||
|
||||
info->private_data = cpu->env.config->isa;
|
||||
info->print_insn = print_insn_xtensa;
|
||||
}
|
||||
|
||||
static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
|
||||
{
|
||||
CPUState *cs = CPU(dev);
|
||||
|
@ -164,6 +172,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
|
|||
cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
|
||||
#endif
|
||||
cc->debug_excp_handler = xtensa_breakpoint_handler;
|
||||
cc->disas_set_info = xtensa_cpu_disas_set_info;
|
||||
cc->tcg_initialize = xtensa_translate_init;
|
||||
dc->vmsd = &vmstate_xtensa_cpu;
|
||||
}
|
||||
|
|
|
@ -37,6 +37,7 @@
|
|||
#include "cpu-qom.h"
|
||||
#include "exec/cpu-defs.h"
|
||||
#include "fpu/softfloat.h"
|
||||
#include "xtensa-isa.h"
|
||||
|
||||
#define NB_MMU_MODES 4
|
||||
|
||||
|
@ -107,6 +108,7 @@ enum {
|
|||
};
|
||||
|
||||
enum {
|
||||
EXPSTATE = 230,
|
||||
THREADPTR = 231,
|
||||
FCR = 232,
|
||||
FSR = 233,
|
||||
|
@ -126,6 +128,7 @@ enum {
|
|||
WINDOW_BASE = 72,
|
||||
WINDOW_START = 73,
|
||||
PTEVADDR = 83,
|
||||
MMID = 89,
|
||||
RASID = 90,
|
||||
ITLBCFG = 91,
|
||||
DTLBCFG = 92,
|
||||
|
@ -133,6 +136,7 @@ enum {
|
|||
MEMCTL = 97,
|
||||
CACHEATTR = 98,
|
||||
ATOMCTL = 99,
|
||||
DDR = 104,
|
||||
IBREAKA = 128,
|
||||
DBREAKA = 144,
|
||||
DBREAKC = 160,
|
||||
|
@ -205,6 +209,8 @@ enum {
|
|||
#define MEMCTL_DSNP 0x2
|
||||
#define MEMCTL_IL0EN 0x1
|
||||
|
||||
#define MAX_INSN_LENGTH 64
|
||||
#define MAX_OPCODE_ARGS 16
|
||||
#define MAX_NAREG 64
|
||||
#define MAX_NINTERRUPT 32
|
||||
#define MAX_NLEVEL 6
|
||||
|
@ -330,6 +336,24 @@ typedef struct XtensaMemory {
|
|||
} location[MAX_NMEMORY];
|
||||
} XtensaMemory;
|
||||
|
||||
typedef struct DisasContext DisasContext;
|
||||
typedef void (*XtensaOpcodeOp)(DisasContext *dc, const uint32_t arg[],
|
||||
const uint32_t par[]);
|
||||
|
||||
typedef struct XtensaOpcodeOps {
|
||||
const char *name;
|
||||
XtensaOpcodeOp translate;
|
||||
const uint32_t *par;
|
||||
} XtensaOpcodeOps;
|
||||
|
||||
typedef struct XtensaOpcodeTranslators {
|
||||
unsigned num_opcodes;
|
||||
const XtensaOpcodeOps *opcode;
|
||||
} XtensaOpcodeTranslators;
|
||||
|
||||
extern const XtensaOpcodeTranslators xtensa_core_opcodes;
|
||||
extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes;
|
||||
|
||||
struct XtensaConfig {
|
||||
const char *name;
|
||||
uint64_t options;
|
||||
|
@ -370,6 +394,11 @@ struct XtensaConfig {
|
|||
|
||||
uint32_t configid[2];
|
||||
|
||||
void *isa_internal;
|
||||
xtensa_isa isa;
|
||||
XtensaOpcodeOps **opcode_ops;
|
||||
const XtensaOpcodeTranslators **opcode_translators;
|
||||
|
||||
uint32_t clock_freq_khz;
|
||||
|
||||
xtensa_tlb itlb;
|
||||
|
@ -522,6 +551,8 @@ static inline void xtensa_select_static_vectors(CPUXtensaState *env,
|
|||
env->static_vectors = n;
|
||||
}
|
||||
void xtensa_runstall(CPUXtensaState *env, bool runstall);
|
||||
XtensaOpcodeOps *xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t,
|
||||
const char *opcode);
|
||||
|
||||
#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
|
||||
#define XTENSA_OPTION_ALL (~(uint64_t)0)
|
||||
|
|
|
@ -52,10 +52,47 @@ static void xtensa_core_class_init(ObjectClass *oc, void *data)
|
|||
cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
|
||||
}
|
||||
|
||||
static void init_libisa(XtensaConfig *config)
|
||||
{
|
||||
unsigned i, j;
|
||||
unsigned opcodes;
|
||||
|
||||
config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL);
|
||||
assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH);
|
||||
opcodes = xtensa_isa_num_opcodes(config->isa);
|
||||
config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes);
|
||||
|
||||
for (i = 0; i < opcodes; ++i) {
|
||||
const char *opc_name = xtensa_opcode_name(config->isa, i);
|
||||
XtensaOpcodeOps *ops = NULL;
|
||||
|
||||
assert(xtensa_opcode_num_operands(config->isa, i) <= MAX_OPCODE_ARGS);
|
||||
if (!config->opcode_translators) {
|
||||
ops = xtensa_find_opcode_ops(&xtensa_core_opcodes, opc_name);
|
||||
} else {
|
||||
for (j = 0; !ops && config->opcode_translators[j]; ++j) {
|
||||
ops = xtensa_find_opcode_ops(config->opcode_translators[j],
|
||||
opc_name);
|
||||
}
|
||||
}
|
||||
#ifdef DEBUG
|
||||
if (ops == NULL) {
|
||||
fprintf(stderr,
|
||||
"opcode translator not found for %s's opcode '%s'\n",
|
||||
config->name, opc_name);
|
||||
}
|
||||
#endif
|
||||
config->opcode_ops[i] = ops;
|
||||
}
|
||||
}
|
||||
|
||||
void xtensa_finalize_config(XtensaConfig *config)
|
||||
{
|
||||
unsigned i, n = 0;
|
||||
|
||||
if (config->isa_internal) {
|
||||
init_libisa(config);
|
||||
}
|
||||
if (config->gdb_regmap.num_regs) {
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -23,6 +23,17 @@ tar -xf "$OVERLAY" -C "$TARGET" --strip-components=1 \
|
|||
--xform='s/core/core-isa/' config/core.h
|
||||
tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \
|
||||
sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.c
|
||||
#
|
||||
# Fix up known issues in the xtensa-modules.c
|
||||
#
|
||||
tar -xf "$OVERLAY" -O binutils/xtensa-modules.c | \
|
||||
sed -e 's/\(xtensa_opcode_encode_fn.*\[\] =\)/static \1/' \
|
||||
-e '/^int num_bypass_groups()/,/}/d' \
|
||||
-e '/^int num_bypass_group_chunks()/,/}/d' \
|
||||
-e '/^uint32 \*bypass_entry(int i)/,/}/d' \
|
||||
-e '/^#include "ansidecl.h"/d' \
|
||||
-e '/^Slot_[a-zA-Z0-9_]\+_decode (const xtensa_insnbuf insn)/,/^}/s/^ return 0;$/ return XTENSA_UNDEFINED;/' \
|
||||
> "$TARGET"/xtensa-modules.c
|
||||
|
||||
cat <<EOF > "${TARGET}.c"
|
||||
#include "qemu/osdep.h"
|
||||
|
@ -35,6 +46,9 @@ cat <<EOF > "${TARGET}.c"
|
|||
#include "core-$NAME/core-isa.h"
|
||||
#include "overlay_tool.h"
|
||||
|
||||
#define xtensa_modules xtensa_modules_$NAME
|
||||
#include "core-$NAME/xtensa-modules.c"
|
||||
|
||||
static XtensaConfig $NAME __attribute__((unused)) = {
|
||||
.name = "$NAME",
|
||||
.gdb_regmap = {
|
||||
|
@ -42,6 +56,7 @@ static XtensaConfig $NAME __attribute__((unused)) = {
|
|||
#include "core-$NAME/gdb-config.c"
|
||||
}
|
||||
},
|
||||
.isa_internal = &xtensa_modules,
|
||||
.clock_freq_khz = $FREQ,
|
||||
DEFAULT_SECTIONS
|
||||
};
|
||||
|
|
|
@ -249,7 +249,7 @@ void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
|
|||
if (windowstart & ((1 << callinc) - 1)) {
|
||||
HELPER(window_check)(env, pc, callinc);
|
||||
}
|
||||
env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
|
||||
env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - imm;
|
||||
rotate_window(env, callinc);
|
||||
env->sregs[WINDOW_START] |=
|
||||
windowstart_bit(env->sregs[WINDOW_BASE], env);
|
||||
|
|
File diff suppressed because it is too large
Load diff
231
target/xtensa/xtensa-isa-internal.h
Normal file
231
target/xtensa/xtensa-isa-internal.h
Normal file
|
@ -0,0 +1,231 @@
|
|||
/* Internal definitions for the Xtensa ISA library.
|
||||
*
|
||||
* Copyright (c) 2004-2011 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef XTENSA_ISA_INTERNAL_H
|
||||
#define XTENSA_ISA_INTERNAL_H
|
||||
|
||||
#ifndef uint32
|
||||
#define uint32 uint32_t
|
||||
#endif
|
||||
|
||||
/* Flags. */
|
||||
|
||||
#define XTENSA_OPERAND_IS_REGISTER 0x00000001
|
||||
#define XTENSA_OPERAND_IS_PCRELATIVE 0x00000002
|
||||
#define XTENSA_OPERAND_IS_INVISIBLE 0x00000004
|
||||
#define XTENSA_OPERAND_IS_UNKNOWN 0x00000008
|
||||
|
||||
#define XTENSA_OPCODE_IS_BRANCH 0x00000001
|
||||
#define XTENSA_OPCODE_IS_JUMP 0x00000002
|
||||
#define XTENSA_OPCODE_IS_LOOP 0x00000004
|
||||
#define XTENSA_OPCODE_IS_CALL 0x00000008
|
||||
|
||||
#define XTENSA_STATE_IS_EXPORTED 0x00000001
|
||||
#define XTENSA_STATE_IS_SHARED_OR 0x00000002
|
||||
|
||||
#define XTENSA_INTERFACE_HAS_SIDE_EFFECT 0x00000001
|
||||
|
||||
/* Function pointer typedefs */
|
||||
typedef void (*xtensa_format_encode_fn)(xtensa_insnbuf);
|
||||
typedef void (*xtensa_get_slot_fn)(const xtensa_insnbuf, xtensa_insnbuf);
|
||||
typedef void (*xtensa_set_slot_fn)(xtensa_insnbuf, const xtensa_insnbuf);
|
||||
typedef int (*xtensa_opcode_decode_fn)(const xtensa_insnbuf);
|
||||
typedef uint32_t (*xtensa_get_field_fn)(const xtensa_insnbuf);
|
||||
typedef void (*xtensa_set_field_fn)(xtensa_insnbuf, uint32_t);
|
||||
typedef int (*xtensa_immed_decode_fn)(uint32_t *);
|
||||
typedef int (*xtensa_immed_encode_fn)(uint32_t *);
|
||||
typedef int (*xtensa_do_reloc_fn)(uint32_t *, uint32_t);
|
||||
typedef int (*xtensa_undo_reloc_fn)(uint32_t *, uint32_t);
|
||||
typedef void (*xtensa_opcode_encode_fn)(xtensa_insnbuf);
|
||||
typedef int (*xtensa_format_decode_fn)(const xtensa_insnbuf);
|
||||
typedef int (*xtensa_length_decode_fn)(const unsigned char *);
|
||||
|
||||
typedef struct xtensa_format_internal_struct {
|
||||
const char *name; /* Instruction format name. */
|
||||
int length; /* Instruction length in bytes. */
|
||||
xtensa_format_encode_fn encode_fn;
|
||||
int num_slots;
|
||||
int *slot_id; /* Array[num_slots] of slot IDs. */
|
||||
} xtensa_format_internal;
|
||||
|
||||
typedef struct xtensa_slot_internal_struct {
|
||||
const char *name; /* Not necessarily unique. */
|
||||
const char *format;
|
||||
int position;
|
||||
xtensa_get_slot_fn get_fn;
|
||||
xtensa_set_slot_fn set_fn;
|
||||
xtensa_get_field_fn *get_field_fns; /* Array[field_id]. */
|
||||
xtensa_set_field_fn *set_field_fns; /* Array[field_id]. */
|
||||
xtensa_opcode_decode_fn opcode_decode_fn;
|
||||
const char *nop_name;
|
||||
} xtensa_slot_internal;
|
||||
|
||||
typedef struct xtensa_operand_internal_struct {
|
||||
const char *name;
|
||||
int field_id;
|
||||
xtensa_regfile regfile; /* Register file. */
|
||||
int num_regs; /* Usually 1; 2 for reg pairs, etc. */
|
||||
uint32_t flags; /* See XTENSA_OPERAND_* flags. */
|
||||
xtensa_immed_encode_fn encode; /* Encode the operand value. */
|
||||
xtensa_immed_decode_fn decode; /* Decode the value from the field. */
|
||||
xtensa_do_reloc_fn do_reloc; /* Perform a PC-relative reloc. */
|
||||
xtensa_undo_reloc_fn undo_reloc; /* Undo a PC-relative relocation. */
|
||||
} xtensa_operand_internal;
|
||||
|
||||
typedef struct xtensa_arg_internal_struct {
|
||||
union {
|
||||
int operand_id; /* For normal operands. */
|
||||
xtensa_state state; /* For stateOperands. */
|
||||
} u;
|
||||
char inout; /* Direction: 'i', 'o', or 'm'. */
|
||||
} xtensa_arg_internal;
|
||||
|
||||
typedef struct xtensa_iclass_internal_struct {
|
||||
int num_operands; /* Size of "operands" array. */
|
||||
xtensa_arg_internal *operands; /* Array[num_operands]. */
|
||||
|
||||
int num_stateOperands; /* Size of "stateOperands" array. */
|
||||
xtensa_arg_internal *stateOperands; /* Array[num_stateOperands]. */
|
||||
|
||||
int num_interfaceOperands; /* Size of "interfaceOperands". */
|
||||
xtensa_interface *interfaceOperands; /* Array[num_interfaceOperands]. */
|
||||
} xtensa_iclass_internal;
|
||||
|
||||
typedef struct xtensa_opcode_internal_struct {
|
||||
const char *name; /* Opcode mnemonic. */
|
||||
int iclass_id; /* Iclass for this opcode. */
|
||||
uint32_t flags; /* See XTENSA_OPCODE_* flags. */
|
||||
xtensa_opcode_encode_fn *encode_fns; /* Array[slot_id]. */
|
||||
int num_funcUnit_uses; /* Number of funcUnit_use entries. */
|
||||
xtensa_funcUnit_use *funcUnit_uses; /* Array[num_funcUnit_uses]. */
|
||||
} xtensa_opcode_internal;
|
||||
|
||||
typedef struct xtensa_regfile_internal_struct {
|
||||
const char *name; /* Full name of the regfile. */
|
||||
const char *shortname; /* Abbreviated name. */
|
||||
xtensa_regfile parent; /* View parent (or identity). */
|
||||
int num_bits; /* Width of the registers. */
|
||||
int num_entries; /* Number of registers. */
|
||||
} xtensa_regfile_internal;
|
||||
|
||||
typedef struct xtensa_interface_internal_struct {
|
||||
const char *name; /* Interface name. */
|
||||
int num_bits; /* Width of the interface. */
|
||||
uint32_t flags; /* See XTENSA_INTERFACE_* flags. */
|
||||
int class_id; /* Class of related interfaces. */
|
||||
char inout; /* "i" or "o". */
|
||||
} xtensa_interface_internal;
|
||||
|
||||
typedef struct xtensa_funcUnit_internal_struct {
|
||||
const char *name; /* Functional unit name. */
|
||||
int num_copies; /* Number of instances. */
|
||||
} xtensa_funcUnit_internal;
|
||||
|
||||
typedef struct xtensa_state_internal_struct {
|
||||
const char *name; /* State name. */
|
||||
int num_bits; /* Number of state bits. */
|
||||
uint32_t flags; /* See XTENSA_STATE_* flags. */
|
||||
} xtensa_state_internal;
|
||||
|
||||
typedef struct xtensa_sysreg_internal_struct {
|
||||
const char *name; /* Register name. */
|
||||
int number; /* Register number. */
|
||||
int is_user; /* Non-zero if a "user register". */
|
||||
} xtensa_sysreg_internal;
|
||||
|
||||
typedef struct xtensa_lookup_entry_struct {
|
||||
const char *key;
|
||||
union {
|
||||
xtensa_opcode opcode; /* Internal opcode number. */
|
||||
xtensa_sysreg sysreg; /* Internal sysreg number. */
|
||||
xtensa_state state; /* Internal state number. */
|
||||
xtensa_interface intf; /* Internal interface number. */
|
||||
xtensa_funcUnit fun; /* Internal funcUnit number. */
|
||||
} u;
|
||||
} xtensa_lookup_entry;
|
||||
|
||||
typedef struct xtensa_isa_internal_struct {
|
||||
int is_big_endian; /* Endianness. */
|
||||
int insn_size; /* Maximum length in bytes. */
|
||||
int insnbuf_size; /* Number of insnbuf_words. */
|
||||
|
||||
int num_formats;
|
||||
xtensa_format_internal *formats;
|
||||
xtensa_format_decode_fn format_decode_fn;
|
||||
xtensa_length_decode_fn length_decode_fn;
|
||||
|
||||
int num_slots;
|
||||
xtensa_slot_internal *slots;
|
||||
|
||||
int num_fields;
|
||||
|
||||
int num_operands;
|
||||
xtensa_operand_internal *operands;
|
||||
|
||||
int num_iclasses;
|
||||
xtensa_iclass_internal *iclasses;
|
||||
|
||||
int num_opcodes;
|
||||
xtensa_opcode_internal *opcodes;
|
||||
xtensa_lookup_entry *opname_lookup_table;
|
||||
|
||||
int num_regfiles;
|
||||
xtensa_regfile_internal *regfiles;
|
||||
|
||||
int num_states;
|
||||
xtensa_state_internal *states;
|
||||
xtensa_lookup_entry *state_lookup_table;
|
||||
|
||||
int num_sysregs;
|
||||
xtensa_sysreg_internal *sysregs;
|
||||
xtensa_lookup_entry *sysreg_lookup_table;
|
||||
|
||||
/*
|
||||
* The current Xtensa ISA only supports 256 of each kind of sysreg so
|
||||
* we can get away with implementing lookups with tables indexed by
|
||||
* the register numbers. If we ever allow larger sysreg numbers, this
|
||||
* may have to be reimplemented. The first entry in the following
|
||||
* arrays corresponds to "special" registers and the second to "user"
|
||||
* registers.
|
||||
*/
|
||||
int max_sysreg_num[2];
|
||||
xtensa_sysreg *sysreg_table[2];
|
||||
|
||||
int num_interfaces;
|
||||
xtensa_interface_internal *interfaces;
|
||||
xtensa_lookup_entry *interface_lookup_table;
|
||||
|
||||
int num_funcUnits;
|
||||
xtensa_funcUnit_internal *funcUnits;
|
||||
xtensa_lookup_entry *funcUnit_lookup_table;
|
||||
|
||||
int num_stages; /* Number of pipe stages. */
|
||||
} xtensa_isa_internal;
|
||||
|
||||
int xtensa_isa_name_compare(const void *, const void *);
|
||||
|
||||
extern xtensa_isa_status xtisa_errno;
|
||||
extern char xtisa_error_msg[];
|
||||
|
||||
#endif /* !XTENSA_ISA_INTERNAL_H */
|
1745
target/xtensa/xtensa-isa.c
Normal file
1745
target/xtensa/xtensa-isa.c
Normal file
File diff suppressed because it is too large
Load diff
1
target/xtensa/xtensa-isa.h
Normal file
1
target/xtensa/xtensa-isa.h
Normal file
|
@ -0,0 +1 @@
|
|||
#include <hw/xtensa/xtensa-isa.h>
|
|
@ -44,7 +44,6 @@ test_end
|
|||
|
||||
test_sr acchi, 1
|
||||
test_sr acclo, 1
|
||||
test_sr /*memctl*/97, 0
|
||||
test_sr_mask /*atomctl*/99, 0, 0
|
||||
test_sr_mask /*br*/4, 0, 0
|
||||
test_sr_mask /*cacheattr*/98, 0, 0
|
||||
|
@ -76,6 +75,7 @@ test_sr lcount, 1
|
|||
test_sr lend, 1
|
||||
test_sr litbase, 1
|
||||
test_sr m0, 1
|
||||
test_sr_mask /*memctl*/97, 0, 0
|
||||
test_sr misc0, 1
|
||||
test_sr_mask /*prefctl*/40, 0, 0
|
||||
test_sr_mask /*prid*/235, 0, 1
|
||||
|
|
Loading…
Reference in a new issue