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x86 queue, 2020-12-17

Browse source 
Features:
 * AVX512_FP16 feature (Cathy Zhang)
 
 Cleanups:
 * accel code cleanup (Claudio Fontana)
 * hyperv initialization cleanup (Vitaly Kuznetsov)
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Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging

x86 queue, 2020-12-17

Features:
* AVX512_FP16 feature (Cathy Zhang)

Cleanups:
* accel code cleanup (Claudio Fontana)
* hyperv initialization cleanup (Vitaly Kuznetsov)

# gpg: Signature made Thu 17 Dec 2020 18:44:45 GMT
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost-gl/tags/x86-next-pull-request:
  cpu: Remove unnecessary noop methods
  tcg: Make CPUClass.debug_excp_handler optional
  tcg: make CPUClass.cpu_exec_* optional
  tcg: cpu_exec_{enter,exit} helpers
  i386: tcg: remove inline from cpu_load_eflags
  i386: move TCG cpu class initialization to tcg/
  x86/cpu: Add AVX512_FP16 cpu feature
  i386: move hyperv_limits initialization to x86_cpu_realizefn()
  i386: move hyperv_version_id initialization to x86_cpu_realizefn()
  i386: move hyperv_interface_id initialization to x86_cpu_realizefn()
  i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()
  i386: move cpu dump out of helper.c into cpu-dump.c
  i386: move TCG accel files into tcg/
  i386: hvf: remove stale MAINTAINERS entry for old hvf stubs
  i386: move hax accel files into hax/
  i386: move whpx accel files into whpx/
  i386: move kvm accel files into kvm/

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-12-17 18:53:36 +00:00
parent af3f37319c 9fb75013d8
commit 75ee62ac60
63 changed files with 956 additions and 766 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
MAINTAINERS
View file

@ -426,7 +426,7 @@ M: Paolo Bonzini <pbonzini@redhat.com>
M: Marcelo Tosatti <mtosatti@redhat.com>
L: kvm@vger.kernel.org
S: Supported
F: target/i386/kvm.c
F: target/i386/kvm/
F: scripts/kvm/vmxcap
Guest CPU Cores (other accelerators)
@ -445,18 +445,13 @@ M: Cameron Esfahani <dirty@apple.com>
M: Roman Bolshakov <r.bolshakov@yadro.com>
W: https://wiki.qemu.org/Features/HVF
S: Maintained
F: accel/stubs/hvf-stub.c
F: target/i386/hvf/
F: include/sysemu/hvf.h
WHPX CPUs
M: Sunil Muthuswamy <sunilmut@microsoft.com>
S: Supported
F: target/i386/whpx-all.c
F: target/i386/whpx-apic.c
F: target/i386/whpx-cpus.c
F: target/i386/whp-dispatch.h
F: accel/stubs/whpx-stub.c
F: target/i386/whpx/
F: include/sysemu/whpx.h
Guest CPU Cores (Xen)
@ -496,7 +491,7 @@ W: https://github.com/intel/haxm/issues
S: Maintained
F: accel/stubs/hax-stub.c
F: include/sysemu/hax.h
F: target/i386/hax-*
F: target/i386/hax/
Hosts
-----

34
accel/tcg/cpu-exec.c
View file

@ -236,9 +236,26 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
}
#endif
void cpu_exec_step_atomic(CPUState *cpu)
static void cpu_exec_enter(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->cpu_exec_enter) {
cc->cpu_exec_enter(cpu);
}
}
static void cpu_exec_exit(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->cpu_exec_exit) {
cc->cpu_exec_exit(cpu);
}
}
void cpu_exec_step_atomic(CPUState *cpu)
{
TranslationBlock *tb;
target_ulong cs_base, pc;
uint32_t flags;
@ -257,11 +274,11 @@ void cpu_exec_step_atomic(CPUState *cpu)
/* Since we got here, we know that parallel_cpus must be true. */
parallel_cpus = false;
cc->cpu_exec_enter(cpu);
cpu_exec_enter(cpu);
/* execute the generated code */
trace_exec_tb(tb, pc);
cpu_tb_exec(cpu, tb);
cc->cpu_exec_exit(cpu);
cpu_exec_exit(cpu);
} else {
/*
* The mmap_lock is dropped by tb_gen_code if it runs out of
@ -465,7 +482,9 @@ static inline void cpu_handle_debug_exception(CPUState *cpu)
}
}
cc->debug_excp_handler(cpu);
if (cc->debug_excp_handler) {
cc->debug_excp_handler(cpu);
}
}
static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
@ -606,7 +625,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
True when it is, and we should restart on a new TB,
and via longjmp via cpu_loop_exit. */
else {
if (cc->cpu_exec_interrupt(cpu, interrupt_request)) {
if (cc->cpu_exec_interrupt &&
cc->cpu_exec_interrupt(cpu, interrupt_request)) {
if (need_replay_interrupt(interrupt_request)) {
replay_interrupt();
}
@ -713,7 +733,7 @@ int cpu_exec(CPUState *cpu)
rcu_read_lock();
cc->cpu_exec_enter(cpu);
cpu_exec_enter(cpu);
/* Calculate difference between guest clock and host clock.
* This delay includes the delay of the last cycle, so
@ -775,7 +795,7 @@ int cpu_exec(CPUState *cpu)
}
}
cc->cpu_exec_exit(cpu);
cpu_exec_exit(cpu);
rcu_read_unlock();
return ret;

13
hw/core/cpu.c
View file

@ -199,15 +199,6 @@ static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
return target_words_bigendian();
}
static void cpu_common_noop(CPUState *cpu)
{
}
static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req)
{
return false;
}
#if !defined(CONFIG_USER_ONLY)
GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
{
@ -425,11 +416,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
k->debug_excp_handler = cpu_common_noop;
k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
k->cpu_exec_enter = cpu_common_noop;
k->cpu_exec_exit = cpu_common_noop;
k->cpu_exec_interrupt = cpu_common_exec_interrupt;
k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;

2
hw/i386/fw_cfg.c
View file

@ -21,7 +21,7 @@
#include "hw/timer/hpet.h"
#include "hw/nvram/fw_cfg.h"
#include "e820_memory_layout.h"
#include "kvm_i386.h"
#include "kvm/kvm_i386.h"
#include CONFIG_DEVICES
struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};

2
hw/i386/intel_iommu.c
View file

@ -37,7 +37,7 @@
#include "sysemu/kvm.h"
#include "sysemu/sysemu.h"
#include "hw/i386/apic_internal.h"
#include "kvm_i386.h"
#include "kvm/kvm_i386.h"
#include "migration/vmstate.h"
#include "trace.h"

2
hw/i386/kvm/apic.c
View file

@ -17,7 +17,7 @@
#include "hw/pci/msi.h"
#include "sysemu/hw_accel.h"
#include "sysemu/kvm.h"
#include "target/i386/kvm_i386.h"
#include "kvm/kvm_i386.h"
static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic,
int reg_id, uint32_t val)

2
hw/i386/kvm/clock.c
View file

@ -20,7 +20,7 @@
#include "sysemu/kvm.h"
#include "sysemu/runstate.h"
#include "sysemu/hw_accel.h"
#include "kvm_i386.h"
#include "kvm/kvm_i386.h"
#include "migration/vmstate.h"
#include "hw/sysbus.h"
#include "hw/kvm/clock.h"

2
hw/i386/microvm.c
View file

@ -51,7 +51,7 @@
#include "cpu.h"
#include "elf.h"
#include "kvm_i386.h"
#include "kvm/kvm_i386.h"
#include "hw/xen/start_info.h"
#define MICROVM_QBOOT_FILENAME "qboot.rom"

2
hw/i386/pc.c
View file

@ -61,7 +61,7 @@
#include "sysemu/qtest.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "kvm_i386.h"
#include "kvm/kvm_i386.h"
#include "hw/xen/xen.h"
#include "hw/xen/start_info.h"
#include "ui/qemu-spice.h"

2
hw/i386/x86.c
View file

@ -54,7 +54,7 @@
#include "elf.h"
#include "standard-headers/asm-x86/bootparam.h"
#include CONFIG_DEVICES
#include "kvm_i386.h"
#include "kvm/kvm_i386.h"
/* Physical Address of PVH entry point read from kernel ELF NOTE */
static size_t pvh_start_addr;

1
meson.build
View file

@ -1497,6 +1497,7 @@ trace_events_subdirs += [
'target/arm',
'target/hppa',
'target/i386',
'target/i386/kvm',
'target/mips',
'target/ppc',
'target/riscv',

537
target/i386/cpu-dump.c Normal file
View file

@ -0,0 +1,537 @@
/*
* i386 CPU dump to FILE
*
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "qemu/qemu-print.h"
#ifndef CONFIG_USER_ONLY
#include "hw/i386/apic_internal.h"
#endif
/***********************************************************/
/* x86 debug */
static const char *cc_op_str[CC_OP_NB] = {
"DYNAMIC",
"EFLAGS",
"MULB",
"MULW",
"MULL",
"MULQ",
"ADDB",
"ADDW",
"ADDL",
"ADDQ",
"ADCB",
"ADCW",
"ADCL",
"ADCQ",
"SUBB",
"SUBW",
"SUBL",
"SUBQ",
"SBBB",
"SBBW",
"SBBL",
"SBBQ",
"LOGICB",
"LOGICW",
"LOGICL",
"LOGICQ",
"INCB",
"INCW",
"INCL",
"INCQ",
"DECB",
"DECW",
"DECL",
"DECQ",
"SHLB",
"SHLW",
"SHLL",
"SHLQ",
"SARB",
"SARW",
"SARL",
"SARQ",
"BMILGB",
"BMILGW",
"BMILGL",
"BMILGQ",
"ADCX",
"ADOX",
"ADCOX",
"CLR",
};
static void
cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f,
const char *name, struct SegmentCache *sc)
{
#ifdef TARGET_X86_64
if (env->hflags & HF_CS64_MASK) {
qemu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name,
sc->selector, sc->base, sc->limit,
sc->flags & 0x00ffff00);
} else
#endif
{
qemu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector,
(uint32_t)sc->base, sc->limit,
sc->flags & 0x00ffff00);
}
if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK))
goto done;
qemu_fprintf(f, " DPL=%d ",
(sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT);
if (sc->flags & DESC_S_MASK) {
if (sc->flags & DESC_CS_MASK) {
qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" :
((sc->flags & DESC_B_MASK) ? "CS32" : "CS16"));
qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-',
(sc->flags & DESC_R_MASK) ? 'R' : '-');
} else {
qemu_fprintf(f, (sc->flags & DESC_B_MASK
|| env->hflags & HF_LMA_MASK)
? "DS " : "DS16");
qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-',
(sc->flags & DESC_W_MASK) ? 'W' : '-');
}
qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-');
} else {
static const char *sys_type_name[2][16] = {
{ /* 32 bit mode */
"Reserved", "TSS16-avl", "LDT", "TSS16-busy",
"CallGate16", "TaskGate", "IntGate16", "TrapGate16",
"Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
"CallGate32", "Reserved", "IntGate32", "TrapGate32"
},
{ /* 64 bit mode */
"<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
"Reserved", "Reserved", "Reserved", "Reserved",
"TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
"Reserved", "IntGate64", "TrapGate64"
}
};
qemu_fprintf(f, "%s",
sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0]
[(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]);
}
done:
qemu_fprintf(f, "\n");
}
#ifndef CONFIG_USER_ONLY
/* ARRAY_SIZE check is not required because
* DeliveryMode(dm) has a size of 3 bit.
*/
static inline const char *dm2str(uint32_t dm)
{
static const char *str[] = {
"Fixed",
"...",
"SMI",
"...",
"NMI",
"INIT",
"...",
"ExtINT"
};
return str[dm];
}
static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer)
{
uint32_t dm = (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT;
qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s",
name, lvt,
lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi",
lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge",
lvt & APIC_LVT_MASKED ? "masked" : "",
lvt & APIC_LVT_DELIV_STS ? "pending" : "",
!is_timer ?
"" : lvt & APIC_LVT_TIMER_PERIODIC ?
"periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ?
"tsc-deadline" : "one-shot",
dm2str(dm));
if (dm != APIC_DM_NMI) {
qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK);
} else {
qemu_printf("\n");
}
}
/* ARRAY_SIZE check is not required because
* destination shorthand has a size of 2 bit.
*/
static inline const char *shorthand2str(uint32_t shorthand)
{
const char *str[] = {
"no-shorthand", "self", "all-self", "all"
};
return str[shorthand];
}
static inline uint8_t divider_conf(uint32_t divide_conf)
{
uint8_t divide_val = ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3);
return divide_val == 7 ? 1 : 2 << divide_val;
}
static inline void mask2str(char *str, uint32_t val, uint8_t size)
{
while (size--) {
*str++ = (val >> size) & 1 ? '1' : '0';
}
*str = 0;
}
#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16
static void dump_apic_icr(APICCommonState *s, CPUX86State *env)
{
uint32_t icr = s->icr[0], icr2 = s->icr[1];
uint8_t dest_shorthand = \
(icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT;
bool logical_mod = icr & APIC_ICR_DEST_MOD;
char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1];
uint32_t dest_field;
bool x2apic;
qemu_printf("ICR\t 0x%08x %s %s %s %s\n",
icr,
logical_mod ? "logical" : "physical",
icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge",
icr & APIC_ICR_LEVEL ? "assert" : "de-assert",
shorthand2str(dest_shorthand));
qemu_printf("ICR2\t 0x%08x", icr2);
if (dest_shorthand != 0) {
qemu_printf("\n");
return;
}
x2apic = env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC;
dest_field = x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT;
if (!logical_mod) {
if (x2apic) {
qemu_printf(" cpu %u (X2APIC ID)\n", dest_field);
} else {
qemu_printf(" cpu %u (APIC ID)\n",
dest_field & APIC_LOGDEST_XAPIC_ID);
}
return;
}
if (s->dest_mode == 0xf) { /* flat mode */
mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8);
qemu_printf(" mask %s (APIC ID)\n", apic_id_str);
} else if (s->dest_mode == 0) { /* cluster mode */
if (x2apic) {
mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16);
qemu_printf(" cluster %u mask %s (X2APIC ID)\n",
dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_str);
} else {
mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4);
qemu_printf(" cluster %u mask %s (APIC ID)\n",
dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_str);
}
}
}
static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab,
uint32_t *tmr_tab)
{
int i, empty = true;
qemu_printf("%s\t ", name);
for (i = 0; i < 256; i++) {
if (apic_get_bit(ireg_tab, i)) {
qemu_printf("%u%s ", i,
apic_get_bit(tmr_tab, i) ? "(level)" : "");
empty = false;
}
}
qemu_printf("%s\n", empty ? "(none)" : "");
}
void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
{
X86CPU *cpu = X86_CPU(cs);
APICCommonState *s = APIC_COMMON(cpu->apic_state);
if (!s) {
qemu_printf("local apic state not available\n");
return;
}
uint32_t *lvt = s->lvt;
qemu_printf("dumping local APIC state for CPU %-2u\n\n",
CPU(cpu)->cpu_index);
dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false);
dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false);
dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false);
dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false);
dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false);
dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true);
qemu_printf("Timer\t DCR=0x%x (divide by %u) initial_count = %u"
" current_count = %u\n",
s->divide_conf & APIC_DCR_MASK,
divider_conf(s->divide_conf),
s->initial_count, apic_get_current_count(s));
qemu_printf("SPIV\t 0x%08x APIC %s, focus=%s, spurious vec %u\n",
s->spurious_vec,
s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disabled",
s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off",
s->spurious_vec & APIC_VECTOR_MASK);
dump_apic_icr(s, &cpu->env);
qemu_printf("ESR\t 0x%08x\n", s->esr);
dump_apic_interrupt("ISR", s->isr, s->tmr);
dump_apic_interrupt("IRR", s->irr, s->tmr);
qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x",
s->arb_id, s->tpr, s->dest_mode, s->log_dest);
if (s->dest_mode == 0) {
qemu_printf("(cluster %u: id %u)",
s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT,
s->log_dest & APIC_LOGDEST_XAPIC_ID);
}
qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s));
}
#else
void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
{
}
#endif /* !CONFIG_USER_ONLY */
#define DUMP_CODE_BYTES_TOTAL 50
#define DUMP_CODE_BYTES_BACKWARD 20
void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
int eflags, i, nb;
char cc_op_name[32];
static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
eflags = cpu_compute_eflags(env);
#ifdef TARGET_X86_64
if (env->hflags & HF_CS64_MASK) {
qemu_fprintf(f, "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
"RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
"R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
"R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
"RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
env->regs[R_EAX],
env->regs[R_EBX],
env->regs[R_ECX],
env->regs[R_EDX],
env->regs[R_ESI],
env->regs[R_EDI],
env->regs[R_EBP],
env->regs[R_ESP],
env->regs[8],
env->regs[9],
env->regs[10],
env->regs[11],
env->regs[12],
env->regs[13],
env->regs[14],
env->regs[15],
env->eip, eflags,
eflags & DF_MASK ? 'D' : '-',
eflags & CC_O ? 'O' : '-',
eflags & CC_S ? 'S' : '-',
eflags & CC_Z ? 'Z' : '-',
eflags & CC_A ? 'A' : '-',
eflags & CC_P ? 'P' : '-',
eflags & CC_C ? 'C' : '-',
env->hflags & HF_CPL_MASK,
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
(env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
cs->halted);
} else
#endif
{
qemu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
"ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
"EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
(uint32_t)env->regs[R_EAX],
(uint32_t)env->regs[R_EBX],
(uint32_t)env->regs[R_ECX],
(uint32_t)env->regs[R_EDX],
(uint32_t)env->regs[R_ESI],
(uint32_t)env->regs[R_EDI],
(uint32_t)env->regs[R_EBP],
(uint32_t)env->regs[R_ESP],
(uint32_t)env->eip, eflags,
eflags & DF_MASK ? 'D' : '-',
eflags & CC_O ? 'O' : '-',
eflags & CC_S ? 'S' : '-',
eflags & CC_Z ? 'Z' : '-',
eflags & CC_A ? 'A' : '-',
eflags & CC_P ? 'P' : '-',
eflags & CC_C ? 'C' : '-',
env->hflags & HF_CPL_MASK,
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
(env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
cs->halted);
}
for(i = 0; i < 6; i++) {
cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]);
}
cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt);
cpu_x86_dump_seg_cache(env, f, "TR", &env->tr);
#ifdef TARGET_X86_64
if (env->hflags & HF_LMA_MASK) {
qemu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
env->gdt.base, env->gdt.limit);
qemu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
env->idt.base, env->idt.limit);
qemu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
(uint32_t)env->cr[0],
env->cr[2],
env->cr[3],
(uint32_t)env->cr[4]);
for(i = 0; i < 4; i++)
qemu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);
qemu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",
env->dr[6], env->dr[7]);
} else
#endif
{
qemu_fprintf(f, "GDT= %08x %08x\n",
(uint32_t)env->gdt.base, env->gdt.limit);
qemu_fprintf(f, "IDT= %08x %08x\n",
(uint32_t)env->idt.base, env->idt.limit);
qemu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
(uint32_t)env->cr[0],
(uint32_t)env->cr[2],
(uint32_t)env->cr[3],
(uint32_t)env->cr[4]);
for(i = 0; i < 4; i++) {
qemu_fprintf(f, "DR%d=" TARGET_FMT_lx " ", i, env->dr[i]);
}
qemu_fprintf(f, "\nDR6=" TARGET_FMT_lx " DR7=" TARGET_FMT_lx "\n",
env->dr[6], env->dr[7]);
}
if (flags & CPU_DUMP_CCOP) {
if ((unsigned)env->cc_op < CC_OP_NB)
snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
else
snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
#ifdef TARGET_X86_64
if (env->hflags & HF_CS64_MASK) {
qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
env->cc_src, env->cc_dst,
cc_op_name);
} else
#endif
{
qemu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
(uint32_t)env->cc_src, (uint32_t)env->cc_dst,
cc_op_name);
}
}
qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
if (flags & CPU_DUMP_FPU) {
int fptag;
fptag = 0;
for(i = 0; i < 8; i++) {
fptag |= ((!env->fptags[i]) << i);
}
update_mxcsr_from_sse_status(env);
qemu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
env->fpuc,
(env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
env->fpstt,
fptag,
env->mxcsr);
for(i=0;i<8;i++) {
CPU_LDoubleU u;
u.d = env->fpregs[i].d;
qemu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
i, u.l.lower, u.l.upper);
if ((i & 1) == 1)
qemu_fprintf(f, "\n");
else
qemu_fprintf(f, " ");
}
if (env->hflags & HF_CS64_MASK)
nb = 16;
else
nb = 8;
for(i=0;i<nb;i++) {
qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
i,
env->xmm_regs[i].ZMM_L(3),
env->xmm_regs[i].ZMM_L(2),
env->xmm_regs[i].ZMM_L(1),
env->xmm_regs[i].ZMM_L(0));
if ((i & 1) == 1)
qemu_fprintf(f, "\n");
else
qemu_fprintf(f, " ");
}
}
if (flags & CPU_DUMP_CODE) {
target_ulong base = env->segs[R_CS].base + env->eip;
target_ulong offs = MIN(env->eip, DUMP_CODE_BYTES_BACKWARD);
uint8_t code;
char codestr[3];
qemu_fprintf(f, "Code=");
for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) {
snprintf(codestr, sizeof(codestr), "%02x", code);
} else {
snprintf(codestr, sizeof(codestr), "??");
}
qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "",
i == offs ? "<" : "", codestr, i == offs ? ">" : "");
}
qemu_fprintf(f, "\n");
}
}

75
target/i386/cpu.c
View file

@ -24,6 +24,8 @@
#include "qemu/qemu-print.h"
#include "cpu.h"
#include "tcg/tcg-cpu.h"
#include "tcg/helper-tcg.h"
#include "exec/exec-all.h"
#include "sysemu/kvm.h"
#include "sysemu/reset.h"
@ -31,7 +33,7 @@
#include "sysemu/cpus.h"
#include "sysemu/xen.h"
#include "sysemu/whpx.h"
#include "kvm_i386.h"
#include "kvm/kvm_i386.h"
#include "sev_i386.h"
#include "qemu/error-report.h"
@ -979,7 +981,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"avx512-vp2intersect", NULL, "md-clear", NULL,
NULL, NULL, "serialize", NULL,
"tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, "avx512-fp16",
NULL, NULL, "spec-ctrl", "stibp",
NULL, "arch-capabilities", "core-capability", "ssbd",
},
@ -1521,7 +1523,8 @@ static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
cpu->env.features[FEAT_XSAVE_COMP_LO];
}
const char *get_register_name_32(unsigned int reg)
/* Return name of 32-bit register, from a R_* constant */
static const char *get_register_name_32(unsigned int reg)
{
if (reg >= CPU_NB_REGS32) {
return NULL;
@ -6544,6 +6547,40 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
}
}
static void x86_cpu_hyperv_realize(X86CPU *cpu)
{
size_t len;
/* Hyper-V vendor id */
if (!cpu->hyperv_vendor) {
memcpy(cpu->hyperv_vendor_id, "Microsoft Hv", 12);
} else {
len = strlen(cpu->hyperv_vendor);
if (len > 12) {
warn_report("hv-vendor-id truncated to 12 characters");
len = 12;
}
memset(cpu->hyperv_vendor_id, 0, 12);
memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len);
}
/* 'Hv#1' interface identification*/
cpu->hyperv_interface_id[0] = 0x31237648;
cpu->hyperv_interface_id[1] = 0;
cpu->hyperv_interface_id[2] = 0;
cpu->hyperv_interface_id[3] = 0;
/* Hypervisor system identity */
cpu->hyperv_version_id[0] = 0x00001bbc;
cpu->hyperv_version_id[1] = 0x00060001;
/* Hypervisor implementation limits */
cpu->hyperv_limits[0] = 64;
cpu->hyperv_limits[1] = 0;
cpu->hyperv_limits[2] = 0;
}
static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
@ -6715,6 +6752,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
env->cache_info_amd.l3_cache = &legacy_l3_cache;
}
/* Process Hyper-V enlightenments */
x86_cpu_hyperv_realize(cpu);
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
@ -7032,13 +7071,6 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.eip = value;
}
static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
X86CPU *cpu = X86_CPU(cs);
cpu->env.eip = tb->pc - tb->cs_base;
}
int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
{
X86CPU *cpu = X86_CPU(cs);
@ -7218,7 +7250,7 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
@ -7273,17 +7305,18 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->class_by_name = x86_cpu_class_by_name;
cc->parse_features = x86_cpu_parse_featurestr;
cc->has_work = x86_cpu_has_work;
#ifdef CONFIG_TCG
cc->do_interrupt = x86_cpu_do_interrupt;
cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
#endif
tcg_cpu_common_class_init(cc);
#endif /* CONFIG_TCG */
cc->dump_state = x86_cpu_dump_state;
cc->set_pc = x86_cpu_set_pc;
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->gdb_read_register = x86_cpu_gdb_read_register;
cc->gdb_write_register = x86_cpu_gdb_write_register;
cc->get_arch_id = x86_cpu_get_arch_id;
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
@ -7294,7 +7327,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->vmsd = &vmstate_x86_cpu;
#endif
#endif /* !CONFIG_USER_ONLY */
cc->gdb_arch_name = x86_gdb_arch_name;
#ifdef TARGET_X86_64
cc->gdb_core_xml_file = "i386-64bit.xml";
@ -7302,15 +7336,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
#else
cc->gdb_core_xml_file = "i386-32bit.xml";
cc->gdb_num_core_regs = 50;
#endif
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
cc->debug_excp_handler = breakpoint_handler;
#endif
cc->cpu_exec_enter = x86_cpu_exec_enter;
cc->cpu_exec_exit = x86_cpu_exec_exit;
#ifdef CONFIG_TCG
cc->tcg_initialize = tcg_x86_init;
cc->tlb_fill = x86_cpu_tlb_fill;
#endif
cc->disas_set_info = x86_disas_set_info;

97
target/i386/cpu.h
View file

@ -22,7 +22,7 @@
#include "sysemu/tcg.h"
#include "cpu-qom.h"
#include "hyperv-proto.h"
#include "kvm/hyperv-proto.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
@ -31,9 +31,6 @@
#define KVM_HAVE_MCE_INJECTION 1
/* Maximum instruction code size */
#define TARGET_MAX_INSN_SIZE 16
/* support for self modifying code even if the modified instruction is
close to the modifying instruction */
#define TARGET_HAS_PRECISE_SMC
@ -784,6 +781,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_SERIALIZE (1U << 14)
/* TSX Suspend Load Address Tracking instruction */
#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
/* AVX512_FP16 instruction */
#define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
/* Speculation Control */
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
/* Single Thread Indirect Branch Predictors */
@ -1659,11 +1658,15 @@ struct X86CPU {
uint64_t ucode_rev;
uint32_t hyperv_spinlock_attempts;
char *hyperv_vendor_id;
char *hyperv_vendor;
bool hyperv_synic_kvm_only;
uint64_t hyperv_features;
bool hyperv_passthrough;
OnOffAuto hyperv_no_nonarch_cs;
uint32_t hyperv_vendor_id[3];
uint32_t hyperv_interface_id[4];
uint32_t hyperv_version_id[4];
uint32_t hyperv_limits[3];
bool check_cpuid;
bool enforce_cpuid;
@ -1769,12 +1772,6 @@ struct X86CPU {
extern VMStateDescription vmstate_x86_cpu;
#endif
/**
* x86_cpu_do_interrupt:
* @cpu: vCPU the interrupt is to be handled by.
*/
void x86_cpu_do_interrupt(CPUState *cpu);
bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
@ -1797,9 +1794,6 @@ hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void x86_cpu_exec_enter(CPUState *cpu);
void x86_cpu_exec_exit(CPUState *cpu);
void x86_cpu_list(void);
int cpu_x86_support_mca_broadcast(CPUX86State *env);
@ -1924,9 +1918,6 @@ void host_cpuid(uint32_t function, uint32_t count,
void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
/* helper.c */
bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
#ifndef CONFIG_USER_ONLY
@ -1951,8 +1942,6 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
#endif
void breakpoint_handler(CPUState *cs);
/* will be suppressed */
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
@ -1962,16 +1951,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
/* hw/pc.c */
uint64_t cpu_get_tsc(CPUX86State *env);
/* XXX: This value should match the one returned by CPUID
* and in exec.c */
# if defined(TARGET_X86_64)
# define TCG_PHYS_ADDR_BITS 40
# else
# define TCG_PHYS_ADDR_BITS 36
# endif
#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_X86_CPU
@ -2008,25 +1987,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
#define CC_SRC2 (env->cc_src2)
#define CC_OP (env->cc_op)
/* n must be a constant to be efficient */
static inline target_long lshift(target_long x, int n)
{
if (n >= 0) {
return x << n;
} else {
return x >> (-n);
}
}
/* float macros */
#define FT0 (env->ft0)
#define ST0 (env->fpregs[env->fpstt].d)
#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
#define ST1 ST(1)
/* translate.c */
void tcg_x86_init(void);
typedef CPUX86State CPUArchState;
typedef X86CPU ArchCPU;
@ -2056,19 +2016,6 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
uint64_t status, uint64_t mcg_status, uint64_t addr,
uint64_t misc, int flags);
/* excp_helper.c */
void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
uintptr_t retaddr);
void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
int error_code);
void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
int error_code, uintptr_t retaddr);
void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
int error_code, int next_eip_addend);
/* cc_helper.c */
extern const uint8_t parity_table[256];
uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
static inline uint32_t cpu_compute_eflags(CPUX86State *env)
@ -2080,18 +2027,6 @@ static inline uint32_t cpu_compute_eflags(CPUX86State *env)
return eflags;
}
/* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
* after generating a call to a helper that uses this.
*/
static inline void cpu_load_eflags(CPUX86State *env, int eflags,
int update_mask)
{
CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
CC_OP = CC_OP_EFLAGS;
env->df = 1 - (2 * ((eflags >> 10) & 1));
env->eflags = (env->eflags & ~update_mask) |
(eflags & update_mask) | 0x2;
}
/* load efer and update the corresponding hflags. XXX: do consistency
checks with cpuid bits? */
@ -2180,16 +2115,6 @@ void helper_lock_init(void);
/* svm_helper.c */
void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
uint64_t param, uintptr_t retaddr);
void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
uint64_t exit_info_1, uintptr_t retaddr);
void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
/* seg_helper.c */
void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
/* smm_helper.c */
void do_smm_enter(X86CPU *cpu);
/* apic.c */
void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
@ -2228,14 +2153,10 @@ typedef int X86CPUVersion;
*/
void x86_cpu_set_default_version(X86CPUVersion version);
/* Return name of 32-bit register, from a R_* constant */
const char *get_register_name_32(unsigned int reg);
void enable_compat_apic_id_mode(void);
#define APIC_DEFAULT_ADDRESS 0xfee00000
#define APIC_SPACE_SIZE 0x100000
/* cpu-dump.c */
void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
/* cpu.c */

0
target/i386/hax-all.c → target/i386/hax/hax-all.c
View file

0
target/i386/hax-cpus.c → target/i386/hax/hax-cpus.c
View file

0
target/i386/hax-cpus.h → target/i386/hax/hax-cpus.h
View file

6
target/i386/hax-i386.h → target/i386/hax/hax-i386.h
View file

@ -84,13 +84,13 @@ void hax_memory_init(void);
#ifdef CONFIG_POSIX
#include "target/i386/hax-posix.h"
#include "hax-posix.h"
#endif
#ifdef CONFIG_WIN32
#include "target/i386/hax-windows.h"
#include "hax-windows.h"
#endif
#include "target/i386/hax-interface.h"
#include "hax-interface.h"
#endif

0
target/i386/hax-interface.h → target/i386/hax/hax-interface.h
View file

0
target/i386/hax-mem.c → target/i386/hax/hax-mem.c
View file

0
target/i386/hax-posix.c → target/i386/hax/hax-posix.c
View file

0
target/i386/hax-posix.h → target/i386/hax/hax-posix.h
View file

0
target/i386/hax-windows.c → target/i386/hax/hax-windows.c
View file

0
target/i386/hax-windows.h → target/i386/hax/hax-windows.h
View file

7
target/i386/hax/meson.build Normal file
View file

@ -0,0 +1,7 @@
i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files(
'hax-all.c',
'hax-mem.c',
'hax-cpus.c',
))
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c'))
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c'))

539
target/i386/helper.c
View file

@ -21,15 +21,11 @@
#include "qapi/qapi-events-run-state.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "qemu/qemu-print.h"
#include "sysemu/kvm.h"
#include "sysemu/runstate.h"
#include "kvm_i386.h"
#include "kvm/kvm_i386.h"
#ifndef CONFIG_USER_ONLY
#include "sysemu/tcg.h"
#include "sysemu/hw_accel.h"
#include "monitor/monitor.h"
#include "hw/i386/apic_internal.h"
#endif
void cpu_sync_bndcs_hflags(CPUX86State *env)
@ -88,518 +84,6 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env)
return 0;
}
/***********************************************************/
/* x86 debug */
static const char *cc_op_str[CC_OP_NB] = {
"DYNAMIC",
"EFLAGS",
"MULB",
"MULW",
"MULL",
"MULQ",
"ADDB",
"ADDW",
"ADDL",
"ADDQ",
"ADCB",
"ADCW",
"ADCL",
"ADCQ",
"SUBB",
"SUBW",
"SUBL",
"SUBQ",
"SBBB",
"SBBW",
"SBBL",
"SBBQ",
"LOGICB",
"LOGICW",
"LOGICL",
"LOGICQ",
"INCB",
"INCW",
"INCL",
"INCQ",
"DECB",
"DECW",
"DECL",
"DECQ",
"SHLB",
"SHLW",
"SHLL",
"SHLQ",
"SARB",
"SARW",
"SARL",
"SARQ",
"BMILGB",
"BMILGW",
"BMILGL",
"BMILGQ",
"ADCX",
"ADOX",
"ADCOX",
"CLR",
};
static void
cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f,
const char *name, struct SegmentCache *sc)
{
#ifdef TARGET_X86_64
if (env->hflags & HF_CS64_MASK) {
qemu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name,
sc->selector, sc->base, sc->limit,
sc->flags & 0x00ffff00);
} else
#endif
{
qemu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector,
(uint32_t)sc->base, sc->limit,
sc->flags & 0x00ffff00);
}
if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK))
goto done;
qemu_fprintf(f, " DPL=%d ",
(sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT);
if (sc->flags & DESC_S_MASK) {
if (sc->flags & DESC_CS_MASK) {
qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" :
((sc->flags & DESC_B_MASK) ? "CS32" : "CS16"));
qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-',
(sc->flags & DESC_R_MASK) ? 'R' : '-');
} else {
qemu_fprintf(f, (sc->flags & DESC_B_MASK
|| env->hflags & HF_LMA_MASK)
? "DS " : "DS16");
qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-',
(sc->flags & DESC_W_MASK) ? 'W' : '-');
}
qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-');
} else {
static const char *sys_type_name[2][16] = {
{ /* 32 bit mode */
"Reserved", "TSS16-avl", "LDT", "TSS16-busy",
"CallGate16", "TaskGate", "IntGate16", "TrapGate16",
"Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
"CallGate32", "Reserved", "IntGate32", "TrapGate32"
},
{ /* 64 bit mode */
"<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
"Reserved", "Reserved", "Reserved", "Reserved",
"TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
"Reserved", "IntGate64", "TrapGate64"
}
};
qemu_fprintf(f, "%s",
sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0]
[(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]);
}
done:
qemu_fprintf(f, "\n");
}
#ifndef CONFIG_USER_ONLY
/* ARRAY_SIZE check is not required because
* DeliveryMode(dm) has a size of 3 bit.
*/
static inline const char *dm2str(uint32_t dm)
{
static const char *str[] = {
"Fixed",
"...",
"SMI",
"...",
"NMI",
"INIT",
"...",
"ExtINT"
};
return str[dm];
}
static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer)
{
uint32_t dm = (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT;
qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s",
name, lvt,
lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi",
lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge",
lvt & APIC_LVT_MASKED ? "masked" : "",
lvt & APIC_LVT_DELIV_STS ? "pending" : "",
!is_timer ?
"" : lvt & APIC_LVT_TIMER_PERIODIC ?
"periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ?
"tsc-deadline" : "one-shot",
dm2str(dm));
if (dm != APIC_DM_NMI) {
qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK);
} else {
qemu_printf("\n");
}
}
/* ARRAY_SIZE check is not required because
* destination shorthand has a size of 2 bit.
*/
static inline const char *shorthand2str(uint32_t shorthand)
{
const char *str[] = {
"no-shorthand", "self", "all-self", "all"
};
return str[shorthand];
}
static inline uint8_t divider_conf(uint32_t divide_conf)
{
uint8_t divide_val = ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3);
return divide_val == 7 ? 1 : 2 << divide_val;
}
static inline void mask2str(char *str, uint32_t val, uint8_t size)
{
while (size--) {
*str++ = (val >> size) & 1 ? '1' : '0';
}
*str = 0;
}
#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16
static void dump_apic_icr(APICCommonState *s, CPUX86State *env)
{
uint32_t icr = s->icr[0], icr2 = s->icr[1];
uint8_t dest_shorthand = \
(icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT;
bool logical_mod = icr & APIC_ICR_DEST_MOD;
char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1];
uint32_t dest_field;
bool x2apic;
qemu_printf("ICR\t 0x%08x %s %s %s %s\n",
icr,
logical_mod ? "logical" : "physical",
icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge",
icr & APIC_ICR_LEVEL ? "assert" : "de-assert",
shorthand2str(dest_shorthand));
qemu_printf("ICR2\t 0x%08x", icr2);
if (dest_shorthand != 0) {
qemu_printf("\n");
return;
}
x2apic = env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC;
dest_field = x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT;
if (!logical_mod) {
if (x2apic) {
qemu_printf(" cpu %u (X2APIC ID)\n", dest_field);
} else {
qemu_printf(" cpu %u (APIC ID)\n",
dest_field & APIC_LOGDEST_XAPIC_ID);
}
return;
}
if (s->dest_mode == 0xf) { /* flat mode */
mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8);
qemu_printf(" mask %s (APIC ID)\n", apic_id_str);
} else if (s->dest_mode == 0) { /* cluster mode */
if (x2apic) {
mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16);
qemu_printf(" cluster %u mask %s (X2APIC ID)\n",
dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_str);
} else {
mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4);
qemu_printf(" cluster %u mask %s (APIC ID)\n",
dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_str);
}
}
}
static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab,
uint32_t *tmr_tab)
{
int i, empty = true;
qemu_printf("%s\t ", name);
for (i = 0; i < 256; i++) {
if (apic_get_bit(ireg_tab, i)) {
qemu_printf("%u%s ", i,
apic_get_bit(tmr_tab, i) ? "(level)" : "");
empty = false;
}
}
qemu_printf("%s\n", empty ? "(none)" : "");
}
void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
{
X86CPU *cpu = X86_CPU(cs);
APICCommonState *s = APIC_COMMON(cpu->apic_state);
if (!s) {
qemu_printf("local apic state not available\n");
return;
}
uint32_t *lvt = s->lvt;
qemu_printf("dumping local APIC state for CPU %-2u\n\n",
CPU(cpu)->cpu_index);
dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false);
dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false);
dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false);
dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false);
dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false);
dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true);
qemu_printf("Timer\t DCR=0x%x (divide by %u) initial_count = %u"
" current_count = %u\n",
s->divide_conf & APIC_DCR_MASK,
divider_conf(s->divide_conf),
s->initial_count, apic_get_current_count(s));
qemu_printf("SPIV\t 0x%08x APIC %s, focus=%s, spurious vec %u\n",
s->spurious_vec,
s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disabled",
s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off",
s->spurious_vec & APIC_VECTOR_MASK);
dump_apic_icr(s, &cpu->env);
qemu_printf("ESR\t 0x%08x\n", s->esr);
dump_apic_interrupt("ISR", s->isr, s->tmr);
dump_apic_interrupt("IRR", s->irr, s->tmr);
qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x",
s->arb_id, s->tpr, s->dest_mode, s->log_dest);
if (s->dest_mode == 0) {
qemu_printf("(cluster %u: id %u)",
s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT,
s->log_dest & APIC_LOGDEST_XAPIC_ID);
}
qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s));
}
#else
void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
{
}
#endif /* !CONFIG_USER_ONLY */
#define DUMP_CODE_BYTES_TOTAL 50
#define DUMP_CODE_BYTES_BACKWARD 20
void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
int eflags, i, nb;
char cc_op_name[32];
static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
eflags = cpu_compute_eflags(env);
#ifdef TARGET_X86_64
if (env->hflags & HF_CS64_MASK) {
qemu_fprintf(f, "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
"RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
"R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
"R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
"RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
env->regs[R_EAX],
env->regs[R_EBX],
env->regs[R_ECX],
env->regs[R_EDX],
env->regs[R_ESI],
env->regs[R_EDI],
env->regs[R_EBP],
env->regs[R_ESP],
env->regs[8],
env->regs[9],
env->regs[10],
env->regs[11],
env->regs[12],
env->regs[13],
env->regs[14],
env->regs[15],
env->eip, eflags,
eflags & DF_MASK ? 'D' : '-',
eflags & CC_O ? 'O' : '-',
eflags & CC_S ? 'S' : '-',
eflags & CC_Z ? 'Z' : '-',
eflags & CC_A ? 'A' : '-',
eflags & CC_P ? 'P' : '-',
eflags & CC_C ? 'C' : '-',
env->hflags & HF_CPL_MASK,
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
(env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
cs->halted);
} else
#endif
{
qemu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
"ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
"EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
(uint32_t)env->regs[R_EAX],
(uint32_t)env->regs[R_EBX],
(uint32_t)env->regs[R_ECX],
(uint32_t)env->regs[R_EDX],
(uint32_t)env->regs[R_ESI],
(uint32_t)env->regs[R_EDI],
(uint32_t)env->regs[R_EBP],
(uint32_t)env->regs[R_ESP],
(uint32_t)env->eip, eflags,
eflags & DF_MASK ? 'D' : '-',
eflags & CC_O ? 'O' : '-',
eflags & CC_S ? 'S' : '-',
eflags & CC_Z ? 'Z' : '-',
eflags & CC_A ? 'A' : '-',
eflags & CC_P ? 'P' : '-',
eflags & CC_C ? 'C' : '-',
env->hflags & HF_CPL_MASK,
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
(env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
cs->halted);
}
for(i = 0; i < 6; i++) {
cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]);
}
cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt);
cpu_x86_dump_seg_cache(env, f, "TR", &env->tr);
#ifdef TARGET_X86_64
if (env->hflags & HF_LMA_MASK) {
qemu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
env->gdt.base, env->gdt.limit);
qemu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
env->idt.base, env->idt.limit);
qemu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
(uint32_t)env->cr[0],
env->cr[2],
env->cr[3],
(uint32_t)env->cr[4]);
for(i = 0; i < 4; i++)
qemu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);
qemu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",
env->dr[6], env->dr[7]);
} else
#endif
{
qemu_fprintf(f, "GDT= %08x %08x\n",
(uint32_t)env->gdt.base, env->gdt.limit);
qemu_fprintf(f, "IDT= %08x %08x\n",
(uint32_t)env->idt.base, env->idt.limit);
qemu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
(uint32_t)env->cr[0],
(uint32_t)env->cr[2],
(uint32_t)env->cr[3],
(uint32_t)env->cr[4]);
for(i = 0; i < 4; i++) {
qemu_fprintf(f, "DR%d=" TARGET_FMT_lx " ", i, env->dr[i]);
}
qemu_fprintf(f, "\nDR6=" TARGET_FMT_lx " DR7=" TARGET_FMT_lx "\n",
env->dr[6], env->dr[7]);
}
if (flags & CPU_DUMP_CCOP) {
if ((unsigned)env->cc_op < CC_OP_NB)
snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
else
snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
#ifdef TARGET_X86_64
if (env->hflags & HF_CS64_MASK) {
qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
env->cc_src, env->cc_dst,
cc_op_name);
} else
#endif
{
qemu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
(uint32_t)env->cc_src, (uint32_t)env->cc_dst,
cc_op_name);
}
}
qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
if (flags & CPU_DUMP_FPU) {
int fptag;
fptag = 0;
for(i = 0; i < 8; i++) {
fptag |= ((!env->fptags[i]) << i);
}
update_mxcsr_from_sse_status(env);
qemu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
env->fpuc,
(env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
env->fpstt,
fptag,
env->mxcsr);
for(i=0;i<8;i++) {
CPU_LDoubleU u;
u.d = env->fpregs[i].d;
qemu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
i, u.l.lower, u.l.upper);
if ((i & 1) == 1)
qemu_fprintf(f, "\n");
else
qemu_fprintf(f, " ");
}
if (env->hflags & HF_CS64_MASK)
nb = 16;
else
nb = 8;
for(i=0;i<nb;i++) {
qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
i,
env->xmm_regs[i].ZMM_L(3),
env->xmm_regs[i].ZMM_L(2),
env->xmm_regs[i].ZMM_L(1),
env->xmm_regs[i].ZMM_L(0));
if ((i & 1) == 1)
qemu_fprintf(f, "\n");
else
qemu_fprintf(f, " ");
}
}
if (flags & CPU_DUMP_CODE) {
target_ulong base = env->segs[R_CS].base + env->eip;
target_ulong offs = MIN(env->eip, DUMP_CODE_BYTES_BACKWARD);
uint8_t code;
char codestr[3];
qemu_fprintf(f, "Code=");
for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) {
snprintf(codestr, sizeof(codestr), "%02x", code);
} else {
snprintf(codestr, sizeof(codestr), "??");
}
qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "",
i == offs ? "<" : "", codestr, i == offs ? ">" : "");
}
qemu_fprintf(f, "\n");
}
}
/***********************************************************/
/* x86 mmu */
/* XXX: add PGE support */
@ -1086,27 +570,6 @@ void do_cpu_sipi(X86CPU *cpu)
}
#endif
/* Frob eflags into and out of the CPU temporary format. */
void x86_cpu_exec_enter(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
env->df = 1 - (2 * ((env->eflags >> 10) & 1));
CC_OP = CC_OP_EFLAGS;
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
}
void x86_cpu_exec_exit(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
env->eflags = cpu_compute_eflags(env);
}
#ifndef CONFIG_USER_ONLY
uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr)
{

0
target/i386/hyperv-proto.h → target/i386/kvm/hyperv-proto.h
View file

0
target/i386/hyperv-stub.c → target/i386/kvm/hyperv-stub.c
View file

0
target/i386/hyperv.c → target/i386/kvm/hyperv.c
View file

0
target/i386/hyperv.h → target/i386/kvm/hyperv.h
View file

0
target/i386/kvm-stub.c → target/i386/kvm/kvm-stub.c
View file

70
target/i386/kvm.c → target/i386/kvm/kvm.c
View file

@ -1171,7 +1171,6 @@ static int hyperv_handle_properties(CPUState *cs,
CPUX86State *env = &cpu->env;
struct kvm_cpuid2 *cpuid;
struct kvm_cpuid_entry2 *c;
uint32_t signature[3];
uint32_t cpuid_i = 0;
int r;
@ -1208,12 +1207,44 @@ static int hyperv_handle_properties(CPUState *cs,
memcpy(cpuid_ent, &cpuid->entries[0],
cpuid->nent * sizeof(cpuid->entries[0]));
c = cpuid_find_entry(cpuid, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, 0);
if (c) {
cpu->hyperv_vendor_id[0] = c->ebx;
cpu->hyperv_vendor_id[1] = c->ecx;
cpu->hyperv_vendor_id[2] = c->edx;
}
c = cpuid_find_entry(cpuid, HV_CPUID_INTERFACE, 0);
if (c) {
cpu->hyperv_interface_id[0] = c->eax;
cpu->hyperv_interface_id[1] = c->ebx;
cpu->hyperv_interface_id[2] = c->ecx;
cpu->hyperv_interface_id[3] = c->edx;
}
c = cpuid_find_entry(cpuid, HV_CPUID_VERSION, 0);
if (c) {
cpu->hyperv_version_id[0] = c->eax;
cpu->hyperv_version_id[1] = c->ebx;
cpu->hyperv_version_id[2] = c->ecx;
cpu->hyperv_version_id[3] = c->edx;
}
c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
if (c) {
env->features[FEAT_HYPERV_EAX] = c->eax;
env->features[FEAT_HYPERV_EBX] = c->ebx;
env->features[FEAT_HYPERV_EDX] = c->edx;
}
c = cpuid_find_entry(cpuid, HV_CPUID_IMPLEMENT_LIMITS, 0);
if (c) {
cpu->hv_max_vps = c->eax;
cpu->hyperv_limits[0] = c->ebx;
cpu->hyperv_limits[1] = c->ecx;
cpu->hyperv_limits[2] = c->edx;
}
c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
if (c) {
env->features[FEAT_HV_RECOMM_EAX] = c->eax;
@ -1282,36 +1313,25 @@ static int hyperv_handle_properties(CPUState *cs,
c = &cpuid_ent[cpuid_i++];
c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
if (!cpu->hyperv_vendor_id) {
memcpy(signature, "Microsoft Hv", 12);
} else {
size_t len = strlen(cpu->hyperv_vendor_id);
if (len > 12) {
error_report("hv-vendor-id truncated to 12 characters");
len = 12;
}
memset(signature, 0, 12);
memcpy(signature, cpu->hyperv_vendor_id, len);
}
c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
c->ebx = signature[0];
c->ecx = signature[1];
c->edx = signature[2];
c->ebx = cpu->hyperv_vendor_id[0];
c->ecx = cpu->hyperv_vendor_id[1];
c->edx = cpu->hyperv_vendor_id[2];
c = &cpuid_ent[cpuid_i++];
c->function = HV_CPUID_INTERFACE;
memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
c->eax = signature[0];
c->ebx = 0;
c->ecx = 0;
c->edx = 0;
c->eax = cpu->hyperv_interface_id[0];
c->ebx = cpu->hyperv_interface_id[1];
c->ecx = cpu->hyperv_interface_id[2];
c->edx = cpu->hyperv_interface_id[3];
c = &cpuid_ent[cpuid_i++];
c->function = HV_CPUID_VERSION;
c->eax = 0x00001bbc;
c->ebx = 0x00060001;
c->eax = cpu->hyperv_version_id[0];
c->ebx = cpu->hyperv_version_id[1];
c->ecx = cpu->hyperv_version_id[2];
c->edx = cpu->hyperv_version_id[3];
c = &cpuid_ent[cpuid_i++];
c->function = HV_CPUID_FEATURES;
@ -1327,7 +1347,9 @@ static int hyperv_handle_properties(CPUState *cs,
c = &cpuid_ent[cpuid_i++];
c->function = HV_CPUID_IMPLEMENT_LIMITS;
c->eax = cpu->hv_max_vps;
c->ebx = 0x40;
c->ebx = cpu->hyperv_limits[0];
c->ecx = cpu->hyperv_limits[1];
c->edx = cpu->hyperv_limits[2];
if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
__u32 function;

0
target/i386/kvm_i386.h → target/i386/kvm/kvm_i386.h
View file

3
target/i386/kvm/meson.build Normal file
View file

@ -0,0 +1,3 @@
i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_false: files('hyperv-stub.c'))

7
target/i386/kvm/trace-events Normal file
View file

@ -0,0 +1,7 @@
# See docs/devel/tracing.txt for syntax documentation.
# kvm.c
kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for GSI %" PRIu32
kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d"
kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d"
kvm_x86_update_msi_routes(int num) "Updated %d MSI routes"

1
target/i386/kvm/trace.h Normal file
View file

@ -0,0 +1 @@
#include "trace/trace-target_i386_kvm.h"

4
target/i386/machine.c
View file

@ -3,9 +3,9 @@
#include "exec/exec-all.h"
#include "hw/isa/isa.h"
#include "migration/cpu.h"
#include "hyperv.h"
#include "kvm/hyperv.h"
#include "hw/i386/x86.h"
#include "kvm_i386.h"
#include "kvm/kvm_i386.h"
#include "sysemu/kvm.h"
#include "sysemu/tcg.h"

33
target/i386/meson.build
View file

@ -4,21 +4,8 @@ i386_ss.add(files(
'gdbstub.c',
'helper.c',
'xsave_helper.c',
'cpu-dump.c',
))
i386_ss.add(when: 'CONFIG_TCG', if_true: files(
'bpt_helper.c',
'cc_helper.c',
'excp_helper.c',
'fpu_helper.c',
'int_helper.c',
'mem_helper.c',
'misc_helper.c',
'mpx_helper.c',
'seg_helper.c',
'smm_helper.c',
'svm_helper.c',
'translate.c'), if_false: files('tcg-stub.c'))
i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c'))
i386_softmmu_ss = ss.source_set()
@ -28,22 +15,12 @@ i386_softmmu_ss.add(files(
'machine.c',
'monitor.c',
))
i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_false: files('hyperv-stub.c'))
i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files(
'whpx-all.c',
'whpx-cpus.c',
'whpx-apic.c',
))
i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files(
'hax-all.c',
'hax-mem.c',
'hax-cpus.c',
))
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c'))
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c'))
subdir('kvm')
subdir('hax')
subdir('whpx')
subdir('hvf')
subdir('tcg')
target_arch += {'i386': i386_ss}
target_softmmu_arch += {'i386': i386_softmmu_ss}

1
target/i386/bpt_helper.c → target/i386/tcg/bpt_helper.c
View file

@ -21,6 +21,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "helper-tcg.h"
#ifndef CONFIG_USER_ONLY

1
target/i386/cc_helper.c → target/i386/tcg/cc_helper.c
View file

@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "helper-tcg.h"
const uint8_t parity_table[256] = {
CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

0
target/i386/cc_helper_template.h → target/i386/tcg/cc_helper_template.h
View file

1
target/i386/excp_helper.c → target/i386/tcg/excp_helper.c
View file

@ -23,6 +23,7 @@
#include "qemu/log.h"
#include "sysemu/runstate.h"
#include "exec/helper-proto.h"
#include "helper-tcg.h"
void helper_raise_interrupt(CPUX86State *env, int intno, int next_eip_addend)
{

39
target/i386/fpu_helper.c → target/i386/tcg/fpu_helper.c
View file

@ -26,11 +26,18 @@
#include "exec/cpu_ldst.h"
#include "fpu/softfloat.h"
#include "fpu/softfloat-macros.h"
#include "helper-tcg.h"
#ifdef CONFIG_SOFTMMU
#include "hw/irq.h"
#endif
/* float macros */
#define FT0 (env->ft0)
#define ST0 (env->fpregs[env->fpstt].d)
#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
#define ST1 ST(1)
#define FPU_RC_MASK 0xc00
#define FPU_RC_NEAR 0x000
#define FPU_RC_DOWN 0x400
@ -2986,23 +2993,21 @@ void update_mxcsr_status(CPUX86State *env)
void update_mxcsr_from_sse_status(CPUX86State *env)
{
if (tcg_enabled()) {
uint8_t flags = get_float_exception_flags(&env->sse_status);
/*
* The MXCSR denormal flag has opposite semantics to
* float_flag_input_denormal (the softfloat code sets that flag
* only when flushing input denormals to zero, but SSE sets it
* only when not flushing them to zero), so is not converted
* here.
*/
env->mxcsr |= ((flags & float_flag_invalid ? FPUS_IE : 0) |
(flags & float_flag_divbyzero ? FPUS_ZE : 0) |
(flags & float_flag_overflow ? FPUS_OE : 0) |
(flags & float_flag_underflow ? FPUS_UE : 0) |
(flags & float_flag_inexact ? FPUS_PE : 0) |
(flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE :
0));
}
uint8_t flags = get_float_exception_flags(&env->sse_status);
/*
* The MXCSR denormal flag has opposite semantics to
* float_flag_input_denormal (the softfloat code sets that flag
* only when flushing input denormals to zero, but SSE sets it
* only when not flushing them to zero), so is not converted
* here.
*/
env->mxcsr |= ((flags & float_flag_invalid ? FPUS_IE : 0) |
(flags & float_flag_divbyzero ? FPUS_ZE : 0) |
(flags & float_flag_overflow ? FPUS_OE : 0) |
(flags & float_flag_underflow ? FPUS_UE : 0) |
(flags & float_flag_inexact ? FPUS_PE : 0) |
(flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE :
0));
}
void helper_update_mxcsr(CPUX86State *env)

95
target/i386/tcg/helper-tcg.h Normal file
View file

@ -0,0 +1,95 @@
/*
* TCG specific prototypes for helpers
*
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef I386_HELPER_TCG_H
#define I386_HELPER_TCG_H
#include "exec/exec-all.h"
/* Maximum instruction code size */
#define TARGET_MAX_INSN_SIZE 16
/*
* XXX: This value should match the one returned by CPUID
* and in exec.c
*/
# if defined(TARGET_X86_64)
# define TCG_PHYS_ADDR_BITS 40
# else
# define TCG_PHYS_ADDR_BITS 36
# endif
#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
/**
* x86_cpu_do_interrupt:
* @cpu: vCPU the interrupt is to be handled by.
*/
void x86_cpu_do_interrupt(CPUState *cpu);
bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
/* helper.c */
bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
void breakpoint_handler(CPUState *cs);
/* n must be a constant to be efficient */
static inline target_long lshift(target_long x, int n)
{
if (n >= 0) {
return x << n;
} else {
return x >> (-n);
}
}
/* translate.c */
void tcg_x86_init(void);
/* excp_helper.c */
void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
uintptr_t retaddr);
void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
int error_code);
void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
int error_code, uintptr_t retaddr);
void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
int error_code, int next_eip_addend);
/* cc_helper.c */
extern const uint8_t parity_table[256];
/* misc_helper.c */
void cpu_load_eflags(CPUX86State *env, int eflags, int update_mask);
/* svm_helper.c */
void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
uint64_t exit_info_1, uintptr_t retaddr);
void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
/* seg_helper.c */
void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
/* smm_helper.c */
void do_smm_enter(X86CPU *cpu);
#endif /* I386_HELPER_TCG_H */

1
target/i386/int_helper.c → target/i386/tcg/int_helper.c
View file

@ -24,6 +24,7 @@
#include "exec/helper-proto.h"
#include "qapi/error.h"
#include "qemu/guest-random.h"
#include "helper-tcg.h"
//#define DEBUG_MULDIV

1
target/i386/mem_helper.c → target/i386/tcg/mem_helper.c
View file

@ -25,6 +25,7 @@
#include "qemu/int128.h"
#include "qemu/atomic128.h"
#include "tcg/tcg.h"
#include "helper-tcg.h"
void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0)
{

14
target/i386/tcg/meson.build Normal file
View file

@ -0,0 +1,14 @@
i386_ss.add(when: 'CONFIG_TCG', if_true: files(
'bpt_helper.c',
'cc_helper.c',
'excp_helper.c',
'fpu_helper.c',
'int_helper.c',
'mem_helper.c',
'misc_helper.c',
'mpx_helper.c',
'seg_helper.c',
'smm_helper.c',
'svm_helper.c',
'tcg-cpu.c',
'translate.c'), if_false: files('tcg-stub.c'))

14
target/i386/misc_helper.c → target/i386/tcg/misc_helper.c
View file

@ -24,6 +24,20 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/address-spaces.h"
#include "helper-tcg.h"
/*
* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
* after generating a call to a helper that uses this.
*/
void cpu_load_eflags(CPUX86State *env, int eflags, int update_mask)
{
CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
CC_OP = CC_OP_EFLAGS;
env->df = 1 - (2 * ((eflags >> 10) & 1));
env->eflags = (env->eflags & ~update_mask) |
(eflags & update_mask) | 0x2;
}
void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
{

1
target/i386/mpx_helper.c → target/i386/tcg/mpx_helper.c
View file

@ -22,6 +22,7 @@
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
#include "helper-tcg.h"
void helper_bndck(CPUX86State *env, uint32_t fail)

1
target/i386/seg_helper.c → target/i386/tcg/seg_helper.c
View file

@ -25,6 +25,7 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/log.h"
#include "helper-tcg.h"
//#define DEBUG_PCALL

2
target/i386/smm_helper.c → target/i386/tcg/smm_helper.c
View file

@ -22,6 +22,8 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/log.h"
#include "helper-tcg.h"
/* SMM support */

1
target/i386/svm_helper.c → target/i386/tcg/svm_helper.c
View file

@ -22,6 +22,7 @@
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "helper-tcg.h"
/* Secure Virtual Machine helpers */

71
target/i386/tcg/tcg-cpu.c Normal file
View file

@ -0,0 +1,71 @@
/*
* i386 TCG cpu class initialization
*
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "tcg-cpu.h"
#include "exec/exec-all.h"
#include "sysemu/runstate.h"
#include "helper-tcg.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/i386/apic.h"
#endif
/* Frob eflags into and out of the CPU temporary format. */
static void x86_cpu_exec_enter(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
env->df = 1 - (2 * ((env->eflags >> 10) & 1));
CC_OP = CC_OP_EFLAGS;
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
}
static void x86_cpu_exec_exit(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
env->eflags = cpu_compute_eflags(env);
}
static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
X86CPU *cpu = X86_CPU(cs);
cpu->env.eip = tb->pc - tb->cs_base;
}
void tcg_cpu_common_class_init(CPUClass *cc)
{
cc->do_interrupt = x86_cpu_do_interrupt;
cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->cpu_exec_enter = x86_cpu_exec_enter;
cc->cpu_exec_exit = x86_cpu_exec_exit;
cc->tcg_initialize = tcg_x86_init;
cc->tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->debug_excp_handler = breakpoint_handler;
#endif
}

15
target/i386/tcg/tcg-cpu.h Normal file
View file

@ -0,0 +1,15 @@
/*
* i386 TCG CPU class initialization
*
* Copyright 2020 SUSE LLC
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef TCG_CPU_H
#define TCG_CPU_H
void tcg_cpu_common_class_init(CPUClass *cc);
#endif /* TCG_CPU_H */

0
target/i386/tcg-stub.c → target/i386/tcg/tcg-stub.c
View file

1
target/i386/translate.c → target/i386/tcg/translate.c
View file

@ -28,6 +28,7 @@
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "helper-tcg.h"
#include "trace-tcg.h"
#include "exec/log.h"

6
target/i386/trace-events
View file

@ -1,11 +1,5 @@
# See docs/devel/tracing.txt for syntax documentation.
# kvm.c
kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for GSI %" PRIu32
kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d"
kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d"
kvm_x86_update_msi_routes(int num) "Updated %d MSI routes"
# sev.c
kvm_sev_init(void) ""
kvm_memcrypt_register_region(void *addr, size_t len) "addr %p len 0x%zx"

5
target/i386/whpx/meson.build Normal file
View file

@ -0,0 +1,5 @@
i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files(
'whpx-all.c',
'whpx-apic.c',
'whpx-cpus.c',
))

0
target/i386/whp-dispatch.h → target/i386/whpx/whp-dispatch.h
View file

0
target/i386/whpx-all.c → target/i386/whpx/whpx-all.c
View file

0
target/i386/whpx-apic.c → target/i386/whpx/whpx-apic.c
View file

0
target/i386/whpx-cpus.c → target/i386/whpx/whpx-cpus.c
View file

0
target/i386/whpx-cpus.h → target/i386/whpx/whpx-cpus.h
View file