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https://gitlab.com/qemu-project/qemu
synced 2024-09-06 18:05:37 +00:00
tcg: Remove TCG_CT_REG
This wasn't actually used for anything, really. All variable operands must accept registers, and which are indicated by the set in TCGArgConstraint.regs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
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66792f90f1
commit
74a117906b
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@ -979,7 +979,6 @@ void tcg_dump_op_count(void);
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#define TCG_CT_ALIAS 0x80
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#define TCG_CT_IALIAS 0x40
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#define TCG_CT_NEWREG 0x20 /* output requires a new register */
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#define TCG_CT_REG 0x01
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#define TCG_CT_CONST 0x02 /* any constant of register size */
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typedef struct TCGArgConstraint {
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@ -128,15 +128,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
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{
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switch (*ct_str++) {
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case 'r': /* general registers */
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ct->ct |= TCG_CT_REG;
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ct->regs |= 0xffffffffu;
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break;
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case 'w': /* advsimd registers */
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ct->ct |= TCG_CT_REG;
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ct->regs |= 0xffffffff00000000ull;
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break;
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case 'l': /* qemu_ld / qemu_st address, data_reg */
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffffffffu;
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#ifdef CONFIG_SOFTMMU
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/* x0 and x1 will be overwritten when reading the tlb entry,
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@ -253,13 +253,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
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break;
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case 'r':
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffff;
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break;
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/* qemu_ld address */
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case 'l':
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffff;
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#ifdef CONFIG_SOFTMMU
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/* r0-r2,lr will be overwritten when reading the tlb entry,
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@ -274,7 +272,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
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/* qemu_st address & data */
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case 's':
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffff;
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/* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
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and r0-r1 doing the byte swapping, so don't use these. */
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@ -208,42 +208,33 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
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{
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switch(*ct_str++) {
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case 'a':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
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break;
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case 'b':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
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break;
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case 'c':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
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break;
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case 'd':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
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break;
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case 'S':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
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break;
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case 'D':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
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break;
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case 'q':
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/* A register that can be used as a byte operand. */
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ct->ct |= TCG_CT_REG;
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ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
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break;
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case 'Q':
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/* A register with an addressable second byte (e.g. %ah). */
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xf;
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break;
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case 'r':
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/* A general register. */
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ct->ct |= TCG_CT_REG;
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ct->regs |= ALL_GENERAL_REGS;
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break;
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case 'W':
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@ -252,13 +243,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
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break;
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case 'x':
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/* A vector register. */
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ct->ct |= TCG_CT_REG;
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ct->regs |= ALL_VECTOR_REGS;
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break;
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/* qemu_ld/st address constraint */
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case 'L':
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ct->ct |= TCG_CT_REG;
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ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
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tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
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tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
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@ -195,11 +195,9 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
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{
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switch(*ct_str++) {
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case 'r':
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffffffff;
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break;
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case 'L': /* qemu_ld input arg constraint */
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffffffff;
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tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
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#if defined(CONFIG_SOFTMMU)
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@ -209,7 +207,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
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#endif
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break;
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case 'S': /* qemu_st constraint */
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffffffff;
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tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
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#if defined(CONFIG_SOFTMMU)
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@ -224,19 +224,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
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{
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switch (*ct_str++) {
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case 'A': case 'B': case 'C': case 'D':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
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break;
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case 'r':
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffffffff;
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break;
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case 'v':
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffffffff00000000ull;
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break;
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case 'L': /* qemu_ld constraint */
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffffffff;
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tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
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#ifdef CONFIG_SOFTMMU
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@ -245,7 +241,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
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#endif
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break;
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case 'S': /* qemu_st constraint */
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffffffff;
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tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
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#ifdef CONFIG_SOFTMMU
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@ -137,12 +137,10 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
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{
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switch (*ct_str++) {
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case 'r':
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffffffff;
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break;
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case 'L':
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/* qemu_ld/qemu_st constraint */
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffffffff;
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/* qemu_ld/qemu_st uses TCG_REG_TMP0 */
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#if defined(CONFIG_SOFTMMU)
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@ -408,23 +408,19 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
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{
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switch (*ct_str++) {
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case 'r': /* all registers */
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffff;
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break;
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case 'L': /* qemu_ld/st constraint */
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffff;
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tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
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tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
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tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
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break;
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case 'a': /* force R2 for division */
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ct->ct |= TCG_CT_REG;
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ct->regs = 0;
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tcg_regset_set_reg(ct->regs, TCG_REG_R2);
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break;
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case 'b': /* force R3 for division */
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ct->ct |= TCG_CT_REG;
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ct->regs = 0;
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tcg_regset_set_reg(ct->regs, TCG_REG_R3);
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break;
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@ -325,15 +325,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
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{
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switch (*ct_str++) {
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case 'r':
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffffffff;
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break;
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case 'R':
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ct->ct |= TCG_CT_REG;
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ct->regs = ALL_64;
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break;
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case 'A': /* qemu_ld/st address constraint */
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ct->ct |= TCG_CT_REG;
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ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
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reserve_helpers:
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tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
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tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
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break;
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case 's': /* qemu_st data 32-bit constraint */
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ct->ct |= TCG_CT_REG;
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ct->regs = 0xffffffff;
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goto reserve_helpers;
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case 'S': /* qemu_st data 64-bit constraint */
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ct->ct |= TCG_CT_REG;
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ct->regs = ALL_64;
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goto reserve_helpers;
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case 'I':
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15
tcg/tcg.c
15
tcg/tcg.c
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@ -2194,21 +2194,14 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
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/* we give more priority to constraints with less registers */
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static int get_constraint_priority(const TCGOpDef *def, int k)
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{
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const TCGArgConstraint *arg_ct;
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const TCGArgConstraint *arg_ct = &def->args_ct[k];
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int n;
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int i, n;
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arg_ct = &def->args_ct[k];
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if (arg_ct->ct & TCG_CT_ALIAS) {
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/* an alias is equivalent to a single register */
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n = 1;
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} else {
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if (!(arg_ct->ct & TCG_CT_REG))
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return 0;
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n = 0;
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for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
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if (tcg_regset_test_reg(arg_ct->regs, i))
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n++;
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}
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n = ctpop64(arg_ct->regs);
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}
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return TCG_TARGET_NB_REGS - n + 1;
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}
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@ -2276,7 +2269,7 @@ static void process_op_defs(TCGContext *s)
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int oarg = *ct_str - '0';
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tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
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tcg_debug_assert(oarg < def->nb_oargs);
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tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG);
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tcg_debug_assert(def->args_ct[oarg].regs != 0);
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/* TCG_CT_ALIAS is for the output arguments.
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The input is tagged with TCG_CT_IALIAS. */
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def->args_ct[i] = def->args_ct[oarg];
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@ -392,7 +392,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
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case 'r':
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case 'L': /* qemu_ld constraint */
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case 'S': /* qemu_st constraint */
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ct->ct |= TCG_CT_REG;
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ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
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break;
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default:
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