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https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
ESP: fix ESP DMA access when DMA is not enabled
Sending ESP a command caused it to trigger DMA immediately even if DMA was not enabled at the DMA controller. Add a signal from DMA controller to ESP to tell ESP about changes in DMA enable bit. Also use the correct function for setting up GPIO outputs. This fixes NetBSD 1.6.1 through 3.0 boot. Thanks to Artyom Tarasenko for extensive debugging of the problem. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
24e0e38b83
commit
73d7434279
5 changed files with 88 additions and 18 deletions
53
hw/esp.c
53
hw/esp.c
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@ -80,6 +80,8 @@ struct ESPState {
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ESPDMAMemoryReadWriteFunc dma_memory_read;
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ESPDMAMemoryReadWriteFunc dma_memory_write;
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void *dma_opaque;
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int dma_enabled;
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void (*dma_cb)(ESPState *s);
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};
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#define ESP_TCLO 0x0
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@ -167,6 +169,24 @@ static void esp_lower_irq(ESPState *s)
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}
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}
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static void esp_dma_enable(void *opaque, int irq, int level)
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{
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DeviceState *d = opaque;
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ESPState *s = container_of(d, ESPState, busdev.qdev);
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if (level) {
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s->dma_enabled = 1;
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DPRINTF("Raise enable\n");
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if (s->dma_cb) {
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s->dma_cb(s);
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s->dma_cb = NULL;
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}
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} else {
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DPRINTF("Lower enable\n");
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s->dma_enabled = 0;
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}
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}
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static uint32_t get_cmd(ESPState *s, uint8_t *buf)
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{
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uint32_t dmalen;
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@ -243,6 +263,10 @@ static void handle_satn(ESPState *s)
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uint8_t buf[32];
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int len;
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if (!s->dma_enabled) {
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s->dma_cb = handle_satn;
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return;
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}
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len = get_cmd(s, buf);
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if (len)
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do_cmd(s, buf);
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@ -253,6 +277,10 @@ static void handle_s_without_atn(ESPState *s)
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uint8_t buf[32];
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int len;
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if (!s->dma_enabled) {
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s->dma_cb = handle_s_without_atn;
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return;
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}
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len = get_cmd(s, buf);
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if (len) {
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do_busid_cmd(s, buf, 0);
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@ -261,6 +289,10 @@ static void handle_s_without_atn(ESPState *s)
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static void handle_satn_stop(ESPState *s)
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{
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if (!s->dma_enabled) {
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s->dma_cb = handle_satn_stop;
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return;
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}
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s->cmdlen = get_cmd(s, s->cmdbuf);
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if (s->cmdlen) {
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DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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@ -431,6 +463,7 @@ static void esp_hard_reset(DeviceState *d)
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s->ti_wptr = 0;
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s->dma = 0;
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s->do_cmd = 0;
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s->dma_cb = NULL;
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s->rregs[ESP_CFG1] = 7;
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}
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@ -450,6 +483,18 @@ static void parent_esp_reset(void *opaque, int irq, int level)
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}
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}
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static void esp_gpio_demux(void *opaque, int irq, int level)
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{
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switch (irq) {
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case 0:
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parent_esp_reset(opaque, irq, level);
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break;
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case 1:
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esp_dma_enable(opaque, irq, level);
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break;
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}
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}
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static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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ESPState *s = opaque;
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@ -646,7 +691,8 @@ static const VMStateDescription vmstate_esp = {
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void esp_init(target_phys_addr_t espaddr, int it_shift,
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ESPDMAMemoryReadWriteFunc dma_memory_read,
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ESPDMAMemoryReadWriteFunc dma_memory_write,
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void *dma_opaque, qemu_irq irq, qemu_irq *reset)
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void *dma_opaque, qemu_irq irq, qemu_irq *reset,
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qemu_irq *dma_enable)
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{
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DeviceState *dev;
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SysBusDevice *s;
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@ -658,11 +704,14 @@ void esp_init(target_phys_addr_t espaddr, int it_shift,
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esp->dma_memory_write = dma_memory_write;
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esp->dma_opaque = dma_opaque;
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esp->it_shift = it_shift;
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/* XXX for now until rc4030 has been changed to use DMA enable signal */
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esp->dma_enabled = 1;
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qdev_init_nofail(dev);
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s = sysbus_from_qdev(dev);
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sysbus_connect_irq(s, 0, irq);
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sysbus_mmio_map(s, 0, espaddr);
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*reset = qdev_get_gpio_in(dev, 0);
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*dma_enable = qdev_get_gpio_in(dev, 1);
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}
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static int esp_init1(SysBusDevice *dev)
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@ -676,7 +725,7 @@ static int esp_init1(SysBusDevice *dev)
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esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s);
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sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
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qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1);
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qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);
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scsi_bus_new(&s->bus, &dev->qdev, 0, ESP_MAX_DEVS, esp_command_complete);
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return scsi_bus_legacy_handle_cmdline(&s->bus);
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3
hw/esp.h
3
hw/esp.h
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@ -7,6 +7,7 @@ typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
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void esp_init(target_phys_addr_t espaddr, int it_shift,
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ESPDMAMemoryReadWriteFunc dma_memory_read,
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ESPDMAMemoryReadWriteFunc dma_memory_write,
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void *dma_opaque, qemu_irq irq, qemu_irq *reset);
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void *dma_opaque, qemu_irq irq, qemu_irq *reset,
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qemu_irq *dma_enable);
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#endif
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@ -137,7 +137,7 @@ void mips_jazz_init (ram_addr_t ram_size,
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NICInfo *nd;
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PITState *pit;
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DriveInfo *fds[MAX_FD];
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qemu_irq esp_reset;
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qemu_irq esp_reset, dma_enable;
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qemu_irq *cpu_exit_irq;
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ram_addr_t ram_offset;
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ram_addr_t bios_offset;
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@ -245,7 +245,7 @@ void mips_jazz_init (ram_addr_t ram_size,
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/* SCSI adapter */
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esp_init(0x80002000, 0,
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rc4030_dma_read, rc4030_dma_write, dmas[0],
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rc4030[5], &esp_reset);
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rc4030[5], &esp_reset, &dma_enable);
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/* Floppy */
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if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
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@ -58,6 +58,7 @@
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#define DMA_INTR 1
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#define DMA_INTREN 0x10
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#define DMA_WRITE_MEM 0x100
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#define DMA_EN 0x200
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#define DMA_LOADED 0x04000000
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#define DMA_DRAIN_FIFO 0x40
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#define DMA_RESET 0x80
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@ -72,7 +73,12 @@ struct DMAState {
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uint32_t dmaregs[DMA_REGS];
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qemu_irq irq;
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void *iommu;
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qemu_irq dev_reset;
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qemu_irq gpio[2];
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};
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enum {
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GPIO_RESET = 0,
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GPIO_DMA,
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};
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/* Note: on sparc, the lance 16 bit bus is swapped */
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@ -201,12 +207,21 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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}
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}
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if (val & DMA_RESET) {
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qemu_irq_raise(s->dev_reset);
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qemu_irq_lower(s->dev_reset);
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qemu_irq_raise(s->gpio[GPIO_RESET]);
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qemu_irq_lower(s->gpio[GPIO_RESET]);
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} else if (val & DMA_DRAIN_FIFO) {
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val &= ~DMA_DRAIN_FIFO;
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} else if (val == 0)
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val = DMA_DRAIN_FIFO;
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if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
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DPRINTF("Raise DMA enable\n");
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qemu_irq_raise(s->gpio[GPIO_DMA]);
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} else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
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DPRINTF("Lower DMA enable\n");
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qemu_irq_lower(s->gpio[GPIO_DMA]);
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}
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val &= ~DMA_CSR_RO_MASK;
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val |= DMA_VER;
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s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
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@ -262,7 +277,7 @@ static int sparc32_dma_init1(SysBusDevice *dev)
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sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory);
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qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
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qdev_init_gpio_out(&dev->qdev, &s->dev_reset, 1);
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qdev_init_gpio_out(&dev->qdev, s->gpio, 2);
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return 0;
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}
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23
hw/sun4m.c
23
hw/sun4m.c
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@ -810,7 +810,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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void *iommu, *espdma, *ledma, *nvram;
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qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
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espdma_irq, ledma_irq;
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qemu_irq esp_reset;
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qemu_irq esp_reset, dma_enable;
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qemu_irq fdc_tc;
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qemu_irq *cpu_halt;
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unsigned long kernel_size;
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@ -930,11 +930,12 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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exit(1);
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}
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esp_reset = qdev_get_gpio_in(espdma, 0);
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esp_init(hwdef->esp_base, 2,
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espdma_memory_read, espdma_memory_write,
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espdma, espdma_irq, &esp_reset);
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espdma, espdma_irq, &esp_reset, &dma_enable);
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qdev_connect_gpio_out(espdma, 0, esp_reset);
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qdev_connect_gpio_out(espdma, 1, dma_enable);
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if (hwdef->cs_base) {
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sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
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@ -1494,7 +1495,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
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void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
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qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
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espdma_irq, ledma_irq;
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qemu_irq esp_reset;
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qemu_irq esp_reset, dma_enable;
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unsigned long kernel_size;
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void *fw_cfg;
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DeviceState *dev;
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@ -1561,10 +1562,12 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
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exit(1);
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}
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esp_reset = qdev_get_gpio_in(espdma, 0);
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esp_init(hwdef->esp_base, 2,
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espdma_memory_read, espdma_memory_write,
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espdma, espdma_irq, &esp_reset);
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espdma, espdma_irq, &esp_reset, &dma_enable);
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qdev_connect_gpio_out(espdma, 0, esp_reset);
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qdev_connect_gpio_out(espdma, 1, dma_enable);
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kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
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RAM_size);
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@ -1683,7 +1686,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
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{
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void *iommu, *espdma, *ledma, *nvram;
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qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
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qemu_irq esp_reset;
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qemu_irq esp_reset, dma_enable;
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qemu_irq fdc_tc;
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unsigned long kernel_size;
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DriveInfo *fd[MAX_FD];
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@ -1751,10 +1754,12 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
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exit(1);
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}
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esp_reset = qdev_get_gpio_in(espdma, 0);
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esp_init(hwdef->esp_base, 2,
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espdma_memory_read, espdma_memory_write,
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espdma, espdma_irq, &esp_reset);
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espdma, espdma_irq, &esp_reset, &dma_enable);
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qdev_connect_gpio_out(espdma, 0, esp_reset);
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qdev_connect_gpio_out(espdma, 1, dma_enable);
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kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
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RAM_size);
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