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tests/tcg/ppc64: Add mffsce test

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Add mffsce test to check both the return value and the new fpscr
stored in the cpu.

Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220629162904.105060-8-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Víctor Colombo 2022-06-29 13:29:00 -03:00 committed by Daniel Henrique Barboza
parent 6cef305fe7
commit 7141a173c8
3 changed files with 39 additions and 0 deletions
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1
tests/tcg/ppc64/Makefile.target
View file

@ -11,6 +11,7 @@ endif
$(PPC64_TESTS): CFLAGS += -mpower8-vector
PPC64_TESTS += mtfsf
PPC64_TESTS += mffsce
ifneq ($(CROSS_CC_HAS_POWER10),)
PPC64_TESTS += byte_reverse sha512-vector

1
tests/tcg/ppc64le/Makefile.target
View file

@ -24,6 +24,7 @@ run-sha512-vector: QEMU_OPTS+=-cpu POWER10
run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10
PPC64LE_TESTS += mtfsf
PPC64LE_TESTS += mffsce
PPC64LE_TESTS += signal_save_restore_xer
PPC64LE_TESTS += xxspltw

37
tests/tcg/ppc64le/mffsce.c Normal file
View file

@ -0,0 +1,37 @@
#include <stdlib.h>
#include <stdint.h>
#include <assert.h>
#define MTFSF(FLM, FRB) asm volatile ("mtfsf %0, %1" :: "i" (FLM), "f" (FRB))
#define MFFS(FRT) asm("mffs %0" : "=f" (FRT))
#define MFFSCE(FRT) asm("mffsce %0" : "=f" (FRT))
#define PPC_BIT_NR(nr) (63 - (nr))
#define FP_VE (1ull << PPC_BIT_NR(56))
#define FP_UE (1ull << PPC_BIT_NR(58))
#define FP_ZE (1ull << PPC_BIT_NR(59))
#define FP_XE (1ull << PPC_BIT_NR(60))
#define FP_NI (1ull << PPC_BIT_NR(61))
#define FP_RN1 (1ull << PPC_BIT_NR(63))
int main(void)
{
uint64_t frt, fpscr;
uint64_t test_value = FP_VE | FP_UE | FP_ZE |
FP_XE | FP_NI | FP_RN1;
MTFSF(0b11111111, test_value); /* set test value to cpu fpscr */
MFFSCE(frt);
MFFS(fpscr); /* read the value that mffsce stored to cpu fpscr */
/* the returned value should be as the cpu fpscr was before */
assert((frt & 0xff) == test_value);
/*
* the cpu fpscr last 3 bits should be unchanged
* and enable bits should be unset
*/
assert((fpscr & 0xff) == (test_value & 0x7));
return 0;
}