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sdhci: check the Spec v1 capabilities correctness
Incorrect value will throw an error. Note than Spec v2 is supported by default. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-11-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé
Paolo Bonzini
parent
09b738ff65
commit
6ff37c3dfa
3 changed files with 116 additions and 2 deletions
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@ -87,6 +87,8 @@
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/* R/W Host control Register 0x0 */
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#define SDHC_HOSTCTL 0x28
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#define SDHC_CTRL_LED 0x01
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#define SDHC_CTRL_DATATRANSFERWIDTH 0x02 /* SD mode only */
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#define SDHC_CTRL_HIGH_SPEED 0x04
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#define SDHC_CTRL_DMA_CHECK_MASK 0x18
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#define SDHC_CTRL_SDMA 0x00
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#define SDHC_CTRL_ADMA1_32 0x08
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@ -102,6 +104,7 @@
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/* R/W Power Control Register 0x0 */
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#define SDHC_PWRCON 0x29
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#define SDHC_POWER_ON (1 << 0)
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FIELD(SDHC_PWRCON, BUS_VOLTAGE, 1, 3);
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/* R/W Block Gap Control Register 0x0 */
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#define SDHC_BLKGAP 0x2A
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@ -124,6 +127,7 @@
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/* R/W Timeout Control Register 0x0 */
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#define SDHC_TIMEOUTCON 0x2E
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FIELD(SDHC_TIMEOUTCON, COUNTER, 0, 4);
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/* R/W Software Reset Register 0x0 */
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#define SDHC_SWRST 0x2F
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@ -180,17 +184,31 @@
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/* ROC Auto CMD12 error status register 0x0 */
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#define SDHC_ACMD12ERRSTS 0x3C
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FIELD(SDHC_ACMD12ERRSTS, TIMEOUT_ERR, 1, 1);
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FIELD(SDHC_ACMD12ERRSTS, CRC_ERR, 2, 1);
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FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1);
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/* HWInit Capabilities Register 0x05E80080 */
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#define SDHC_CAPAB 0x40
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#define SDHC_CAN_DO_DMA 0x00400000
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#define SDHC_CAN_DO_ADMA2 0x00080000
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#define SDHC_CAN_DO_ADMA1 0x00100000
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#define SDHC_64_BIT_BUS_SUPPORT (1 << 28)
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FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6);
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FIELD(SDHC_CAPAB, TOUNIT, 7, 1);
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FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8);
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FIELD(SDHC_CAPAB, MAXBLOCKLENGTH, 16, 2);
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FIELD(SDHC_CAPAB, HIGHSPEED, 21, 1);
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FIELD(SDHC_CAPAB, SDMA, 22, 1);
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FIELD(SDHC_CAPAB, SUSPRESUME, 23, 1);
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FIELD(SDHC_CAPAB, V33, 24, 1);
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FIELD(SDHC_CAPAB, V30, 25, 1);
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FIELD(SDHC_CAPAB, V18, 26, 1);
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/* HWInit Maximum Current Capabilities Register 0x0 */
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#define SDHC_MAXCURR 0x48
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FIELD(SDHC_MAXCURR, V33_VDD1, 0, 8);
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FIELD(SDHC_MAXCURR, V30_VDD1, 8, 8);
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FIELD(SDHC_MAXCURR, V18_VDD1, 16, 8);
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/* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */
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#define SDHC_FEAER 0x50
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@ -23,6 +23,7 @@
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "sysemu/block-backend.h"
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@ -63,6 +64,92 @@ static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
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return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH));
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}
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/* return true on error */
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static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc,
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uint8_t freq, Error **errp)
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{
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switch (freq) {
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case 0:
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case 10 ... 63:
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break;
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default:
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error_setg(errp, "SD %s clock frequency can have value"
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"in range 0-63 only", desc);
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return true;
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}
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return false;
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}
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static void sdhci_check_capareg(SDHCIState *s, Error **errp)
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{
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uint64_t msk = s->capareg;
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uint32_t val;
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bool y;
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switch (s->sd_spec_version) {
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case 2: /* default version */
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/* fallthrough */
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case 1:
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y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT);
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msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0);
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val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ);
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trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val);
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if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) {
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return;
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}
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msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0);
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val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ);
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trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val);
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if (sdhci_check_capab_freq_range(s, "base", val, errp)) {
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return;
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}
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msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0);
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val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH);
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if (val >= 3) {
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error_setg(errp, "block size can be 512, 1024 or 2048 only");
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return;
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}
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trace_sdhci_capareg("max block length", sdhci_get_fifolen(s));
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msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0);
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val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED);
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trace_sdhci_capareg("high speed", val);
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msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0);
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val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA);
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trace_sdhci_capareg("SDMA", val);
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msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0);
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val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME);
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trace_sdhci_capareg("suspend/resume", val);
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msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0);
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val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33);
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trace_sdhci_capareg("3.3v", val);
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msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0);
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val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30);
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trace_sdhci_capareg("3.0v", val);
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msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0);
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val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18);
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trace_sdhci_capareg("1.8v", val);
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msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0);
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break;
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default:
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error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version);
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}
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if (msk) {
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qemu_log_mask(LOG_UNIMP,
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"SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk);
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}
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}
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static uint8_t sdhci_slotint(SDHCIState *s)
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{
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return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) ||
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@ -990,7 +1077,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
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case SDHC_TRNMOD:
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/* DMA can be enabled only if it is supported as indicated by
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* capabilities register */
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if (!(s->capareg & SDHC_CAN_DO_DMA)) {
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if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) {
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value &= ~SDHC_TRNS_DMA;
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}
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MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK);
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@ -1125,11 +1212,19 @@ static const MemoryRegionOps sdhci_mmio_ops = {
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static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
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{
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Error *local_err = NULL;
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if (s->sd_spec_version != 2) {
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error_setg(errp, "Only Spec v2 is supported");
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return;
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}
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s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1);
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sdhci_check_capareg(s, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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}
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/* --- qdev common --- */
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@ -13,6 +13,7 @@ sdhci_adma_transfer_completed(void) ""
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sdhci_access(const char *access, unsigned int size, uint64_t offset, const char *dir, uint64_t val, uint64_t val2) "%s%u: addr[0x%04" PRIx64 "] %s 0x%08" PRIx64 " (%" PRIu64 ")"
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sdhci_read_dataport(uint16_t data_count) "all %u bytes of data have been read from input buffer"
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sdhci_write_dataport(uint16_t data_count) "write buffer filled with %u bytes of data"
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sdhci_capareg(const char *desc, uint16_t val) "%s: %u"
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# hw/sd/milkymist-memcard.c
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milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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