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https://gitlab.com/qemu-project/qemu
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target/nios2: Replace MMU_LOG with tracepoints
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
1fb877a467
commit
6f83e277eb
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@ -2705,6 +2705,7 @@ if have_system or have_user
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'target/i386',
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'target/i386',
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'target/i386/kvm',
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'target/i386/kvm',
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'target/mips/tcg',
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'target/mips/tcg',
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'target/nios2',
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'target/ppc',
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'target/ppc',
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'target/riscv',
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'target/riscv',
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'target/s390x',
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'target/s390x',
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@ -23,18 +23,10 @@
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#include "cpu.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/exec-all.h"
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#include "mmu.h"
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#include "mmu.h"
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#include "trace/trace-target_nios2.h"
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#if !defined(CONFIG_USER_ONLY)
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#if !defined(CONFIG_USER_ONLY)
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/* Define this to enable MMU debug messages */
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/* #define DEBUG_MMU */
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#ifdef DEBUG_MMU
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#define MMU_LOG(x) x
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#else
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#define MMU_LOG(x)
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#endif
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/* rw - 0 = read, 1 = write, 2 = fetch. */
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/* rw - 0 = read, 1 = write, 2 = fetch. */
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unsigned int mmu_translate(CPUNios2State *env,
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unsigned int mmu_translate(CPUNios2State *env,
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Nios2MMULookup *lu,
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Nios2MMULookup *lu,
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@ -43,37 +35,26 @@ unsigned int mmu_translate(CPUNios2State *env,
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Nios2CPU *cpu = env_archcpu(env);
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Nios2CPU *cpu = env_archcpu(env);
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int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
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int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
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int vpn = vaddr >> 12;
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int vpn = vaddr >> 12;
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int way, n_ways = cpu->tlb_num_ways;
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MMU_LOG(qemu_log("mmu_translate vaddr %08X, pid %08X, vpn %08X\n",
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for (way = 0; way < n_ways; way++) {
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vaddr, pid, vpn));
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uint32_t index = (way * n_ways) + (vpn & env->mmu.tlb_entry_mask);
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Nios2TLBEntry *entry = &env->mmu.tlb[index];
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int way;
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for (way = 0; way < cpu->tlb_num_ways; way++) {
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Nios2TLBEntry *entry =
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&env->mmu.tlb[(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask)];
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MMU_LOG(qemu_log("TLB[%d] TAG %08X, VPN %08X\n",
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(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask),
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entry->tag, (entry->tag >> 12)));
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if (((entry->tag >> 12) != vpn) ||
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if (((entry->tag >> 12) != vpn) ||
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(((entry->tag & (1 << 11)) == 0) &&
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(((entry->tag & (1 << 11)) == 0) &&
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((entry->tag & ((1 << cpu->pid_num_bits) - 1)) != pid))) {
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((entry->tag & ((1 << cpu->pid_num_bits) - 1)) != pid))) {
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trace_nios2_mmu_translate_miss(vaddr, pid, index, entry->tag);
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continue;
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continue;
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}
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}
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lu->vaddr = vaddr & TARGET_PAGE_MASK;
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lu->vaddr = vaddr & TARGET_PAGE_MASK;
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lu->paddr = (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BITS;
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lu->paddr = (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BITS;
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lu->prot = ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) |
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lu->prot = ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) |
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((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) |
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((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) |
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((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0);
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((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0);
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MMU_LOG(qemu_log("HIT TLB[%d] %08X %08X %08X\n",
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trace_nios2_mmu_translate_hit(vaddr, pid, index, lu->paddr, lu->prot);
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(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask),
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lu->vaddr, lu->paddr, lu->prot));
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return 1;
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return 1;
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}
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}
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return 0;
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return 0;
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@ -84,21 +65,18 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
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CPUState *cs = env_cpu(env);
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CPUState *cs = env_cpu(env);
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Nios2CPU *cpu = env_archcpu(env);
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Nios2CPU *cpu = env_archcpu(env);
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int idx;
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int idx;
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MMU_LOG(qemu_log("TLB Flush PID %d\n", pid));
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for (idx = 0; idx < cpu->tlb_num_entries; idx++) {
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for (idx = 0; idx < cpu->tlb_num_entries; idx++) {
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Nios2TLBEntry *entry = &env->mmu.tlb[idx];
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Nios2TLBEntry *entry = &env->mmu.tlb[idx];
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MMU_LOG(qemu_log("TLB[%d] => %08X %08X\n",
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idx, entry->tag, entry->data));
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if ((entry->tag & (1 << 10)) && (!(entry->tag & (1 << 11))) &&
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if ((entry->tag & (1 << 10)) && (!(entry->tag & (1 << 11))) &&
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((entry->tag & ((1 << cpu->pid_num_bits) - 1)) == pid)) {
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((entry->tag & ((1 << cpu->pid_num_bits) - 1)) == pid)) {
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uint32_t vaddr = entry->tag & TARGET_PAGE_MASK;
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uint32_t vaddr = entry->tag & TARGET_PAGE_MASK;
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MMU_LOG(qemu_log("TLB Flush Page %08X\n", vaddr));
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trace_nios2_mmu_flush_pid_hit(pid, idx, vaddr);
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tlb_flush_page(cs, vaddr);
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tlb_flush_page(cs, vaddr);
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} else {
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trace_nios2_mmu_flush_pid_miss(pid, idx, entry->tag);
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}
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}
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}
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}
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}
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}
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@ -108,18 +86,15 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
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CPUState *cs = env_cpu(env);
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CPUState *cs = env_cpu(env);
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Nios2CPU *cpu = env_archcpu(env);
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Nios2CPU *cpu = env_archcpu(env);
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MMU_LOG(qemu_log("mmu_write %08X = %08X\n", rn, v));
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switch (rn) {
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switch (rn) {
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case CR_TLBACC:
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case CR_TLBACC:
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MMU_LOG(qemu_log("TLBACC: IG %02X, FLAGS %c%c%c%c%c, PFN %05X\n",
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trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT,
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v >> CR_TLBACC_IGN_SHIFT,
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(v & CR_TLBACC_C) ? 'C' : '.',
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(v & CR_TLBACC_C) ? 'C' : '.',
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(v & CR_TLBACC_R) ? 'R' : '.',
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(v & CR_TLBACC_R) ? 'R' : '.',
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(v & CR_TLBACC_W) ? 'W' : '.',
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(v & CR_TLBACC_W) ? 'W' : '.',
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(v & CR_TLBACC_X) ? 'X' : '.',
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(v & CR_TLBACC_X) ? 'X' : '.',
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(v & CR_TLBACC_G) ? 'G' : '.',
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(v & CR_TLBACC_G) ? 'G' : '.',
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v & CR_TLBACC_PFN_MASK);
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v & CR_TLBACC_PFN_MASK));
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/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
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/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
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if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) {
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if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) {
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@ -138,16 +113,10 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
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if ((entry->tag != newTag) || (entry->data != newData)) {
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if ((entry->tag != newTag) || (entry->data != newData)) {
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if (entry->tag & (1 << 10)) {
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if (entry->tag & (1 << 10)) {
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/* Flush existing entry */
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/* Flush existing entry */
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MMU_LOG(qemu_log("TLB Flush Page (OLD) %08X\n",
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entry->tag & TARGET_PAGE_MASK));
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tlb_flush_page(cs, entry->tag & TARGET_PAGE_MASK);
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tlb_flush_page(cs, entry->tag & TARGET_PAGE_MASK);
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}
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}
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entry->tag = newTag;
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entry->tag = newTag;
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entry->data = newData;
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entry->data = newData;
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MMU_LOG(qemu_log("TLB[%d] = %08X %08X\n",
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(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask),
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entry->tag, entry->data));
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}
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}
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/* Auto-increment tlbmisc.WAY */
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/* Auto-increment tlbmisc.WAY */
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env->regs[CR_TLBMISC] =
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env->regs[CR_TLBMISC] =
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@ -161,15 +130,14 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
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break;
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break;
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case CR_TLBMISC:
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case CR_TLBMISC:
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MMU_LOG(qemu_log("TLBMISC: WAY %X, FLAGS %c%c%c%c%c%c, PID %04X\n",
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trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT,
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v >> CR_TLBMISC_WAY_SHIFT,
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(v & CR_TLBMISC_RD) ? 'R' : '.',
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(v & CR_TLBMISC_RD) ? 'R' : '.',
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(v & CR_TLBMISC_WR) ? 'W' : '.',
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(v & CR_TLBMISC_WR) ? 'W' : '.',
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(v & CR_TLBMISC_DBL) ? '2' : '.',
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(v & CR_TLBMISC_DBL) ? '2' : '.',
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(v & CR_TLBMISC_BAD) ? 'B' : '.',
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(v & CR_TLBMISC_BAD) ? 'B' : '.',
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(v & CR_TLBMISC_PERM) ? 'P' : '.',
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(v & CR_TLBMISC_PERM) ? 'P' : '.',
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(v & CR_TLBMISC_D) ? 'D' : '.',
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(v & CR_TLBMISC_D) ? 'D' : '.',
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(v & CR_TLBMISC_PID_MASK) >> 4);
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(v & CR_TLBMISC_PID_MASK) >> 4));
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if ((v & CR_TLBMISC_PID_MASK) !=
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if ((v & CR_TLBMISC_PID_MASK) !=
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(env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) {
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(env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) {
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@ -193,11 +161,6 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
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CR_TLBMISC_PID_SHIFT);
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CR_TLBMISC_PID_SHIFT);
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env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK;
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env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK;
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env->regs[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT;
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env->regs[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT;
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MMU_LOG(qemu_log("TLB READ way %d, vpn %05X, tag %08X, data %08X, "
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"tlbacc %08X, tlbmisc %08X, pteaddr %08X\n",
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way, vpn, entry->tag, entry->data,
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env->regs[CR_TLBACC], env->regs[CR_TLBMISC],
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env->regs[CR_PTEADDR]));
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} else {
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} else {
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env->regs[CR_TLBMISC] = v;
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env->regs[CR_TLBMISC] = v;
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}
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}
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@ -206,9 +169,8 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
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break;
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break;
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case CR_PTEADDR:
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case CR_PTEADDR:
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MMU_LOG(qemu_log("PTEADDR: PTBASE %03X, VPN %05X\n",
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trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT,
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v >> CR_PTEADDR_PTBASE_SHIFT,
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(v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT);
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(v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT));
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/* Writes to PTEADDR don't change the read-back VPN value */
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/* Writes to PTEADDR don't change the read-back VPN value */
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env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) |
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env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) |
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@ -226,8 +188,6 @@ void mmu_init(CPUNios2State *env)
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Nios2CPU *cpu = env_archcpu(env);
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Nios2CPU *cpu = env_archcpu(env);
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Nios2MMU *mmu = &env->mmu;
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Nios2MMU *mmu = &env->mmu;
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MMU_LOG(qemu_log("mmu_init\n"));
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mmu->tlb_entry_mask = (cpu->tlb_num_entries / cpu->tlb_num_ways) - 1;
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mmu->tlb_entry_mask = (cpu->tlb_num_entries / cpu->tlb_num_ways) - 1;
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mmu->tlb = g_new0(Nios2TLBEntry, cpu->tlb_num_entries);
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mmu->tlb = g_new0(Nios2TLBEntry, cpu->tlb_num_entries);
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}
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}
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10
target/nios2/trace-events
Normal file
10
target/nios2/trace-events
Normal file
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@ -0,0 +1,10 @@
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# mmu.c
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nios2_mmu_translate_miss(uint32_t vaddr, uint32_t pid, uint32_t index, uint32_t tag) "mmu_translate: MISS vaddr=0x%08x pid=%u TLB[%u] tag=0x%08x"
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nios2_mmu_translate_hit(uint32_t vaddr, uint32_t pid, uint32_t index, uint32_t paddr, uint32_t prot) "mmu_translate: HIT vaddr=0x%08x pid=%u TLB[%u] paddr=0x%08x prot=0x%x"
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nios2_mmu_flush_pid_miss(uint32_t pid, uint32_t index, uint32_t vaddr) "mmu_flush: MISS pid=%u TLB[%u] tag=0x%08x"
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nios2_mmu_flush_pid_hit(uint32_t pid, uint32_t index, uint32_t vaddr) "mmu_flush: HIT pid=%u TLB[%u] vaddr=0x%08x"
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nios2_mmu_write_tlbacc(uint32_t ig, char c, char r, char w, char x, char g, uint32_t pfn) "mmu_write_tlbacc: ig=0x%02x flags=%c%c%c%c%c pfn=0x%08x"
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nios2_mmu_write_tlbmisc(uint32_t way, char r, char w, char t, char b, char p, char d, uint32_t pid) "mmu_write_tlbmisc: way=0x%x flags=%c%c%c%c%c%c pid=%u"
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nios2_mmu_write_pteaddr(uint32_t ptb, uint32_t vpn) "mmu_write_pteaddr: ptbase=0x%03x vpn=0x%05x"
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