target: Unify QOM style

Enforce the style described by commit 067109a11c ("docs/devel: mention the spacing requirement for QOM"): The first declaration of a storage or class structure should always be the parent and leave a visual space between that declaration and the new code. It is also useful to separate backing for properties (options driven by the user) and internal state to make navigation easier. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231013140116.255-2-philmd@linaro.org>
2024-07-22 02:44:53 +00:00 · 2023-10-13 11:21:51 +02:00 · 2023-10-13 11:21:51 +02:00 · 6ee45fac56
parent bb6cf6f016
commit 6ee45fac56
37 changed files with 4 additions and 84 deletions
--- a/target/alpha/cpu-qom.h
+++ b/target/alpha/cpu-qom.h
@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
 * An Alpha CPU model.
 */
 struct AlphaCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    DeviceReset parent_reset;
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@ -259,9 +259,7 @@ typedef struct CPUArchState {
 * An Alpha CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUAlphaState env;

--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@ -46,9 +46,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info);
 * An ARM CPU model.
 */
 struct ARMCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    const ARMCPUInfo *info;
    DeviceRealize parent_realize;
@ -62,9 +60,7 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
                       TYPE_AARCH64_CPU)

 struct AArch64CPUClass {
-    /*< private >*/
    ARMCPUClass parent_class;
-    /*< public >*/
 };

 void register_cp_regs_for_features(ARMCPU *cpu);
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@ -852,9 +852,7 @@ typedef struct {
 * An ARM CPU core.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUARMState env;

--- a/target/avr/cpu-qom.h
+++ b/target/avr/cpu-qom.h
@ -36,9 +36,8 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
 *  A AVR CPU model.
 */
 struct AVRCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/
+
    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
 };
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@ -144,9 +144,7 @@ typedef struct CPUArchState {
 *  A AVR CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUAVRState env;
 };
--- a/target/cris/cpu-qom.h
+++ b/target/cris/cpu-qom.h
@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
 * A CRIS CPU model.
 */
 struct CRISCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@ -174,9 +174,7 @@ typedef struct CPUArchState {
 * A CRIS CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUCRISState env;
 };
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@ -130,17 +130,14 @@ typedef struct CPUArchState {
 OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)

 typedef struct HexagonCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/
+
    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
 } HexagonCPUClass;

 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUHexagonState env;

--- a/target/hppa/cpu-qom.h
+++ b/target/hppa/cpu-qom.h
@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
 * An HPPA CPU model.
 */
 struct HPPACPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    DeviceReset parent_reset;
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@ -247,9 +247,7 @@ typedef struct CPUArchState {
 * An HPPA CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUHPPAState env;
    QEMUTimer *alarm_timer;
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@ -47,9 +47,7 @@ typedef struct X86CPUModel X86CPUModel;
 * An x86 CPU model or family.
 */
 struct X86CPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    /* CPU definition, automatically loaded by instance_init if not NULL.
     * Should be eventually replaced by subclass-specific property defaults.
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@ -1897,9 +1897,7 @@ struct kvm_msrs;
 * An x86 CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUX86State env;
    VMChangeStateEntry *vmsentry;
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@ -371,9 +371,7 @@ typedef struct CPUArchState {
 * A LoongArch CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPULoongArchState env;
    QEMUTimer timer;
@ -398,9 +396,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
 * A LoongArch CPU model.
 */
 struct LoongArchCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
--- a/target/m68k/cpu-qom.h
+++ b/target/m68k/cpu-qom.h
@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
 * A Motorola 68k CPU model.
 */
 struct M68kCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@ -164,9 +164,7 @@ typedef struct CPUArchState {
 * A Motorola 68k CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUM68KState env;
 };
--- a/target/microblaze/cpu-qom.h
+++ b/target/microblaze/cpu-qom.h
@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
 * A MicroBlaze CPU model.
 */
 struct MicroBlazeCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@ -343,9 +343,7 @@ typedef struct {
 * A MicroBlaze CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUMBState env;

--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
 * A MIPS CPU model.
 */
 struct MIPSCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@ -1209,9 +1209,7 @@ typedef struct CPUArchState {
 * A MIPS CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUMIPSState env;

--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
 * A Nios2 CPU model.
 */
 struct Nios2CPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
@ -214,9 +212,7 @@ typedef struct {
 * A Nios2 CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUNios2State env;

--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
 * A OpenRISC CPU model.
 */
 struct OpenRISCCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
@ -301,9 +299,7 @@ typedef struct CPUArchState {
 * A OpenRISC CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUOpenRISCState env;
 };
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@ -1313,9 +1313,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
 * A PowerPC CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUPPCState env;

--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@ -63,9 +63,8 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
 * A RISCV CPU model.
 */
 struct RISCVCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/
+
    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
 };
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@ -411,9 +411,7 @@ struct CPUArchState {
 * A RISCV CPU.
 */
 struct ArchCPU {
-    /* < private > */
    CPUState parent_obj;
-    /* < public > */

    CPURISCVState env;

--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
 * A RX CPU model.
 */
 struct RXCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@ -107,9 +107,7 @@ typedef struct CPUArchState {
 * A RX CPU
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPURXState env;
 };
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@ -49,9 +49,8 @@ typedef enum cpu_reset_type {
 * An S/390 CPU model.
 */
 struct S390CPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/
+
    const S390CPUDef *cpu_def;
    bool kvm_required;
    bool is_static;
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@ -172,9 +172,7 @@ static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
 * An S/390 CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUS390XState env;
    S390CPUModel *model;
--- a/target/sh4/cpu-qom.h
+++ b/target/sh4/cpu-qom.h
@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
 * A SuperH CPU model.
 */
 struct SuperHCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@ -204,9 +204,7 @@ typedef struct CPUArchState {
 * A SuperH CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUSH4State env;
 };
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@ -40,9 +40,7 @@ typedef struct sparc_def_t sparc_def_t;
 * A SPARC CPU model.
 */
 struct SPARCCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@ -562,9 +562,7 @@ struct CPUArchState {
 * A SPARC CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUSPARCState env;
 };
--- a/target/tricore/cpu-qom.h
+++ b/target/tricore/cpu-qom.h
@ -27,9 +27,7 @@
 OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)

 struct TriCoreCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@ -63,9 +63,7 @@ typedef struct CPUArchState {
 * A TriCore CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUTriCoreState env;
 };
--- a/target/xtensa/cpu-qom.h
+++ b/target/xtensa/cpu-qom.h
@ -47,9 +47,7 @@ typedef struct XtensaConfig XtensaConfig;
 * An Xtensa CPU model.
 */
 struct XtensaCPUClass {
-    /*< private >*/
    CPUClass parent_class;
-    /*< public >*/

    DeviceRealize parent_realize;
    ResettablePhases parent_phases;
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@ -556,9 +556,7 @@ struct CPUArchState {
 * An Xtensa CPU.
 */
 struct ArchCPU {
-    /*< private >*/
    CPUState parent_obj;
-    /*< public >*/

    CPUXtensaState env;
    Clock *clock;