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https://gitlab.com/qemu-project/qemu
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nvme: introduce PMR support from NVMe 1.4 spec
This patch introduces support for PMR that has been defined as part of NVMe 1.4 spec. User can now specify a pmrdev option that should point to HostMemoryBackend. pmrdev memory region will subsequently be exposed as PCI BAR 2 in emulated NVMe device. Guest OS can perform mmio read and writes to the PMR region that will stay persistent across system reboot. Signed-off-by: Andrzej Jakowski <andrzej.jakowski@linux.intel.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20200330164656.9348-1-andrzej.jakowski@linux.intel.com> Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
This commit is contained in:
Andrzej Jakowski
Kevin Wolf
parent
eb8a0cf3ba
commit
6cf9413229
5 changed files with 288 additions and 1 deletions
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@ -7,12 +7,12 @@ common-obj-$(CONFIG_PFLASH_CFI02) += pflash_cfi02.o
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common-obj-$(CONFIG_XEN) += xen-block.o
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common-obj-$(CONFIG_ECC) += ecc.o
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common-obj-$(CONFIG_ONENAND) += onenand.o
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common-obj-$(CONFIG_NVME_PCI) += nvme.o
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common-obj-$(CONFIG_SWIM) += swim.o
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common-obj-$(CONFIG_SH4) += tc58128.o
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obj-$(CONFIG_VIRTIO_BLK) += virtio-blk.o
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obj-$(CONFIG_VHOST_USER_BLK) += vhost-user-blk.o
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obj-$(CONFIG_NVME_PCI) += nvme.o
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obj-y += dataplane/
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109
hw/block/nvme.c
109
hw/block/nvme.c
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@ -19,10 +19,19 @@
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* -drive file=<file>,if=none,id=<drive_id>
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* -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>, \
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* cmb_size_mb=<cmb_size_mb[optional]>, \
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* [pmrdev=<mem_backend_file_id>,] \
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* num_queues=<N[optional]>
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*
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* Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at
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* offset 0 in BAR2 and supports only WDS, RDS and SQS for now.
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*
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* cmb_size_mb= and pmrdev= options are mutually exclusive due to limitation
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* in available BAR's. cmb_size_mb= will take precedence over pmrdev= when
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* both provided.
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* Enabling pmr emulation can be achieved by pointing to memory-backend-file.
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* For example:
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* -object memory-backend-file,id=<mem_id>,share=on,mem-path=<file_path>, \
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* size=<size> .... -device nvme,...,pmrdev=<mem_id>
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*/
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#include "qemu/osdep.h"
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@ -35,7 +44,9 @@
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#include "sysemu/sysemu.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
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#include "sysemu/hostmem.h"
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#include "sysemu/block-backend.h"
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#include "exec/ram_addr.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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@ -1141,6 +1152,26 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
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NVME_GUEST_ERR(nvme_ub_mmiowr_cmbsz_readonly,
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"invalid write to read only CMBSZ, ignored");
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return;
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case 0xE00: /* PMRCAP */
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NVME_GUEST_ERR(nvme_ub_mmiowr_pmrcap_readonly,
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"invalid write to PMRCAP register, ignored");
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return;
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case 0xE04: /* TODO PMRCTL */
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break;
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case 0xE08: /* PMRSTS */
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NVME_GUEST_ERR(nvme_ub_mmiowr_pmrsts_readonly,
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"invalid write to PMRSTS register, ignored");
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return;
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case 0xE0C: /* PMREBS */
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NVME_GUEST_ERR(nvme_ub_mmiowr_pmrebs_readonly,
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"invalid write to PMREBS register, ignored");
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return;
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case 0xE10: /* PMRSWTP */
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NVME_GUEST_ERR(nvme_ub_mmiowr_pmrswtp_readonly,
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"invalid write to PMRSWTP register, ignored");
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return;
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case 0xE14: /* TODO PMRMSC */
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break;
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default:
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NVME_GUEST_ERR(nvme_ub_mmiowr_invalid,
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"invalid MMIO write,"
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@ -1169,6 +1200,16 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
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}
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if (addr < sizeof(n->bar)) {
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/*
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* When PMRWBM bit 1 is set then read from
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* from PMRSTS should ensure prior writes
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* made it to persistent media
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*/
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if (addr == 0xE08 &&
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(NVME_PMRCAP_PMRWBM(n->bar.pmrcap) & 0x02)) {
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qemu_ram_writeback(n->pmrdev->mr.ram_block,
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0, n->pmrdev->size);
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}
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memcpy(&val, ptr + addr, size);
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} else {
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NVME_GUEST_ERR(nvme_ub_mmiord_invalid_ofs,
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@ -1332,6 +1373,23 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
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error_setg(errp, "serial property not set");
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return;
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}
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if (!n->cmb_size_mb && n->pmrdev) {
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if (host_memory_backend_is_mapped(n->pmrdev)) {
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char *path = object_get_canonical_path_component(OBJECT(n->pmrdev));
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error_setg(errp, "can't use already busy memdev: %s", path);
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g_free(path);
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return;
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}
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if (!is_power_of_2(n->pmrdev->size)) {
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error_setg(errp, "pmr backend size needs to be power of 2 in size");
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return;
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}
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host_memory_backend_set_mapped(n->pmrdev, true);
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}
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blkconf_blocksizes(&n->conf);
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if (!blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.blk),
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false, errp)) {
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@ -1415,6 +1473,51 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
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PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 |
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PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);
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} else if (n->pmrdev) {
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/* Controller Capabilities register */
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NVME_CAP_SET_PMRS(n->bar.cap, 1);
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/* PMR Capabities register */
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n->bar.pmrcap = 0;
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NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
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NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
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NVME_PMRCAP_SET_BIR(n->bar.pmrcap, 2);
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NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
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/* Turn on bit 1 support */
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NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
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NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
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NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
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/* PMR Control register */
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n->bar.pmrctl = 0;
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NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
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/* PMR Status register */
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n->bar.pmrsts = 0;
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NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
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NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
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NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
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NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
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/* PMR Elasticity Buffer Size register */
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n->bar.pmrebs = 0;
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NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
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NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
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NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
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/* PMR Sustained Write Throughput register */
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n->bar.pmrswtp = 0;
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NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
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NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
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/* PMR Memory Space Control register */
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n->bar.pmrmsc = 0;
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NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
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NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
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pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
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PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 |
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PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
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}
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for (i = 0; i < n->num_namespaces; i++) {
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@ -1445,11 +1548,17 @@ static void nvme_exit(PCIDevice *pci_dev)
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if (n->cmb_size_mb) {
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g_free(n->cmbuf);
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}
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if (n->pmrdev) {
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host_memory_backend_set_mapped(n->pmrdev, false);
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}
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msix_uninit_exclusive_bar(pci_dev);
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}
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static Property nvme_props[] = {
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DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf),
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DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmrdev, TYPE_MEMORY_BACKEND,
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HostMemoryBackend *),
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DEFINE_PROP_STRING("serial", NvmeCtrl, serial),
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DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, cmb_size_mb, 0),
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DEFINE_PROP_UINT32("num_queues", NvmeCtrl, num_queues, 64),
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@ -83,6 +83,8 @@ typedef struct NvmeCtrl {
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uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */
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char *serial;
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HostMemoryBackend *pmrdev;
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NvmeNamespace *namespaces;
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NvmeSQueue **sq;
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NvmeCQueue **cq;
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@ -110,6 +110,10 @@ nvme_ub_mmiowr_ssreset_w1c_unsupported(void) "attempted to W1C CSTS.NSSRO but CA
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nvme_ub_mmiowr_ssreset_unsupported(void) "attempted NVM subsystem reset but CAP.NSSRS is zero (not supported)"
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nvme_ub_mmiowr_cmbloc_reserved(void) "invalid write to reserved CMBLOC when CMBSZ is zero, ignored"
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nvme_ub_mmiowr_cmbsz_readonly(void) "invalid write to read only CMBSZ, ignored"
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nvme_ub_mmiowr_pmrcap_readonly(void) "invalid write to read only PMRCAP, ignored"
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nvme_ub_mmiowr_pmrsts_readonly(void) "invalid write to read only PMRSTS, ignored"
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nvme_ub_mmiowr_pmrebs_readonly(void) "invalid write to read only PMREBS, ignored"
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nvme_ub_mmiowr_pmrswtp_readonly(void) "invalid write to read only PMRSWTP, ignored"
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nvme_ub_mmiowr_invalid(uint64_t offset, uint64_t data) "invalid MMIO write, offset=0x%"PRIx64", data=0x%"PRIx64""
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nvme_ub_mmiord_misaligned32(uint64_t offset) "MMIO read not 32-bit aligned, offset=0x%"PRIx64""
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nvme_ub_mmiord_toosmall(uint64_t offset) "MMIO read smaller than 32-bits, offset=0x%"PRIx64""
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@ -15,6 +15,13 @@ typedef struct NvmeBar {
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uint64_t acq;
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uint32_t cmbloc;
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uint32_t cmbsz;
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uint8_t padding[3520]; /* not used by QEMU */
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uint32_t pmrcap;
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uint32_t pmrctl;
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uint32_t pmrsts;
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uint32_t pmrebs;
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uint32_t pmrswtp;
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uint32_t pmrmsc;
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} NvmeBar;
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enum NvmeCapShift {
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@ -27,6 +34,7 @@ enum NvmeCapShift {
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CAP_CSS_SHIFT = 37,
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CAP_MPSMIN_SHIFT = 48,
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CAP_MPSMAX_SHIFT = 52,
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CAP_PMR_SHIFT = 56,
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};
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enum NvmeCapMask {
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@ -39,6 +47,7 @@ enum NvmeCapMask {
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CAP_CSS_MASK = 0xff,
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CAP_MPSMIN_MASK = 0xf,
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CAP_MPSMAX_MASK = 0xf,
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CAP_PMR_MASK = 0x1,
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};
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#define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK)
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@ -69,6 +78,8 @@ enum NvmeCapMask {
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<< CAP_MPSMIN_SHIFT)
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#define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\
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<< CAP_MPSMAX_SHIFT)
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#define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\
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<< CAP_PMR_SHIFT)
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enum NvmeCcShift {
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CC_EN_SHIFT = 0,
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@ -205,6 +216,167 @@ enum NvmeCmbszMask {
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#define NVME_CMBSZ_GETSIZE(cmbsz) \
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(NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz))))
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enum NvmePmrcapShift {
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PMRCAP_RDS_SHIFT = 3,
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PMRCAP_WDS_SHIFT = 4,
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PMRCAP_BIR_SHIFT = 5,
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PMRCAP_PMRTU_SHIFT = 8,
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PMRCAP_PMRWBM_SHIFT = 10,
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PMRCAP_PMRTO_SHIFT = 16,
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PMRCAP_CMSS_SHIFT = 24,
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};
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enum NvmePmrcapMask {
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PMRCAP_RDS_MASK = 0x1,
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PMRCAP_WDS_MASK = 0x1,
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PMRCAP_BIR_MASK = 0x7,
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PMRCAP_PMRTU_MASK = 0x3,
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PMRCAP_PMRWBM_MASK = 0xf,
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PMRCAP_PMRTO_MASK = 0xff,
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PMRCAP_CMSS_MASK = 0x1,
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};
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#define NVME_PMRCAP_RDS(pmrcap) \
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((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK)
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#define NVME_PMRCAP_WDS(pmrcap) \
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((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK)
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#define NVME_PMRCAP_BIR(pmrcap) \
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((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK)
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#define NVME_PMRCAP_PMRTU(pmrcap) \
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((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK)
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#define NVME_PMRCAP_PMRWBM(pmrcap) \
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((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK)
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#define NVME_PMRCAP_PMRTO(pmrcap) \
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((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK)
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#define NVME_PMRCAP_CMSS(pmrcap) \
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((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK)
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#define NVME_PMRCAP_SET_RDS(pmrcap, val) \
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(pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT)
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#define NVME_PMRCAP_SET_WDS(pmrcap, val) \
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(pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT)
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#define NVME_PMRCAP_SET_BIR(pmrcap, val) \
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(pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT)
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#define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \
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(pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT)
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#define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \
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(pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT)
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#define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \
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(pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT)
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#define NVME_PMRCAP_SET_CMSS(pmrcap, val) \
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(pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT)
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enum NvmePmrctlShift {
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PMRCTL_EN_SHIFT = 0,
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};
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enum NvmePmrctlMask {
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PMRCTL_EN_MASK = 0x1,
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};
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#define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK)
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#define NVME_PMRCTL_SET_EN(pmrctl, val) \
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(pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT)
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enum NvmePmrstsShift {
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PMRSTS_ERR_SHIFT = 0,
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PMRSTS_NRDY_SHIFT = 8,
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PMRSTS_HSTS_SHIFT = 9,
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PMRSTS_CBAI_SHIFT = 12,
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};
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enum NvmePmrstsMask {
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PMRSTS_ERR_MASK = 0xff,
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PMRSTS_NRDY_MASK = 0x1,
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PMRSTS_HSTS_MASK = 0x7,
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PMRSTS_CBAI_MASK = 0x1,
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};
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#define NVME_PMRSTS_ERR(pmrsts) \
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((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK)
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#define NVME_PMRSTS_NRDY(pmrsts) \
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((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK)
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#define NVME_PMRSTS_HSTS(pmrsts) \
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((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK)
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#define NVME_PMRSTS_CBAI(pmrsts) \
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((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK)
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#define NVME_PMRSTS_SET_ERR(pmrsts, val) \
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(pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT)
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#define NVME_PMRSTS_SET_NRDY(pmrsts, val) \
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(pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT)
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#define NVME_PMRSTS_SET_HSTS(pmrsts, val) \
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(pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT)
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#define NVME_PMRSTS_SET_CBAI(pmrsts, val) \
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(pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT)
|
||||
|
||||
enum NvmePmrebsShift {
|
||||
PMREBS_PMRSZU_SHIFT = 0,
|
||||
PMREBS_RBB_SHIFT = 4,
|
||||
PMREBS_PMRWBZ_SHIFT = 8,
|
||||
};
|
||||
|
||||
enum NvmePmrebsMask {
|
||||
PMREBS_PMRSZU_MASK = 0xf,
|
||||
PMREBS_RBB_MASK = 0x1,
|
||||
PMREBS_PMRWBZ_MASK = 0xffffff,
|
||||
};
|
||||
|
||||
#define NVME_PMREBS_PMRSZU(pmrebs) \
|
||||
((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK)
|
||||
#define NVME_PMREBS_RBB(pmrebs) \
|
||||
((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK)
|
||||
#define NVME_PMREBS_PMRWBZ(pmrebs) \
|
||||
((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK)
|
||||
|
||||
#define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \
|
||||
(pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT)
|
||||
#define NVME_PMREBS_SET_RBB(pmrebs, val) \
|
||||
(pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT)
|
||||
#define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \
|
||||
(pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT)
|
||||
|
||||
enum NvmePmrswtpShift {
|
||||
PMRSWTP_PMRSWTU_SHIFT = 0,
|
||||
PMRSWTP_PMRSWTV_SHIFT = 8,
|
||||
};
|
||||
|
||||
enum NvmePmrswtpMask {
|
||||
PMRSWTP_PMRSWTU_MASK = 0xf,
|
||||
PMRSWTP_PMRSWTV_MASK = 0xffffff,
|
||||
};
|
||||
|
||||
#define NVME_PMRSWTP_PMRSWTU(pmrswtp) \
|
||||
((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK)
|
||||
#define NVME_PMRSWTP_PMRSWTV(pmrswtp) \
|
||||
((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK)
|
||||
|
||||
#define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \
|
||||
(pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT)
|
||||
#define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \
|
||||
(pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT)
|
||||
|
||||
enum NvmePmrmscShift {
|
||||
PMRMSC_CMSE_SHIFT = 1,
|
||||
PMRMSC_CBA_SHIFT = 12,
|
||||
};
|
||||
|
||||
enum NvmePmrmscMask {
|
||||
PMRMSC_CMSE_MASK = 0x1,
|
||||
PMRMSC_CBA_MASK = 0xfffffffffffff,
|
||||
};
|
||||
|
||||
#define NVME_PMRMSC_CMSE(pmrmsc) \
|
||||
((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK)
|
||||
#define NVME_PMRMSC_CBA(pmrmsc) \
|
||||
((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK)
|
||||
|
||||
#define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \
|
||||
(pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT)
|
||||
#define NVME_PMRMSC_SET_CBA(pmrmsc, val) \
|
||||
(pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT)
|
||||
|
||||
typedef struct NvmeCmd {
|
||||
uint8_t opcode;
|
||||
uint8_t fuse;
|
||||
|
|
|
|||
Loading…
Reference in a new issue