system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-09-06 09:55:55 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES

Browse source 
The bit 6, 7 and 8 of MSR_IA32_ARCH_CAPABILITIES are recently disclosed
for some security issues. Add the definitions for them to be used by named
CPU models.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-Id: <20191225063018.20038-2-xiaoyao.li@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Xiaoyao Li 2019-12-25 14:30:17 +08:00 committed by Paolo Bonzini
parent 5a07192a04
commit 6c997b4adb
1 changed files with 8 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
target/i386/cpu.h
View file

@ -835,12 +835,15 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
/* MSR Feature Bits */
#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
#define MSR_ARCH_CAP_RSBA (1U << 2)
#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
#define MSR_ARCH_CAP_RSBA (1U << 2)
#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
#define MSR_ARCH_CAP_SSB_NO (1U << 4)
#define MSR_ARCH_CAP_MDS_NO (1U << 5)
#define MSR_ARCH_CAP_SSB_NO (1U << 4)
#define MSR_ARCH_CAP_MDS_NO (1U << 5)
#define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
#define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
#define MSR_ARCH_CAP_TAA_NO (1U << 8)
#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)