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target/arm: Implement ARMv8.5-FRINT
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190301200501.16533-11-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -3476,6 +3476,11 @@ static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
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}
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static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
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}
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static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
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{
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/* We always set the AdvSIMD and FP fields identically wrt FP16. */
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@ -321,6 +321,7 @@ static void aarch64_max_initfn(Object *obj)
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t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
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t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
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cpu->isar.id_aa64isar1 = t;
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t = cpu->isar.id_aa64pfr0;
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@ -683,6 +683,11 @@ DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
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DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, ptr)
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DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr)
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DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr)
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DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr)
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#ifdef TARGET_AARCH64
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#include "helper-a64.h"
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#include "helper-sve.h"
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@ -5723,6 +5723,20 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
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case 0xf: /* FRINTI */
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gen_fpst = gen_helper_rints;
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break;
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case 0x10: /* FRINT32Z */
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rmode = float_round_to_zero;
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gen_fpst = gen_helper_frint32_s;
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break;
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case 0x11: /* FRINT32X */
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gen_fpst = gen_helper_frint32_s;
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break;
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case 0x12: /* FRINT64Z */
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rmode = float_round_to_zero;
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gen_fpst = gen_helper_frint64_s;
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break;
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case 0x13: /* FRINT64X */
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gen_fpst = gen_helper_frint64_s;
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break;
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default:
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g_assert_not_reached();
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}
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@ -5786,6 +5800,20 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
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case 0xf: /* FRINTI */
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gen_fpst = gen_helper_rintd;
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break;
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case 0x10: /* FRINT32Z */
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rmode = float_round_to_zero;
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gen_fpst = gen_helper_frint32_d;
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break;
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case 0x11: /* FRINT32X */
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gen_fpst = gen_helper_frint32_d;
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break;
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case 0x12: /* FRINT64Z */
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rmode = float_round_to_zero;
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gen_fpst = gen_helper_frint64_d;
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break;
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case 0x13: /* FRINT64X */
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gen_fpst = gen_helper_frint64_d;
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break;
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default:
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g_assert_not_reached();
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}
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@ -5922,6 +5950,13 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
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handle_fp_fcvt(s, opcode, rd, rn, dtype, type);
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break;
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}
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case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
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if (type > 1 || !dc_isar_feature(aa64_frint, s)) {
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unallocated_encoding(s);
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return;
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}
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/* fall through */
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case 0x0 ... 0x3:
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case 0x8 ... 0xc:
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case 0xe ... 0xf:
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@ -5931,14 +5966,12 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
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if (!fp_access_check(s)) {
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return;
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}
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handle_fp_1src_single(s, opcode, rd, rn);
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break;
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case 1:
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if (!fp_access_check(s)) {
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return;
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}
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handle_fp_1src_double(s, opcode, rd, rn);
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break;
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case 3:
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@ -5950,13 +5983,13 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
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if (!fp_access_check(s)) {
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return;
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}
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handle_fp_1src_half(s, opcode, rd, rn);
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break;
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default:
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unallocated_encoding(s);
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}
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break;
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default:
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unallocated_encoding(s);
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break;
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@ -9484,6 +9517,14 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
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case 0x59: /* FRINTX */
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gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus);
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break;
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case 0x1e: /* FRINT32Z */
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case 0x5e: /* FRINT32X */
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gen_helper_frint32_d(tcg_rd, tcg_rn, tcg_fpstatus);
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break;
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case 0x1f: /* FRINT64Z */
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case 0x5f: /* FRINT64X */
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gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus);
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break;
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default:
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g_assert_not_reached();
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}
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@ -12134,8 +12175,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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}
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break;
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case 0xc ... 0xf:
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case 0x16 ... 0x1d:
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case 0x1f:
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case 0x16 ... 0x1f:
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{
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/* Floating point: U, size[1] and opcode indicate operation;
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* size[0] indicates single or double precision.
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@ -12278,6 +12318,19 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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}
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need_fpstatus = true;
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break;
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case 0x1e: /* FRINT32Z */
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case 0x1f: /* FRINT64Z */
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need_rmode = true;
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rmode = FPROUNDING_ZERO;
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/* fall through */
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case 0x5e: /* FRINT32X */
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case 0x5f: /* FRINT64X */
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need_fpstatus = true;
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if ((size == 3 && !is_q) || !dc_isar_feature(aa64_frint, s)) {
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unallocated_encoding(s);
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return;
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}
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break;
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default:
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unallocated_encoding(s);
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return;
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@ -12443,6 +12496,14 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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case 0x7c: /* URSQRTE */
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gen_helper_rsqrte_u32(tcg_res, tcg_op, tcg_fpstatus);
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break;
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case 0x1e: /* FRINT32Z */
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case 0x5e: /* FRINT32X */
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gen_helper_frint32_s(tcg_res, tcg_op, tcg_fpstatus);
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break;
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case 0x1f: /* FRINT64Z */
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case 0x5f: /* FRINT64X */
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gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus);
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break;
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default:
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g_assert_not_reached();
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}
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@ -1174,3 +1174,99 @@ uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
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return result;
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}
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/* Round a float32 to an integer that fits in int32_t or int64_t. */
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static float32 frint_s(float32 f, float_status *fpst, int intsize)
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{
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int old_flags = get_float_exception_flags(fpst);
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uint32_t exp = extract32(f, 23, 8);
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if (unlikely(exp == 0xff)) {
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/* NaN or Inf. */
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goto overflow;
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}
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/* Round and re-extract the exponent. */
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f = float32_round_to_int(f, fpst);
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exp = extract32(f, 23, 8);
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/* Validate the range of the result. */
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if (exp < 126 + intsize) {
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/* abs(F) <= INT{N}_MAX */
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return f;
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}
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if (exp == 126 + intsize) {
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uint32_t sign = extract32(f, 31, 1);
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uint32_t frac = extract32(f, 0, 23);
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if (sign && frac == 0) {
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/* F == INT{N}_MIN */
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return f;
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}
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}
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overflow:
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/*
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* Raise Invalid and return INT{N}_MIN as a float. Revert any
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* inexact exception float32_round_to_int may have raised.
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*/
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set_float_exception_flags(old_flags | float_flag_invalid, fpst);
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return (0x100u + 126u + intsize) << 23;
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}
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float32 HELPER(frint32_s)(float32 f, void *fpst)
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{
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return frint_s(f, fpst, 32);
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}
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float32 HELPER(frint64_s)(float32 f, void *fpst)
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{
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return frint_s(f, fpst, 64);
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}
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/* Round a float64 to an integer that fits in int32_t or int64_t. */
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static float64 frint_d(float64 f, float_status *fpst, int intsize)
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{
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int old_flags = get_float_exception_flags(fpst);
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uint32_t exp = extract64(f, 52, 11);
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if (unlikely(exp == 0x7ff)) {
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/* NaN or Inf. */
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goto overflow;
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}
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/* Round and re-extract the exponent. */
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f = float64_round_to_int(f, fpst);
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exp = extract64(f, 52, 11);
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/* Validate the range of the result. */
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if (exp < 1022 + intsize) {
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/* abs(F) <= INT{N}_MAX */
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return f;
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}
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if (exp == 1022 + intsize) {
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uint64_t sign = extract64(f, 63, 1);
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uint64_t frac = extract64(f, 0, 52);
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if (sign && frac == 0) {
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/* F == INT{N}_MIN */
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return f;
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}
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}
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overflow:
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/*
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* Raise Invalid and return INT{N}_MIN as a float. Revert any
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* inexact exception float64_round_to_int may have raised.
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*/
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set_float_exception_flags(old_flags | float_flag_invalid, fpst);
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return (uint64_t)(0x800 + 1022 + intsize) << 52;
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}
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float64 HELPER(frint32_d)(float64 f, void *fpst)
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{
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return frint_d(f, fpst, 32);
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}
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float64 HELPER(frint64_d)(float64 f, void *fpst)
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{
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return frint_d(f, fpst, 64);
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}
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