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target/arm: Add SMEEXC_EL to TB flags
This is CheckSMEAccess, which is the basis for a set of related tests for various SME cpregs and instructions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1134,6 +1134,7 @@ void aarch64_sync_64_to_32(CPUARMState *env);
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int fp_exception_el(CPUARMState *env, int cur_el);
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int sve_exception_el(CPUARMState *env, int cur_el);
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int sme_exception_el(CPUARMState *env, int cur_el);
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/**
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* sve_vqm1_for_el:
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@ -3148,6 +3149,7 @@ FIELD(TBFLAG_A64, ATA, 15, 1)
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FIELD(TBFLAG_A64, TCMA, 16, 2)
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FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
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FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
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FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
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/*
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* Helpers for using the above.
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@ -6218,6 +6218,55 @@ int sve_exception_el(CPUARMState *env, int el)
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return 0;
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}
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/*
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* Return the exception level to which exceptions should be taken for SME.
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* C.f. the ARM pseudocode function CheckSMEAccess.
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*/
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int sme_exception_el(CPUARMState *env, int el)
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{
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#ifndef CONFIG_USER_ONLY
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if (el <= 1 && !el_is_in_host(env, el)) {
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switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, SMEN)) {
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case 1:
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if (el != 0) {
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break;
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}
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/* fall through */
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case 0:
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case 2:
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return 1;
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}
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}
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if (el <= 2 && arm_is_el2_enabled(env)) {
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/* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
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if (env->cp15.hcr_el2 & HCR_E2H) {
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switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, SMEN)) {
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case 1:
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if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) {
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break;
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}
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/* fall through */
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case 0:
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case 2:
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return 2;
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}
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} else {
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if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TSM)) {
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return 2;
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}
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}
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}
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/* CPTR_EL3. Since ESM is negative we must check for EL3. */
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if (arm_feature(env, ARM_FEATURE_EL3)
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&& !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) {
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return 3;
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}
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#endif
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return 0;
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}
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/*
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* Given that SVE is enabled, return the vector length for EL.
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*/
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@ -11197,6 +11246,9 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
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}
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DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
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}
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if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
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DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el));
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}
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sctlr = regime_sctlr(env, stage1);
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@ -14603,6 +14603,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
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dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
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dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
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dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
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dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
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dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
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dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE);
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dc->bt = EX_TBFLAG_A64(tb_flags, BT);
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@ -42,6 +42,7 @@ typedef struct DisasContext {
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bool ns; /* Use non-secure CPREG bank on access */
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int fp_excp_el; /* FP exception EL or 0 if enabled */
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int sve_excp_el; /* SVE exception EL or 0 if enabled */
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int sme_excp_el; /* SME exception EL or 0 if enabled */
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int vl; /* current vector length in bytes */
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bool vfp_enabled; /* FP enabled via FPSCR.EN */
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int vec_len;
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