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PPC: Bring EPR support closer to reality

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We already used to support the external proxy facility of FSL MPICs,
but only implemented it halfway correctly.

This patch adds support for

  * dynamic enablement of the EPR facility
  * interrupt acknowledgement only when the interrupt is delivered

This way the implementation now is closer to real hardware.

Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf 2013-01-04 11:21:04 +01:00
parent 1a61a9ae61
commit 68c2dd7006
8 changed files with 31 additions and 46 deletions
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21
hw/openpic.c
View file

@ -131,6 +131,9 @@ static const int debug_openpic = 0;
#define VIR_GENERIC 0x00000000 /* Generic Vendor ID */
#define GCR_RESET 0x80000000
#define GCR_MODE_PASS 0x00000000
#define GCR_MODE_MIXED 0x20000000
#define GCR_MODE_PROXY 0x60000000
#define TBCR_CI 0x80000000 /* count inhibit */
#define TCCR_TOG 0x80000000 /* toggles when decrement to zero */
@ -233,6 +236,7 @@ typedef struct OpenPICState {
uint32_t ivpr_reset;
uint32_t idr_reset;
uint32_t brr1;
uint32_t mpic_mode_mask;
/* Sub-regions */
MemoryRegion sub_io_mem[5];
@ -667,6 +671,20 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
case 0x1020: /* GCR */
if (val & GCR_RESET) {
openpic_reset(&opp->busdev.qdev);
} else if (opp->mpic_mode_mask) {
CPUArchState *env;
int mpic_proxy = 0;
opp->gcr &= ~opp->mpic_mode_mask;
opp->gcr |= val & opp->mpic_mode_mask;
/* Set external proxy mode */
if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) {
mpic_proxy = 1;
}
for (env = first_cpu; env != NULL; env = env->next_cpu) {
env->mpic_proxy = mpic_proxy;
}
}
break;
case 0x1080: /* VIR */
@ -1407,6 +1425,9 @@ static int openpic_init(SysBusDevice *dev)
opp->irq_tim0 = FSL_MPIC_20_TMR_IRQ;
opp->irq_msi = FSL_MPIC_20_MSI_IRQ;
opp->brr1 = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN;
/* XXX really only available as of MPIC 4.0 */
opp->mpic_mode_mask = GCR_MODE_PROXY;
msi_supported = true;
list = list_be;

4
hw/ppc/e500.c
View file

@ -497,8 +497,8 @@ void ppce500_init(PPCE500Params *params)
irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
env->mpic_cpu_base = MPC8544_CCSRBAR_BASE +
MPC8544_MPIC_REGS_OFFSET + 0x20000;
env->mpic_iack = MPC8544_CCSRBAR_BASE +
MPC8544_MPIC_REGS_OFFSET + 0x200A0;
ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);

1
target-ppc/Makefile.objs
View file

@ -9,4 +9,3 @@ obj-y += mmu_helper.o
obj-y += timebase_helper.o
obj-y += misc_helper.o
obj-y += mem_helper.o
obj-y += mpic_helper.o

4
target-ppc/cpu.h
View file

@ -1067,7 +1067,9 @@ struct CPUPPCState {
target_ulong ivor_mask;
target_ulong ivpr_mask;
target_ulong hreset_vector;
hwaddr mpic_cpu_base;
hwaddr mpic_iack;
/* true when the external proxy facility mode is enabled */
bool mpic_proxy;
#endif
/* Those resources are used only during code translation */

4
target-ppc/excp_helper.c
View file

@ -178,6 +178,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
if (lpes0 == 1) {
new_msr |= (target_ulong)MSR_HVB;
}
if (env->mpic_proxy) {
/* IACK the IRQ on delivery */
env->spr[SPR_BOOKE_EPR] = ldl_phys(env->mpic_iack);
}
goto store_next;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
if (lpes1 == 0) {

1
target-ppc/helper.h
View file

@ -405,7 +405,6 @@ DEF_HELPER_2(store_40x_dbcr0, void, env, tl)
DEF_HELPER_2(store_40x_sler, void, env, tl)
DEF_HELPER_2(store_booke_tcr, void, env, tl)
DEF_HELPER_2(store_booke_tsr, void, env, tl)
DEF_HELPER_1(load_epr, tl, env)
DEF_HELPER_3(store_ibatl, void, env, i32, tl)
DEF_HELPER_3(store_ibatu, void, env, i32, tl)
DEF_HELPER_3(store_dbatl, void, env, i32, tl)

35
target-ppc/mpic_helper.c
View file

@ -1,35 +0,0 @@
/*
* PowerPC emulation helpers for QEMU.
*
* Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "cpu.h"
#include "helper.h"
/*****************************************************************************/
/* SPR accesses */
#if !defined(CONFIG_USER_ONLY)
/*
* This is an ugly helper for EPR, which is basically the same as accessing
* the IACK (PIAC) register on the MPIC. Because we model the MPIC as a device
* that can only talk to the CPU through MMIO, let's access it that way!
*/
target_ulong helper_load_epr(CPUPPCState *env)
{
return ldl_phys(env->mpic_cpu_base + 0xA0);
}
#endif

7
target-ppc/translate_init.c
View file

@ -4493,11 +4493,6 @@ static void spr_read_mas73(void *opaque, int gprn, int sprn)
tcg_temp_free(mas7);
}
static void spr_load_epr(void *opaque, int gprn, int sprn)
{
gen_helper_load_epr(cpu_gpr[gprn], cpu_env);
}
#endif
enum fsl_e500_version {
@ -4656,7 +4651,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
0x00000000);
spr_register(env, SPR_BOOKE_EPR, "EPR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_load_epr, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
/* XXX better abstract into Emb.xxx features */
if (version == fsl_e5500) {