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target/microblaze: Store "current" iflags in insn_start
This data is available during exception unwinding, thus we can restore it from there directly, rather than saving it during the TB. Thus we may remove the t_sync_flags() calls in the load/store operations. Note that these calls were missing from the other places where runtime exceptions may be raised, such as idiv and the floating point operations. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -228,6 +228,8 @@ typedef struct CPUMBState CPUMBState;
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#define STREAM_CONTROL (1 << 3)
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#define STREAM_NONBLOCK (1 << 4)
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#define TARGET_INSN_START_EXTRA_WORDS 1
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struct CPUMBState {
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uint32_t btaken;
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uint32_t btarget;
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@ -58,6 +58,9 @@ typedef struct DisasContext {
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DisasContextBase base;
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MicroBlazeCPU *cpu;
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/* TCG op of the current insn_start. */
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TCGOp *insn_start;
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TCGv_i32 r0;
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bool r0_set;
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@ -71,7 +74,7 @@ typedef struct DisasContext {
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unsigned int cpustate_changed;
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unsigned int delayed_branch;
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unsigned int tb_flags, synced_flags; /* tb dependent flags. */
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unsigned int tb_flags;
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unsigned int clear_imm;
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int mem_index;
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@ -96,12 +99,11 @@ static int typeb_imm(DisasContext *dc, int x)
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/* Include the auto-generated decoder. */
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#include "decode-insns.c.inc"
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static inline void t_sync_flags(DisasContext *dc)
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static void t_sync_flags(DisasContext *dc)
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{
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/* Synch the tb dependent flags between translator and runtime. */
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if (dc->tb_flags != dc->synced_flags) {
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tcg_gen_movi_i32(cpu_iflags, dc->tb_flags);
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dc->synced_flags = dc->tb_flags;
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if ((dc->tb_flags ^ dc->base.tb->flags) & ~MSR_TB_MASK) {
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tcg_gen_movi_i32(cpu_iflags, dc->tb_flags & ~MSR_TB_MASK);
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}
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}
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@ -770,7 +772,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
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}
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}
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t_sync_flags(dc);
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sync_jmpstate(dc);
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/*
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@ -893,7 +894,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
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/* lwx does not throw unaligned access errors, so force alignment */
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tcg_gen_andi_tl(addr, addr, ~3);
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t_sync_flags(dc);
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sync_jmpstate(dc);
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tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL);
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@ -929,7 +929,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
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}
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}
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t_sync_flags(dc);
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sync_jmpstate(dc);
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tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop);
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@ -1046,7 +1045,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
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TCGLabel *swx_fail = gen_new_label();
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TCGv_i32 tval;
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t_sync_flags(dc);
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sync_jmpstate(dc);
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/* swx does not throw unaligned access errors, so force alignment */
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@ -1655,7 +1653,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
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int bound;
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dc->cpu = cpu;
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dc->synced_flags = dc->tb_flags = dc->base.tb->flags;
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dc->tb_flags = dc->base.tb->flags;
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dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
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dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP;
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dc->cpustate_changed = 0;
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@ -1675,7 +1673,10 @@ static void mb_tr_tb_start(DisasContextBase *dcb, CPUState *cs)
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static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs)
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{
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tcg_gen_insn_start(dcb->pc_next);
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DisasContext *dc = container_of(dcb, DisasContext, base);
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tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK);
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dc->insn_start = tcg_last_op();
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}
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static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs,
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@ -1917,4 +1918,5 @@ void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,
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target_ulong *data)
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{
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env->pc = data[0];
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env->iflags = data[1];
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}
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