From 667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 29 Aug 2015 12:59:29 -0700 Subject: [PATCH] target-*: Unconditionally emit tcg_gen_insn_start While we're at it, emit the opcode adjacent to where we currently record data for search_pc. This puts gen_io_start et al on the "correct" side of the marker. Reviewed-by: Aurelien Jarno Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target-alpha/translate.c | 6 ++---- target-arm/translate-a64.c | 5 +---- target-arm/translate.c | 5 +---- target-cris/translate.c | 5 +---- target-cris/translate_v10.c | 3 --- target-i386/translate.c | 5 ++--- target-lm32/translate.c | 5 +---- target-m68k/translate.c | 10 +++++----- target-microblaze/translate.c | 5 +---- target-mips/translate.c | 9 ++++----- target-moxie/translate.c | 6 ++---- target-openrisc/translate.c | 5 +---- target-ppc/translate.c | 5 ++--- target-s390x/translate.c | 6 ++---- target-sh4/translate.c | 14 +++++--------- target-sparc/translate.c | 10 +++++----- target-tilegx/translate.c | 6 ++---- target-tricore/translate.c | 2 ++ target-unicore32/translate.c | 5 +---- target-xtensa/translate.c | 5 +---- 20 files changed, 41 insertions(+), 81 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 76916f434a..60370d69b6 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -2933,16 +2933,14 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(ctx.pc); + if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } insn = cpu_ldl_code(env, ctx.pc); num_insns++; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(ctx.pc); - } - TCGV_UNUSED_I64(ctx.zero); TCGV_UNUSED_I64(ctx.sink); TCGV_UNUSED_I64(ctx.lit); diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index a618711b64..6a66ac019a 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11103,15 +11103,12 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(dc->pc); if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(dc->pc); - } - if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either diff --git a/target-arm/translate.c b/target-arm/translate.c index b521fc86f8..83488486b9 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11348,14 +11348,11 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(dc->pc); if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(dc->pc); - } - if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either diff --git a/target-cris/translate.c b/target-cris/translate.c index c5a22afa66..0a4b363dec 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -2994,10 +2994,6 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) int insn_len = 2; int i; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(dc->pc); - } - /* Load a halfword onto the instruction register. */ dc->ir = cris_fetch(env, dc, dc->pc, 2, 0); @@ -3197,6 +3193,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(dc->pc); /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c index 12d7dfc45e..3ab1c398e0 100644 --- a/target-cris/translate_v10.c +++ b/target-cris/translate_v10.c @@ -1199,9 +1199,6 @@ static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc) { unsigned int insn_len = 2; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_insn_start(dc->pc); - /* Load a halfword onto the instruction register. */ dc->ir = cpu_lduw_code(env, dc->pc); diff --git a/target-i386/translate.c b/target-i386/translate.c index c18f82bfd1..82d32e12f4 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -4401,9 +4401,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, target_ulong next_eip, tval; int rex_w, rex_r; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(pc_start); - } s->pc = pc_start; prefixes = 0; s->override = -1; @@ -7962,6 +7959,8 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(pc_ptr); + if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); diff --git a/target-lm32/translate.c b/target-lm32/translate.c index b1b4cbb750..84eeac3437 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1005,10 +1005,6 @@ static const DecoderInfo decinfo[] = { static inline void decode(DisasContext *dc, uint32_t ir) { - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(dc->pc); - } - dc->ir = ir; LOG_DIS("%8.8x\t", dc->ir); @@ -1106,6 +1102,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(dc->pc); /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); diff --git a/target-m68k/translate.c b/target-m68k/translate.c index e34bf2b8cd..bfd9c00edf 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -2955,10 +2955,6 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s) { uint16_t insn; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(s->pc); - } - insn = cpu_lduw_code(env, s->pc); s->pc += 2; @@ -3025,8 +3021,12 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) + tcg_gen_insn_start(dc->pc); + + if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); + } + dc->insn_pc = dc->pc; disas_m68k_insn(env, dc); num_insns++; diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 0d340c0e78..02ccf45da3 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1588,10 +1588,6 @@ static inline void decode(DisasContext *dc, uint32_t ir) { int i; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(dc->pc); - } - dc->ir = ir; LOG_DIS("%8.8x\t", dc->ir); @@ -1718,6 +1714,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(dc->pc); /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); diff --git a/target-mips/translate.c b/target-mips/translate.c index 2b3f2b00b1..aa0e0fd55e 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -18904,10 +18904,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) gen_set_label(l1); } - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(ctx->pc); - } - op = MASK_OP_MAJOR(ctx->opcode); rs = (ctx->opcode >> 21) & 0x1f; rt = (ctx->opcode >> 16) & 0x1f; @@ -19622,8 +19618,11 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) + tcg_gen_insn_start(ctx.pc); + + if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); + } is_slot = ctx.hflags & MIPS_HFLAG_BMASK; if (!(ctx.hflags & MIPS_HFLAG_M16)) { diff --git a/target-moxie/translate.c b/target-moxie/translate.c index 0bb94a02b8..1becfde1b5 100644 --- a/target-moxie/translate.c +++ b/target-moxie/translate.c @@ -153,10 +153,6 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx) /* Set the default instruction length. */ int length = 2; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(ctx->pc); - } - /* Examine the 16-bit opcode. */ opcode = ctx->opcode; @@ -865,6 +861,8 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(ctx.pc); + ctx.opcode = cpu_lduw_code(env, ctx.pc); ctx.pc += decode_opc(cpu, &ctx); num_insns++; diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 727fbba66f..4f9b76833f 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1687,10 +1687,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, tcg_ctx.gen_opc_instr_start[k] = 1; tcg_ctx.gen_opc_icount[k] = num_insns; } - - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(dc->pc); - } + tcg_gen_insn_start(dc->pc); if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); diff --git a/target-ppc/translate.c b/target-ppc/translate.c index c46133d9df..6ca3e9fca5 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11502,6 +11502,8 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(ctx.nip); + LOG_DISAS("----------------\n"); LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", ctx.nip, ctx.mem_idx, (int)msr_ir); @@ -11515,9 +11517,6 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode), ctx.le_mode ? "little" : "big"); - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(ctx.nip); - } ctx.nip += 4; table = env->opcodes; num_insns++; diff --git a/target-s390x/translate.c b/target-s390x/translate.c index a87d83c79e..2767f6a35c 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -5370,14 +5370,12 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(dc.pc); + if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(dc.pc); - } - status = NO_EXIT; if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { diff --git a/target-sh4/translate.c b/target-sh4/translate.c index d9d2c02a39..1e43e6d62d 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1790,10 +1790,6 @@ static void decode_opc(DisasContext * ctx) { uint32_t old_flags = ctx->flags; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(ctx->pc); - } - _decode_opc(ctx); if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { @@ -1876,12 +1872,12 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb, tcg_ctx.gen_opc_instr_start[ii] = 1; tcg_ctx.gen_opc_icount[ii] = num_insns; } - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) + tcg_gen_insn_start(ctx.pc); + + if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); -#if 0 - fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc); - fflush(stderr); -#endif + } + ctx.opcode = cpu_lduw_code(env, ctx.pc); decode_opc(&ctx); num_insns++; diff --git a/target-sparc/translate.c b/target-sparc/translate.c index ef17e26253..a47e65f15b 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2482,10 +2482,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; target_long simm; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(dc->pc); - } - opc = GET_FIELD(insn, 0, 1); rd = GET_FIELD(insn, 2, 6); @@ -5271,8 +5267,12 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu, tcg_ctx.gen_opc_icount[lj] = num_insns; } } - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) + tcg_gen_insn_start(dc->pc); + + if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); + } + last_pc = dc->pc; insn = cpu_ldl_code(env, dc->pc); diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 3fb7fc6a21..6babc3c733 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -2008,10 +2008,6 @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle) } dc->num_wb = 0; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(dc->pc); - } - qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc); if (get_Mode(bundle)) { notice_excp(dc, bundle, "y0", decode_y0(dc, bundle)); @@ -2100,6 +2096,8 @@ static inline void gen_intermediate_code_internal(TileGXCPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(dc->pc); + translate_one_bundle(dc, cpu_ldq_data(env, dc->pc)); if (dc->exit_tb) { diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 440f30a843..27564d330f 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -8292,6 +8292,8 @@ gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb, tcg_clear_temp_count(); gen_tb_start(tb); while (ctx.bstate == BS_NONE) { + tcg_gen_insn_start(ctx.pc); + ctx.opcode = cpu_ldl_code(env, ctx.pc); decode_opc(env, &ctx, 0); diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 63a5192b59..28db34a41a 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1794,10 +1794,6 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s) UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int insn; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(s->pc); - } - insn = cpu_ldl_code(env, s->pc); s->pc += 4; @@ -1941,6 +1937,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = num_insns; } + tcg_gen_insn_start(dc->pc); if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index ea777dabdd..ab9e8f9c21 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -3076,10 +3076,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu, tcg_ctx.gen_opc_instr_start[lj] = 1; tcg_ctx.gen_opc_icount[lj] = insn_count; } - - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_insn_start(dc.pc); - } + tcg_gen_insn_start(dc.pc); ++dc.ccount_delta;