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fw_cfg: move boards to fw_cfg_init_io() / fw_cfg_init_mem()
This allows us to drop the fw_cfg_init() shim and to enforce the possible mappings at compile time. Signed-off-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1419250305-31062-3-git-send-email-pbonzini@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -649,7 +649,7 @@ static FWCfgState *bochs_bios_init(void)
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int i, j;
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unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
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fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
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fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
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/* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
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*
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* SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
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@ -1170,7 +1170,7 @@ FWCfgState *xen_load_linux(const char *kernel_filename,
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assert(kernel_filename != NULL);
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fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
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fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
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rom_set_fw(fw_cfg);
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load_linux(fw_cfg, kernel_filename, initrd_filename,
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@ -632,20 +632,6 @@ FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr)
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}
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FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
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hwaddr crl_addr, hwaddr data_addr)
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{
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if (ctl_port + 1 == data_port && crl_addr == 0 && data_addr == 0) {
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return fw_cfg_init_io(ctl_port);
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}
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if (ctl_port == 0 && data_port == 0 && crl_addr != 0 && data_addr != 0) {
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return fw_cfg_init_mem(crl_addr, data_addr);
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}
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assert(false);
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return NULL;
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}
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FWCfgState *fw_cfg_find(void)
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{
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return FW_CFG(object_resolve_path(FW_CFG_PATH, NULL));
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@ -454,7 +454,7 @@ static void ppc_core99_init(MachineState *machine)
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pmac_format_nvram_partition(nvr, 0x2000);
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/* No PCI init: the BIOS will do it */
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fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
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fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
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fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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@ -313,7 +313,7 @@ static void ppc_heathrow_init(MachineState *machine)
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/* No PCI init: the BIOS will do it */
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fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
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fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
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fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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@ -1084,7 +1084,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
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ecc_init(hwdef->ecc_base, slavio_irq[28],
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hwdef->ecc_version);
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fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
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fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
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fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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@ -892,7 +892,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
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graphic_width, graphic_height, graphic_depth,
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(uint8_t *)&nd_table[0].macaddr);
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fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
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fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
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fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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@ -78,8 +78,6 @@ void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
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void *data, size_t len);
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void *fw_cfg_modify_file(FWCfgState *s, const char *filename, void *data,
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size_t len);
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FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
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hwaddr crl_addr, hwaddr data_addr);
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FWCfgState *fw_cfg_init_io(uint32_t iobase);
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FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr);
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