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Replace Qemu by QEMU in internal documentation

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The official spelling is QEMU.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Stefan Weil 2012-04-07 09:23:37 +02:00 committed by Blue Swirl
parent 071c939458
commit 6576b74b0b
5 changed files with 6 additions and 6 deletions
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2
CODING_STYLE
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@ -1,4 +1,4 @@
Qemu Coding Style
QEMU Coding Style
=================
Please use the script checkpatch.pl in the scripts directory to check

2
docs/ccid.txt
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@ -1,4 +1,4 @@
Qemu CCID Device Documentation.
QEMU CCID Device Documentation.
Contents
1. USB CCID device

2
docs/specs/ivshmem_device_spec.txt
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@ -24,7 +24,7 @@ The device currently supports 4 registers of 32-bits each. Registers
are used for synchronization between guests sharing the same memory object when
interrupts are supported (this requires using the shared memory server).
The server assigns each VM an ID number and sends this ID number to the Qemu
The server assigns each VM an ID number and sends this ID number to the QEMU
process when the guest starts.
enum ivshmem_registers {

2
target-alpha/STATUS
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@ -4,7 +4,7 @@ Alpha emulation structure:
cpu.h : CPU definitions globally exported
exec.h : CPU definitions used only for translated code execution
helper.c : helpers that can be called either by the translated code
or the Qemu core, including the exception handler.
or the QEMU core, including the exception handler.
op_helper.c : helpers that can be called only from TCG
helper.h : TCG helpers prototypes
translate.c : Alpha instructions to micro-operations translator

4
target-mips/TODO
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@ -16,7 +16,7 @@ General
Existing documentation is x86-centric.
- Reverse endianness bit not implemented
- The TLB emulation is very inefficient:
Qemu's softmmu implements a x86-style MMU, with separate entries
QEMU's softmmu implements a x86-style MMU, with separate entries
for read/write/execute, a TLB index which is just a modulo of the
virtual address, and a set of TLBs for each user/kernel/supervisor
MMU mode.
@ -25,7 +25,7 @@ General
up to 256 ASID tags as additional matching criterion (which roughly
equates to 256 MMU modes). It also has a global flag which causes
entries to match regardless of ASID.
To cope with these differences, Qemu currently flushes the TLB at
To cope with these differences, QEMU currently flushes the TLB at
each ASID change. Using the MMU modes to implement ASIDs hinges on
implementing the global bit efficiently.
- save/restore of the CPU state is not implemented (see machine.c).