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disas/nanomips: Remove __cond methods from class

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NMD class methods with the conditional_function type like
NMD::ADDIU_32__cond, NMD::ADDIU_RS5__cond, etc. are removed from the NMD
class. They're now declared global static functions. Therefore, typedef
of the function pointer, conditional_function is defined outside of the
class.

Now that conditional_function type functions are not part of the NMD
class we can't access them using the this pointer. Thus, the use of
the this pointer has been deleted.

Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-7-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Milica Lazarevic 2022-09-12 14:26:17 +02:00 committed by Philippe Mathieu-Daudé
parent 2dc0c175df
commit 655fc22f1b
2 changed files with 23 additions and 33 deletions
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42
disas/nanomips.cpp
View file

@ -784,7 +784,7 @@ int NMD::Disassemble(const uint16 * data, std::string & dis,
if ((op_code & table[i].mask) == table[i].value) {
/* possible match */
conditional_function cond = table[i].condition;
if ((cond == 0) || (this->*cond)(op_code)) {
if ((cond == NULL) || cond(op_code)) {
try
{
if (table[i].type == pool) {
@ -1672,28 +1672,28 @@ static uint64 extract_u_3_2_1_0__s1(uint64 instruction)
bool NMD::ADDIU_32__cond(uint64 instruction)
static bool ADDIU_32__cond(uint64 instruction)
{
uint64 rt = extract_rt_25_24_23_22_21(instruction);
return rt != 0;
}
bool NMD::ADDIU_RS5__cond(uint64 instruction)
static bool ADDIU_RS5__cond(uint64 instruction)
{
uint64 rt = extract_rt_9_8_7_6_5(instruction);
return rt != 0;
}
bool NMD::BALRSC_cond(uint64 instruction)
static bool BALRSC_cond(uint64 instruction)
{
uint64 rt = extract_rt_25_24_23_22_21(instruction);
return rt != 0;
}
bool NMD::BEQC_16__cond(uint64 instruction)
static bool BEQC_16__cond(uint64 instruction)
{
uint64 rs3 = extract_rs3_6_5_4(instruction);
uint64 rt3 = extract_rt3_9_8_7(instruction);
@ -1702,7 +1702,7 @@ bool NMD::BEQC_16__cond(uint64 instruction)
}
bool NMD::BNEC_16__cond(uint64 instruction)
static bool BNEC_16__cond(uint64 instruction)
{
uint64 rs3 = extract_rs3_6_5_4(instruction);
uint64 rt3 = extract_rt3_9_8_7(instruction);
@ -1711,35 +1711,35 @@ bool NMD::BNEC_16__cond(uint64 instruction)
}
bool NMD::MOVE_cond(uint64 instruction)
static bool MOVE_cond(uint64 instruction)
{
uint64 rt = extract_rt_9_8_7_6_5(instruction);
return rt != 0;
}
bool NMD::P16_BR1_cond(uint64 instruction)
static bool P16_BR1_cond(uint64 instruction)
{
uint64 u = extract_u_3_2_1_0__s1(instruction);
return u != 0;
}
bool NMD::PREF_S9__cond(uint64 instruction)
static bool PREF_S9__cond(uint64 instruction)
{
uint64 hint = extract_hint_25_24_23_22_21(instruction);
return hint != 31;
}
bool NMD::PREFE_cond(uint64 instruction)
static bool PREFE_cond(uint64 instruction)
{
uint64 hint = extract_hint_25_24_23_22_21(instruction);
return hint != 31;
}
bool NMD::SLTU_cond(uint64 instruction)
static bool SLTU_cond(uint64 instruction)
{
uint64 rd = extract_rd_15_14_13_12_11(instruction);
return rd != 0;
@ -16692,7 +16692,7 @@ NMD::Pool NMD::P_ADDIU[2] = {
0xffe00000, 0x00000000, 0 , 0,
0x0 }, /* P.RI */
{ instruction , 0 , 0 , 32,
0xfc000000, 0x00000000, &NMD::ADDIU_32_ , &NMD::ADDIU_32__cond ,
0xfc000000, 0x00000000, &NMD::ADDIU_32_ , &ADDIU_32__cond ,
0x0 }, /* ADDIU[32] */
};
@ -16790,7 +16790,7 @@ NMD::Pool NMD::P_SLTU[2] = {
0xfc00fbff, 0x20000390, 0 , 0,
0x0 }, /* P.DVP */
{ instruction , 0 , 0 , 32,
0xfc0003ff, 0x20000390, &NMD::SLTU , &NMD::SLTU_cond ,
0xfc0003ff, 0x20000390, &NMD::SLTU , &SLTU_cond ,
0x0 }, /* SLTU */
};
@ -21335,7 +21335,7 @@ NMD::Pool NMD::P_PREF_S9_[2] = {
0xffe07f00, 0xa7e01800, &NMD::SYNCI , 0,
0x0 }, /* SYNCI */
{ instruction , 0 , 0 , 32,
0xfc007f00, 0xa4001800, &NMD::PREF_S9_ , &NMD::PREF_S9__cond ,
0xfc007f00, 0xa4001800, &NMD::PREF_S9_ , &PREF_S9__cond ,
0x0 }, /* PREF[S9] */
};
@ -21547,7 +21547,7 @@ NMD::Pool NMD::P_PREFE[2] = {
0xffe07f00, 0xa7e01a00, &NMD::SYNCIE , 0,
CP0_ | EVA_ }, /* SYNCIE */
{ instruction , 0 , 0 , 32,
0xfc007f00, 0xa4001a00, &NMD::PREFE , &NMD::PREFE_cond ,
0xfc007f00, 0xa4001a00, &NMD::PREFE , &PREFE_cond ,
CP0_ | EVA_ }, /* PREFE */
};
@ -21719,7 +21719,7 @@ NMD::Pool NMD::P_BALRSC[2] = {
0xffe0f000, 0x48008000, &NMD::BRSC , 0,
0x0 }, /* BRSC */
{ call_instruction , 0 , 0 , 32,
0xfc00f000, 0x48008000, &NMD::BALRSC , &NMD::BALRSC_cond ,
0xfc00f000, 0x48008000, &NMD::BALRSC , &BALRSC_cond ,
0x0 }, /* BALRSC */
};
@ -22067,7 +22067,7 @@ NMD::Pool NMD::P16_MV[2] = {
0xffe0 , 0x1000 , 0 , 0,
0x0 }, /* P16.RI */
{ instruction , 0 , 0 , 16,
0xfc00 , 0x1000 , &NMD::MOVE , &NMD::MOVE_cond ,
0xfc00 , 0x1000 , &NMD::MOVE , &MOVE_cond ,
0x0 }, /* MOVE */
};
@ -22133,7 +22133,7 @@ NMD::Pool NMD::P_ADDIU_RS5_[2] = {
0xffe8 , 0x9008 , &NMD::NOP_16_ , 0,
0x0 }, /* NOP[16] */
{ instruction , 0 , 0 , 16,
0xfc08 , 0x9008 , &NMD::ADDIU_RS5_ , &NMD::ADDIU_RS5__cond ,
0xfc08 , 0x9008 , &NMD::ADDIU_RS5_ , &ADDIU_RS5__cond ,
0x0 }, /* ADDIU[RS5] */
};
@ -22170,10 +22170,10 @@ NMD::Pool NMD::P16_JRC[2] = {
NMD::Pool NMD::P16_BR1[2] = {
{ branch_instruction , 0 , 0 , 16,
0xfc00 , 0xd800 , &NMD::BEQC_16_ , &NMD::BEQC_16__cond ,
0xfc00 , 0xd800 , &NMD::BEQC_16_ , &BEQC_16__cond ,
XMMS_ }, /* BEQC[16] */
{ branch_instruction , 0 , 0 , 16,
0xfc00 , 0xd800 , &NMD::BNEC_16_ , &NMD::BNEC_16__cond ,
0xfc00 , 0xd800 , &NMD::BNEC_16_ , &BNEC_16__cond ,
XMMS_ }, /* BNEC[16] */
};
@ -22183,7 +22183,7 @@ NMD::Pool NMD::P16_BR[2] = {
0xfc0f , 0xd800 , 0 , 0,
0x0 }, /* P16.JRC */
{ pool , P16_BR1 , 2 , 16,
0xfc00 , 0xd800 , 0 , &NMD::P16_BR1_cond ,
0xfc00 , 0xd800 , 0 , &P16_BR1_cond ,
0x0 }, /* P16.BR1 */
};

14
disas/nanomips.h
View file

@ -64,6 +64,8 @@ typedef struct Dis_info {
img_address m_pc;
} Dis_info;
typedef bool (*conditional_function)(uint64 instruction);
class NMD
{
public:
@ -75,7 +77,6 @@ private:
typedef std::string(NMD:: *disassembly_function)(uint64 instruction,
Dis_info *info);
typedef bool(NMD:: *conditional_function)(uint64 instruction);
struct Pool {
TABLE_ENTRY_TYPE type;
@ -94,17 +95,6 @@ private:
TABLE_ENTRY_TYPE & type, const Pool *table, int table_size,
Dis_info *info);
bool ADDIU_32__cond(uint64 instruction);
bool ADDIU_RS5__cond(uint64 instruction);
bool BALRSC_cond(uint64 instruction);
bool BEQC_16__cond(uint64 instruction);
bool BNEC_16__cond(uint64 instruction);
bool MOVE_cond(uint64 instruction);
bool P16_BR1_cond(uint64 instruction);
bool PREF_S9__cond(uint64 instruction);
bool PREFE_cond(uint64 instruction);
bool SLTU_cond(uint64 instruction);
std::string ABS_D(uint64 instruction, Dis_info *info);
std::string ABS_S(uint64 instruction, Dis_info *info);
std::string ABSQ_S_PH(uint64 instruction, Dis_info *info);