system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-09-06 01:43:39 +00:00
Code Issues Packages Projects Releases Wiki Activity

hw/cxl/device: Plumb real Label Storage Area (LSA) sizing

Browse source 
This should introduce no change. Subsequent work will make use of this
new class member.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-21-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Ben Widawsky 2022-04-29 15:40:45 +01:00 committed by Michael S. Tsirkin
parent 092c6b11f2
commit 639daf8e93
3 changed files with 22 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
hw/cxl/cxl-mailbox-utils.c
View file

@ -277,6 +277,8 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd,
} QEMU_PACKED *id;
QEMU_BUILD_BUG_ON(sizeof(*id) != 0x43);
CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d);
uint64_t size = cxl_dstate->pmem_size;
if (!QEMU_IS_ALIGNED(size, 256 << 20)) {
@ -291,6 +293,7 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd,
id->total_capacity = size / (256 << 20);
id->persistent_capacity = size / (256 << 20);
id->lsa_size = cvc->get_lsa_size(ct3d);
*len = sizeof(*id);
return CXL_MBOX_SUCCESS;

9
hw/mem/cxl_type3.c
View file

@ -179,10 +179,16 @@ static Property ct3_props[] = {
DEFINE_PROP_END_OF_LIST(),
};
static uint64_t get_lsa_size(CXLType3Dev *ct3d)
{
return 0;
}
static void ct3_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
CXLType3Class *cvc = CXL_TYPE3_CLASS(oc);
pc->realize = ct3_realize;
pc->exit = ct3_exit;
@ -195,11 +201,14 @@ static void ct3_class_init(ObjectClass *oc, void *data)
dc->desc = "CXL PMEM Device (Type 3)";
dc->reset = ct3d_reset;
device_class_set_props(dc, ct3_props);
cvc->get_lsa_size = get_lsa_size;
}
static const TypeInfo ct3d_info = {
.name = TYPE_CXL_TYPE3,
.parent = TYPE_PCI_DEVICE,
.class_size = sizeof(struct CXLType3Class),
.class_init = ct3_class_init,
.instance_size = sizeof(CXLType3Dev),
.interfaces = (InterfaceInfo[]) {

11
include/hw/cxl/cxl_device.h
View file

@ -236,6 +236,7 @@ struct CXLType3Dev {
/* Properties */
HostMemoryBackend *hostmem;
HostMemoryBackend *lsa;
/* State */
CXLComponentState cxl_cstate;
@ -243,6 +244,14 @@ struct CXLType3Dev {
};
#define TYPE_CXL_TYPE3 "cxl-type3"
OBJECT_DECLARE_SIMPLE_TYPE(CXLType3Dev, CXL_TYPE3)
OBJECT_DECLARE_TYPE(CXLType3Dev, CXLType3Class, CXL_TYPE3)
struct CXLType3Class {
/* Private */
PCIDeviceClass parent_class;
/* public */
uint64_t (*get_lsa_size)(CXLType3Dev *ct3d);
};
#endif