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pci-bridge/cxl_upstream: Add a CXL switch upstream port
An initial simple upstream port emulation to allow the creation of CXL switches. The Device ID has been allocated for this use. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20220616145126.8002-2-Jonathan.Cameron@huawei.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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216
hw/pci-bridge/cxl_upstream.c
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216
hw/pci-bridge/cxl_upstream.c
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@ -0,0 +1,216 @@
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/*
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* Emulated CXL Switch Upstream Port
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*
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* Copyright (c) 2022 Huawei Technologies.
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*
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* Based on xio3130_upstream.c
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/pcie.h"
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#include "hw/pci/pcie_port.h"
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#define CXL_UPSTREAM_PORT_MSI_NR_VECTOR 1
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#define CXL_UPSTREAM_PORT_MSI_OFFSET 0x70
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#define CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET 0x90
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#define CXL_UPSTREAM_PORT_AER_OFFSET 0x100
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#define CXL_UPSTREAM_PORT_DVSEC_OFFSET \
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(CXL_UPSTREAM_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
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typedef struct CXLUpstreamPort {
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/*< private >*/
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PCIEPort parent_obj;
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/*< public >*/
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CXLComponentState cxl_cstate;
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} CXLUpstreamPort;
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CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp)
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{
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return &usp->cxl_cstate;
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}
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static void cxl_usp_dvsec_write_config(PCIDevice *dev, uint32_t addr,
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uint32_t val, int len)
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{
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CXLUpstreamPort *usp = CXL_USP(dev);
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if (range_contains(&usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC], addr)) {
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uint8_t *reg = &dev->config[addr];
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addr -= usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC].lob;
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if (addr == PORT_CONTROL_OFFSET) {
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if (pci_get_word(reg) & PORT_CONTROL_UNMASK_SBR) {
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/* unmask SBR */
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qemu_log_mask(LOG_UNIMP, "SBR mask control is not supported\n");
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}
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if (pci_get_word(reg) & PORT_CONTROL_ALT_MEMID_EN) {
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/* Alt Memory & ID Space Enable */
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qemu_log_mask(LOG_UNIMP,
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"Alt Memory & ID space is not supported\n");
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}
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}
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}
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}
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static void cxl_usp_write_config(PCIDevice *d, uint32_t address,
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uint32_t val, int len)
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{
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pci_bridge_write_config(d, address, val, len);
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pcie_cap_flr_write_config(d, address, val, len);
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pcie_aer_write_config(d, address, val, len);
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cxl_usp_dvsec_write_config(d, address, val, len);
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}
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static void latch_registers(CXLUpstreamPort *usp)
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{
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uint32_t *reg_state = usp->cxl_cstate.crb.cache_mem_registers;
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uint32_t *write_msk = usp->cxl_cstate.crb.cache_mem_regs_write_mask;
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cxl_component_register_init_common(reg_state, write_msk,
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CXL2_UPSTREAM_PORT);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 8);
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}
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static void cxl_usp_reset(DeviceState *qdev)
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{
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PCIDevice *d = PCI_DEVICE(qdev);
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CXLUpstreamPort *usp = CXL_USP(qdev);
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pci_bridge_reset(qdev);
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pcie_cap_deverr_reset(d);
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latch_registers(usp);
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}
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static void build_dvsecs(CXLComponentState *cxl)
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{
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uint8_t *dvsec;
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dvsec = (uint8_t *)&(CXLDVSECPortExtensions){
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.status = 0x1, /* Port Power Management Init Complete */
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};
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cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT,
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EXTENSIONS_PORT_DVSEC_LENGTH,
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EXTENSIONS_PORT_DVSEC,
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EXTENSIONS_PORT_DVSEC_REVID, dvsec);
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dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){
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.cap = 0x27, /* Cache, IO, Mem, non-MLD */
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.ctrl = 0x27, /* Cache, IO, Mem */
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.status = 0x26, /* same */
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.rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */
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};
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cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT,
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PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0,
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PCIE_FLEXBUS_PORT_DVSEC,
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PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0, dvsec);
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dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
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.rsvd = 0,
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.reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
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.reg0_base_hi = 0,
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};
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cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT,
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REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
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REG_LOC_DVSEC_REVID, dvsec);
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}
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static void cxl_usp_realize(PCIDevice *d, Error **errp)
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{
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PCIEPort *p = PCIE_PORT(d);
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CXLUpstreamPort *usp = CXL_USP(d);
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CXLComponentState *cxl_cstate = &usp->cxl_cstate;
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ComponentRegisters *cregs = &cxl_cstate->crb;
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MemoryRegion *component_bar = &cregs->component_registers;
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int rc;
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pci_bridge_initfn(d, TYPE_PCIE_BUS);
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pcie_port_init_reg(d);
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rc = msi_init(d, CXL_UPSTREAM_PORT_MSI_OFFSET,
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CXL_UPSTREAM_PORT_MSI_NR_VECTOR, true, true, errp);
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if (rc) {
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assert(rc == -ENOTSUP);
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goto err_bridge;
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}
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rc = pcie_cap_init(d, CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET,
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PCI_EXP_TYPE_UPSTREAM, p->port, errp);
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if (rc < 0) {
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goto err_msi;
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}
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pcie_cap_flr_init(d);
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pcie_cap_deverr_init(d);
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rc = pcie_aer_init(d, PCI_ERR_VER, CXL_UPSTREAM_PORT_AER_OFFSET,
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PCI_ERR_SIZEOF, errp);
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if (rc) {
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goto err_cap;
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}
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cxl_cstate->dvsec_offset = CXL_UPSTREAM_PORT_DVSEC_OFFSET;
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cxl_cstate->pdev = d;
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build_dvsecs(cxl_cstate);
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cxl_component_register_block_init(OBJECT(d), cxl_cstate, TYPE_CXL_USP);
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pci_register_bar(d, CXL_COMPONENT_REG_BAR_IDX,
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PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_TYPE_64,
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component_bar);
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return;
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err_cap:
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pcie_cap_exit(d);
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err_msi:
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msi_uninit(d);
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err_bridge:
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pci_bridge_exitfn(d);
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}
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static void cxl_usp_exitfn(PCIDevice *d)
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{
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pcie_aer_exit(d);
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pcie_cap_exit(d);
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msi_uninit(d);
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pci_bridge_exitfn(d);
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}
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static void cxl_upstream_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(oc);
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k->is_bridge = true;
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k->config_write = cxl_usp_write_config;
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k->realize = cxl_usp_realize;
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k->exit = cxl_usp_exitfn;
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k->vendor_id = 0x19e5; /* Huawei */
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k->device_id = 0xa128; /* Emulated CXL Switch Upstream Port */
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k->revision = 0;
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->desc = "CXL Switch Upstream Port";
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dc->reset = cxl_usp_reset;
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}
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static const TypeInfo cxl_usp_info = {
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.name = TYPE_CXL_USP,
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.parent = TYPE_PCIE_PORT,
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.instance_size = sizeof(CXLUpstreamPort),
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.class_init = cxl_upstream_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ INTERFACE_CXL_DEVICE },
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{ }
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},
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};
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static void cxl_usp_register_type(void)
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{
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type_register_static(&cxl_usp_info);
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}
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type_init(cxl_usp_register_type);
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@ -6,7 +6,7 @@ pci_ss.add(when: 'CONFIG_PCIE_PORT', if_true: files('pcie_root_port.c', 'gen_pci
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pci_ss.add(when: 'CONFIG_PXB', if_true: files('pci_expander_bridge.c'),
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if_false: files('pci_expander_bridge_stubs.c'))
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pci_ss.add(when: 'CONFIG_XIO3130', if_true: files('xio3130_upstream.c', 'xio3130_downstream.c'))
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pci_ss.add(when: 'CONFIG_CXL', if_true: files('cxl_root_port.c'))
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pci_ss.add(when: 'CONFIG_CXL', if_true: files('cxl_root_port.c', 'cxl_upstream.c'))
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# NewWorld PowerMac
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pci_ss.add(when: 'CONFIG_DEC_PCI', if_true: files('dec.c'))
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@ -53,4 +53,9 @@ struct CXLHost {
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#define TYPE_PXB_CXL_HOST "pxb-cxl-host"
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OBJECT_DECLARE_SIMPLE_TYPE(CXLHost, PXB_CXL_HOST)
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#define TYPE_CXL_USP "cxl-upstream"
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typedef struct CXLUpstreamPort CXLUpstreamPort;
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DECLARE_INSTANCE_CHECKER(CXLUpstreamPort, CXL_USP, TYPE_CXL_USP)
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CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp);
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#endif
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