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- buildsys

Browse source 
- Various header cleaned up (removing pointless headers)
   - Mark various files/code user/system specific
   - Make various objects target-independent
   - Remove tswapN() calls from dump.o
   - Suggest g_assert_not_reached() instead of assert(0)
 
 - qdev / qom
   - Replace various container_of() by QOM cast macros
   - Declare some QOM macros using OBJECT_DECLARE_TYPE()
   - Embed OHCI QOM child in SM501 chipset
 
 - hw (ISA & IDE)
   - add some documentation, improve function names
   - un-inline, open-code few functions
   - have ISA API accessing IRQ/DMA prefer ISABus over ISADevice
   - Demote IDE subsystem maintenance to "Odd Fixes"
 
 - ui: Improve Ctrl+Alt hint on Darwin Cocoa
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Merge tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu into staging

- buildsys
  - Various header cleaned up (removing pointless headers)
  - Mark various files/code user/system specific
  - Make various objects target-independent
  - Remove tswapN() calls from dump.o
  - Suggest g_assert_not_reached() instead of assert(0)

- qdev / qom
  - Replace various container_of() by QOM cast macros
  - Declare some QOM macros using OBJECT_DECLARE_TYPE()
  - Embed OHCI QOM child in SM501 chipset

- hw (ISA & IDE)
  - add some documentation, improve function names
  - un-inline, open-code few functions
  - have ISA API accessing IRQ/DMA prefer ISABus over ISADevice
  - Demote IDE subsystem maintenance to "Odd Fixes"

- ui: Improve Ctrl+Alt hint on Darwin Cocoa

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# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 27 Feb 2023 21:34:24 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu: (125 commits)
  ui/cocoa: user friendly characters for release mouse
  dump: Add create_win_dump() stub for non-x86 targets
  dump: Simplify compiling win_dump.o by introducing win_dump_available()
  dump: Clean included headers
  dump: Replace TARGET_PAGE_SIZE -> qemu_target_page_size()
  dump: Replace tswapN() -> cpu_to_dumpN()
  hw/ide/pci: Add PCIIDEState::isa_irq[]
  hw/ide/via: Replace magic 2 value by ARRAY_SIZE / MAX_IDE_DEVS
  hw/ide/piix: Refactor pci_piix_init_ports as pci_piix_init_bus per bus
  hw/ide/piix: Pass Error* to pci_piix_init_ports() for better error msg
  hw/ide/piix: Remove unused includes
  hw/ide/pci: Unexport bmdma_active_if()
  hw/ide/ioport: Remove unnecessary includes
  hw/ide: Declare ide_get_[geometry/bios_chs_trans] in 'hw/ide/internal.h'
  hw/ide: Rename idebus_active_if() -> ide_bus_active_if()
  hw/ide: Rename ide_init2() -> ide_bus_init_output_irq()
  hw/ide: Rename ide_exec_cmd() -> ide_bus_exec_cmd()
  hw/ide: Rename ide_register_restart_cb -> ide_bus_register_restart_cb
  hw/ide: Rename ide_create_drive() -> ide_bus_create_drive()
  hw/ide: Rename ide_set_irq() -> ide_bus_set_irq()
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-02-28 15:09:18 +00:00
parent 33dc95d032 23bdd0de97
commit 6276340310
173 changed files with 2179 additions and 1962 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
MAINTAINERS
View file

@ -123,6 +123,7 @@ M: Richard Henderson <richard.henderson@linaro.org>
R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: softmmu/cpus.c
F: softmmu/watchpoint.c
F: cpus-common.c
F: page-vary.c
F: page-vary-common.c
@ -1679,6 +1680,7 @@ F: hw/i2c/smbus_ich9.c
F: hw/acpi/piix4.c
F: hw/acpi/ich9*.c
F: include/hw/acpi/ich9*.h
F: include/hw/southbridge/ich9.h
F: include/hw/southbridge/piix.h
F: hw/isa/apm.c
F: include/hw/isa/apm.h
@ -1711,6 +1713,7 @@ F: include/hw/char/parallel.h
F: include/hw/dma/i8257.h
F: include/hw/i2c/pm_smbus.h
F: include/hw/input/i8042.h
F: include/hw/intc/ioapic*
F: include/hw/isa/i8259_internal.h
F: include/hw/isa/superio.h
F: include/hw/timer/hpet.h
@ -1795,7 +1798,7 @@ F: hw/misc/edu.c
IDE
M: John Snow <jsnow@redhat.com>
L: qemu-block@nongnu.org
S: Supported
S: Odd Fixes
F: include/hw/ide.h
F: include/hw/ide/
F: hw/ide/
@ -1820,7 +1823,7 @@ T: git https://github.com/cminyard/qemu.git master-ipmi-rebase
Floppy
M: John Snow <jsnow@redhat.com>
L: qemu-block@nongnu.org
S: Supported
S: Odd Fixes
F: hw/block/fdc.c
F: hw/block/fdc-internal.h
F: hw/block/fdc-isa.c
@ -3239,6 +3242,7 @@ S: Supported
F: replay/*
F: block/blkreplay.c
F: net/filter-replay.c
F: include/exec/replay-core.h
F: include/sysemu/replay.h
F: docs/devel/replay.rst
F: docs/system/replay.rst

8
accel/kvm/kvm-all.c
View file

@ -2361,13 +2361,13 @@ static int kvm_init(MachineState *ms)
static const char upgrade_note[] =
"Please upgrade to at least kernel 2.6.29 or recent kvm-kmod\n"
"(see http://sourceforge.net/projects/kvm).\n";
struct {
const struct {
const char *name;
int num;
} num_cpus[] = {
{ "SMP", ms->smp.cpus },
{ "hotpluggable", ms->smp.max_cpus },
{ NULL, }
{ /* end of list */ }
}, *nc = num_cpus;
int soft_vcpus_limit, hard_vcpus_limit;
KVMState *s;
@ -3305,7 +3305,7 @@ bool kvm_supports_guest_debug(void)
return kvm_has_guest_debug;
}
int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len)
int kvm_insert_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len)
{
struct kvm_sw_breakpoint *bp;
int err;
@ -3343,7 +3343,7 @@ int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len)
return 0;
}
int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len)
int kvm_remove_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len)
{
struct kvm_sw_breakpoint *bp;
int err;

4
accel/kvm/kvm-cpus.h
View file

@ -19,8 +19,8 @@ void kvm_cpu_synchronize_post_reset(CPUState *cpu);
void kvm_cpu_synchronize_post_init(CPUState *cpu);
void kvm_cpu_synchronize_pre_loadvm(CPUState *cpu);
bool kvm_supports_guest_debug(void);
int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len);
int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len);
int kvm_insert_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len);
int kvm_remove_breakpoint(CPUState *cpu, int type, vaddr addr, vaddr len);
void kvm_remove_all_breakpoints(CPUState *cpu);
#endif /* KVM_CPUS_H */

91
accel/tcg/cpu-exec.c
View file

@ -20,7 +20,6 @@
#include "qemu/osdep.h"
#include "qemu/qemu-print.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-machine.h"
#include "qapi/type-helpers.h"
#include "hw/core/tcg-cpu-ops.h"
#include "trace.h"
@ -28,7 +27,6 @@
#include "exec/exec-all.h"
#include "tcg/tcg.h"
#include "qemu/atomic.h"
#include "qemu/timer.h"
#include "qemu/rcu.h"
#include "exec/log.h"
#include "qemu/main-loop.h"
@ -38,7 +36,7 @@
#include "sysemu/cpus.h"
#include "exec/cpu-all.h"
#include "sysemu/cpu-timers.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
#include "sysemu/tcg.h"
#include "exec/helper-proto.h"
#include "tb-jmp-cache.h"
@ -64,8 +62,8 @@ typedef struct SyncClocks {
#define MAX_DELAY_PRINT_RATE 2000000000LL
#define MAX_NB_PRINTS 100
static int64_t max_delay;
static int64_t max_advance;
int64_t max_delay;
int64_t max_advance;
static void align_clocks(SyncClocks *sc, CPUState *cpu)
{
@ -1072,86 +1070,3 @@ void tcg_exec_unrealizefn(CPUState *cpu)
tlb_destroy(cpu);
g_free_rcu(cpu->tb_jmp_cache, rcu);
}
#ifndef CONFIG_USER_ONLY
static void dump_drift_info(GString *buf)
{
if (!icount_enabled()) {
return;
}
g_string_append_printf(buf, "Host - Guest clock %"PRIi64" ms\n",
(cpu_get_clock() - icount_get()) / SCALE_MS);
if (icount_align_option) {
g_string_append_printf(buf, "Max guest delay %"PRIi64" ms\n",
-max_delay / SCALE_MS);
g_string_append_printf(buf, "Max guest advance %"PRIi64" ms\n",
max_advance / SCALE_MS);
} else {
g_string_append_printf(buf, "Max guest delay NA\n");
g_string_append_printf(buf, "Max guest advance NA\n");
}
}
HumanReadableText *qmp_x_query_jit(Error **errp)
{
g_autoptr(GString) buf = g_string_new("");
if (!tcg_enabled()) {
error_setg(errp, "JIT information is only available with accel=tcg");
return NULL;
}
dump_exec_info(buf);
dump_drift_info(buf);
return human_readable_text_from_str(buf);
}
HumanReadableText *qmp_x_query_opcount(Error **errp)
{
g_autoptr(GString) buf = g_string_new("");
if (!tcg_enabled()) {
error_setg(errp, "Opcode count information is only available with accel=tcg");
return NULL;
}
tcg_dump_op_count(buf);
return human_readable_text_from_str(buf);
}
#ifdef CONFIG_PROFILER
int64_t dev_time;
HumanReadableText *qmp_x_query_profile(Error **errp)
{
g_autoptr(GString) buf = g_string_new("");
static int64_t last_cpu_exec_time;
int64_t cpu_exec_time;
int64_t delta;
cpu_exec_time = tcg_cpu_exec_time();
delta = cpu_exec_time - last_cpu_exec_time;
g_string_append_printf(buf, "async time %" PRId64 " (%0.3f)\n",
dev_time, dev_time / (double)NANOSECONDS_PER_SECOND);
g_string_append_printf(buf, "qemu time %" PRId64 " (%0.3f)\n",
delta, delta / (double)NANOSECONDS_PER_SECOND);
last_cpu_exec_time = cpu_exec_time;
dev_time = 0;
return human_readable_text_from_str(buf);
}
#else
HumanReadableText *qmp_x_query_profile(Error **errp)
{
error_setg(errp, "Internal profiler not compiled");
return NULL;
}
#endif
#endif /* !CONFIG_USER_ONLY */

14
accel/tcg/hmp.c
View file

@ -1,14 +0,0 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-machine.h"
#include "exec/exec-all.h"
#include "monitor/monitor.h"
static void hmp_tcg_register(void)
{
monitor_register_hmp_info_hrt("jit", qmp_x_query_jit);
monitor_register_hmp_info_hrt("opcount", qmp_x_query_opcount);
}
type_init(hmp_tcg_register);

3
accel/tcg/internal.h
View file

@ -64,4 +64,7 @@ static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *tb)
#endif
}
extern int64_t max_delay;
extern int64_t max_advance;
#endif /* ACCEL_TCG_INTERNAL_H */

2
accel/tcg/meson.build
View file

@ -18,7 +18,7 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
'cputlb.c',
'hmp.c',
'monitor.c',
))
tcg_module_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(

106
accel/tcg/monitor.c Normal file
View file

@ -0,0 +1,106 @@
/*
* SPDX-License-Identifier: LGPL-2.1-or-later
*
* QEMU TCG monitor
*
* Copyright (c) 2003-2005 Fabrice Bellard
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qapi/type-helpers.h"
#include "qapi/qapi-commands-machine.h"
#include "monitor/monitor.h"
#include "sysemu/cpus.h"
#include "sysemu/cpu-timers.h"
#include "sysemu/tcg.h"
#include "internal.h"
static void dump_drift_info(GString *buf)
{
if (!icount_enabled()) {
return;
}
g_string_append_printf(buf, "Host - Guest clock %"PRIi64" ms\n",
(cpu_get_clock() - icount_get()) / SCALE_MS);
if (icount_align_option) {
g_string_append_printf(buf, "Max guest delay %"PRIi64" ms\n",
-max_delay / SCALE_MS);
g_string_append_printf(buf, "Max guest advance %"PRIi64" ms\n",
max_advance / SCALE_MS);
} else {
g_string_append_printf(buf, "Max guest delay NA\n");
g_string_append_printf(buf, "Max guest advance NA\n");
}
}
HumanReadableText *qmp_x_query_jit(Error **errp)
{
g_autoptr(GString) buf = g_string_new("");
if (!tcg_enabled()) {
error_setg(errp, "JIT information is only available with accel=tcg");
return NULL;
}
dump_exec_info(buf);
dump_drift_info(buf);
return human_readable_text_from_str(buf);
}
HumanReadableText *qmp_x_query_opcount(Error **errp)
{
g_autoptr(GString) buf = g_string_new("");
if (!tcg_enabled()) {
error_setg(errp,
"Opcode count information is only available with accel=tcg");
return NULL;
}
tcg_dump_op_count(buf);
return human_readable_text_from_str(buf);
}
#ifdef CONFIG_PROFILER
int64_t dev_time;
HumanReadableText *qmp_x_query_profile(Error **errp)
{
g_autoptr(GString) buf = g_string_new("");
static int64_t last_cpu_exec_time;
int64_t cpu_exec_time;
int64_t delta;
cpu_exec_time = tcg_cpu_exec_time();
delta = cpu_exec_time - last_cpu_exec_time;
g_string_append_printf(buf, "async time %" PRId64 " (%0.3f)\n",
dev_time, dev_time / (double)NANOSECONDS_PER_SECOND);
g_string_append_printf(buf, "qemu time %" PRId64 " (%0.3f)\n",
delta, delta / (double)NANOSECONDS_PER_SECOND);
last_cpu_exec_time = cpu_exec_time;
dev_time = 0;
return human_readable_text_from_str(buf);
}
#else
HumanReadableText *qmp_x_query_profile(Error **errp)
{
error_setg(errp, "Internal profiler not compiled");
return NULL;
}
#endif
static void hmp_tcg_register(void)
{
monitor_register_hmp_info_hrt("jit", qmp_x_query_jit);
monitor_register_hmp_info_hrt("opcount", qmp_x_query_opcount);
}
type_init(hmp_tcg_register);

17
accel/tcg/tcg-accel-ops.c
View file

@ -44,7 +44,18 @@
void tcg_cpu_init_cflags(CPUState *cpu, bool parallel)
{
uint32_t cflags = cpu->cluster_index << CF_CLUSTER_SHIFT;
uint32_t cflags;
/*
* Include the cluster number in the hash we use to look up TBs.
* This is important because a TB that is valid for one cluster at
* a given physical address and set of CPU flags is not necessarily
* valid for another:
* the two clusters may have different views of physical memory, or
* may have different CPU features (eg FPU present or absent).
*/
cflags = cpu->cluster_index << CF_CLUSTER_SHIFT;
cflags |= parallel ? CF_PARALLEL : 0;
cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
cpu->tcg_cflags = cflags;
@ -116,7 +127,7 @@ static inline int xlat_gdb_type(CPUState *cpu, int gdbtype)
return cputype;
}
static int tcg_insert_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr len)
static int tcg_insert_breakpoint(CPUState *cs, int type, vaddr addr, vaddr len)
{
CPUState *cpu;
int err = 0;
@ -147,7 +158,7 @@ static int tcg_insert_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr len
}
}
static int tcg_remove_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr len)
static int tcg_remove_breakpoint(CPUState *cs, int type, vaddr addr, vaddr len)
{
CPUState *cpu;
int err = 0;

2
accel/tcg/tcg-all.c
View file

@ -25,7 +25,7 @@
#include "qemu/osdep.h"
#include "sysemu/tcg.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
#include "sysemu/cpu-timers.h"
#include "tcg/tcg.h"
#include "qapi/error.h"

1
accel/tcg/translate-all.c
View file

@ -49,7 +49,6 @@
#include "exec/translator.h"
#include "qemu/bitmap.h"
#include "qemu/qemu-print.h"
#include "qemu/timer.h"
#include "qemu/main-loop.h"
#include "qemu/cacheinfo.h"
#include "exec/log.h"

2
accel/tcg/translator.c
View file

@ -16,7 +16,7 @@
#include "exec/log.h"
#include "exec/translator.h"
#include "exec/plugin-gen.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
/* Pairs with tcg_clear_temp_count.
To be called by #TranslatorOps.{translate_insn,tb_stop} if

2
accel/tcg/user-exec-stub.c
View file

@ -1,6 +1,6 @@
#include "qemu/osdep.h"
#include "hw/core/cpu.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
bool enable_cpu_pm = false;

10
accel/xen/xen-all.c
View file

@ -23,16 +23,6 @@
#include "migration/global_state.h"
#include "hw/boards.h"
//#define DEBUG_XEN
#ifdef DEBUG_XEN
#define DPRINTF(fmt, ...) \
do { fprintf(stderr, "xen: " fmt, ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) \
do { } while (0)
#endif
bool xen_allowed;
xc_interface *xen_xc;

3
block/vvfat.c
View file

@ -2784,13 +2784,10 @@ static int handle_commits(BDRVVVFATState* s)
fail = -2;
break;
case ACTION_WRITEOUT: {
#ifndef NDEBUG
/* these variables are only used by assert() below */
direntry_t* entry = array_get(&(s->directory),
commit->param.writeout.dir_index);
uint32_t begin = begin_of_direntry(entry);
mapping_t* mapping = find_mapping_for_cluster(s, begin);
#endif
assert(mapping);
assert(mapping->begin == begin);

73
cpu.c
View file

@ -33,7 +33,7 @@
#endif
#include "sysemu/tcg.h"
#include "sysemu/kvm.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
#include "exec/translate-all.h"
@ -319,77 +319,6 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
}
#endif
/* Add a breakpoint. */
int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
CPUBreakpoint **breakpoint)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
CPUBreakpoint *bp;
if (cc->gdb_adjust_breakpoint) {
pc = cc->gdb_adjust_breakpoint(cpu, pc);
}
bp = g_malloc(sizeof(*bp));
bp->pc = pc;
bp->flags = flags;
/* keep all GDB-injected breakpoints in front */
if (flags & BP_GDB) {
QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
} else {
QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
}
if (breakpoint) {
*breakpoint = bp;
}
trace_breakpoint_insert(cpu->cpu_index, pc, flags);
return 0;
}
/* Remove a specific breakpoint. */
int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
CPUBreakpoint *bp;
if (cc->gdb_adjust_breakpoint) {
pc = cc->gdb_adjust_breakpoint(cpu, pc);
}
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
if (bp->pc == pc && bp->flags == flags) {
cpu_breakpoint_remove_by_ref(cpu, bp);
return 0;
}
}
return -ENOENT;
}
/* Remove a specific breakpoint by reference. */
void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp)
{
QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);
trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
g_free(bp);
}
/* Remove all matching breakpoints. */
void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
{
CPUBreakpoint *bp, *next;
QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
if (bp->flags & mask) {
cpu_breakpoint_remove_by_ref(cpu, bp);
}
}
}
/* enable or disable single step mode. EXCP_DEBUG is returned by the
CPU loop after each instruction */
void cpu_single_step(CPUState *cpu, int enabled)

72
cpus-common.c
View file

@ -23,6 +23,7 @@
#include "hw/core/cpu.h"
#include "sysemu/cpus.h"
#include "qemu/lockable.h"
#include "trace/trace-root.h"
static QemuMutex qemu_cpu_list_lock;
static QemuCond exclusive_cond;
@ -368,3 +369,74 @@ void process_queued_cpu_work(CPUState *cpu)
qemu_mutex_unlock(&cpu->work_mutex);
qemu_cond_broadcast(&qemu_work_cond);
}
/* Add a breakpoint. */
int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
CPUBreakpoint **breakpoint)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
CPUBreakpoint *bp;
if (cc->gdb_adjust_breakpoint) {
pc = cc->gdb_adjust_breakpoint(cpu, pc);
}
bp = g_malloc(sizeof(*bp));
bp->pc = pc;
bp->flags = flags;
/* keep all GDB-injected breakpoints in front */
if (flags & BP_GDB) {
QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
} else {
QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
}
if (breakpoint) {
*breakpoint = bp;
}
trace_breakpoint_insert(cpu->cpu_index, pc, flags);
return 0;
}
/* Remove a specific breakpoint. */
int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
CPUBreakpoint *bp;
if (cc->gdb_adjust_breakpoint) {
pc = cc->gdb_adjust_breakpoint(cpu, pc);
}
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
if (bp->pc == pc && bp->flags == flags) {
cpu_breakpoint_remove_by_ref(cpu, bp);
return 0;
}
}
return -ENOENT;
}
/* Remove a specific breakpoint by reference. */
void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp)
{
QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);
trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
g_free(bp);
}
/* Remove all matching breakpoints. */
void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
{
CPUBreakpoint *bp, *next;
QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
if (bp->flags & mask) {
cpu_breakpoint_remove_by_ref(cpu, bp);
}
}
}

2
dump/dump-hmp-cmds.c
View file

@ -1,5 +1,5 @@
/*
* Human Monitor Interface commands
* Windows crashdump (Human Monitor Interface commands)
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.

35
dump/dump.c
View file

@ -14,25 +14,21 @@
#include "qemu/osdep.h"
#include "qemu/cutils.h"
#include "elf.h"
#include "exec/hwaddr.h"
#include "qemu/bswap.h"
#include "exec/target_page.h"
#include "monitor/monitor.h"
#include "sysemu/kvm.h"
#include "sysemu/dump.h"
#include "sysemu/memory_mapping.h"
#include "sysemu/runstate.h"
#include "sysemu/cpus.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-dump.h"
#include "qapi/qapi-events-dump.h"
#include "qapi/qmp/qerror.h"
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
#include "hw/misc/vmcoreinfo.h"
#include "migration/blocker.h"
#ifdef TARGET_X86_64
#include "hw/core/cpu.h"
#include "win_dump.h"
#endif
#include <zlib.h>
#ifdef CONFIG_LZO
@ -907,13 +903,13 @@ static void get_note_sizes(DumpState *s, const void *note,
if (dump_is_64bit(s)) {
const Elf64_Nhdr *hdr = note;
note_head_sz = sizeof(Elf64_Nhdr);
name_sz = tswap64(hdr->n_namesz);
desc_sz = tswap64(hdr->n_descsz);
name_sz = cpu_to_dump64(s, hdr->n_namesz);
desc_sz = cpu_to_dump64(s, hdr->n_descsz);
} else {
const Elf32_Nhdr *hdr = note;
note_head_sz = sizeof(Elf32_Nhdr);
name_sz = tswap32(hdr->n_namesz);
desc_sz = tswap32(hdr->n_descsz);
name_sz = cpu_to_dump32(s, hdr->n_namesz);
desc_sz = cpu_to_dump32(s, hdr->n_descsz);
}
if (note_head_size) {
@ -1860,7 +1856,7 @@ static void dump_init(DumpState *s, int fd, bool has_format,
}
if (!s->dump_info.page_size) {
s->dump_info.page_size = TARGET_PAGE_SIZE;
s->dump_info.page_size = qemu_target_page_size();
}
s->note_size = cpu_get_note_size(s->dump_info.d_class,
@ -2022,9 +2018,7 @@ static void dump_process(DumpState *s, Error **errp)
DumpQueryResult *result = NULL;
if (s->has_format && s->format == DUMP_GUEST_MEMORY_FORMAT_WIN_DMP) {
#ifdef TARGET_X86_64
create_win_dump(s, errp);
#endif
} else if (s->has_format && s->format != DUMP_GUEST_MEMORY_FORMAT_ELF) {
create_kdump_vmcore(s, errp);
} else {
@ -2127,12 +2121,10 @@ void qmp_dump_guest_memory(bool paging, const char *file,
}
#endif
#ifndef TARGET_X86_64
if (has_format && format == DUMP_GUEST_MEMORY_FORMAT_WIN_DMP) {
error_setg(errp, "Windows dump is only available for x86-64");
if (has_format && format == DUMP_GUEST_MEMORY_FORMAT_WIN_DMP
&& !win_dump_available(errp)) {
return;
}
#endif
#if !defined(WIN32)
if (strstart(file, "fd:", &p)) {
@ -2214,10 +2206,9 @@ DumpGuestMemoryCapability *qmp_query_dump_guest_memory_capability(Error **errp)
QAPI_LIST_APPEND(tail, DUMP_GUEST_MEMORY_FORMAT_KDUMP_SNAPPY);
#endif
/* Windows dump is available only if target is x86_64 */
#ifdef TARGET_X86_64
QAPI_LIST_APPEND(tail, DUMP_GUEST_MEMORY_FORMAT_WIN_DMP);
#endif
if (win_dump_available(NULL)) {
QAPI_LIST_APPEND(tail, DUMP_GUEST_MEMORY_FORMAT_WIN_DMP);
}
return cap;
}

6
dump/meson.build
View file

@ -1,4 +1,2 @@
softmmu_ss.add(files('dump-hmp-cmds.c'))
specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: [files('dump.c'), snappy, lzo])
specific_ss.add(when: ['CONFIG_SOFTMMU', 'TARGET_X86_64'], if_true: files('win_dump.c'))
softmmu_ss.add([files('dump.c', 'dump-hmp-cmds.c'), snappy, lzo])
specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: files('win_dump.c'))

38
dump/win_dump.c
View file

@ -1,5 +1,5 @@
/*
* Windows crashdump
* Windows crashdump (target specific implementations)
*
* Copyright (c) 2018 Virtuozzo International GmbH
*
@ -9,19 +9,21 @@
*/
#include "qemu/osdep.h"
#include "qemu/cutils.h"
#include "elf.h"
#include "exec/hwaddr.h"
#include "monitor/monitor.h"
#include "sysemu/kvm.h"
#include "sysemu/dump.h"
#include "sysemu/memory_mapping.h"
#include "sysemu/cpus.h"
#include "qapi/error.h"
#include "qapi/qmp/qerror.h"
#include "qemu/error-report.h"
#include "hw/misc/vmcoreinfo.h"
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
#include "qemu/win_dump_defs.h"
#include "win_dump.h"
#include "cpu.h"
#if defined(TARGET_X86_64)
bool win_dump_available(Error **errp)
{
return true;
}
static size_t win_dump_ptr_size(bool x64)
{
@ -475,3 +477,19 @@ out_cr3:
return;
}
#else /* !TARGET_X86_64 */
bool win_dump_available(Error **errp)
{
error_setg(errp, "Windows dump is only available for x86-64");
return false;
}
void create_win_dump(DumpState *s, Error **errp)
{
win_dump_available(errp);
}
#endif

5
dump/win_dump.h
View file

@ -11,7 +11,10 @@
#ifndef WIN_DUMP_H
#define WIN_DUMP_H
#include "qemu/win_dump_defs.h"
#include "sysemu/dump.h"
/* Check Windows dump availability for the current target */
bool win_dump_available(Error **errp);
void create_win_dump(DumpState *s, Error **errp);

3
gdbstub/gdbstub.c
View file

@ -48,8 +48,7 @@
#include "sysemu/runstate.h"
#include "semihosting/semihost.h"
#include "exec/exec-all.h"
#include "exec/hwaddr.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
#include "internals.h"

6
gdbstub/internals.h
View file

@ -9,9 +9,11 @@
#ifndef _INTERNALS_H_
#define _INTERNALS_H_
#include "exec/cpu-common.h"
bool gdb_supports_guest_debug(void);
int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len);
int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len);
int gdb_breakpoint_insert(CPUState *cs, int type, vaddr addr, vaddr len);
int gdb_breakpoint_remove(CPUState *cs, int type, vaddr addr, vaddr len);
void gdb_breakpoint_remove_all(CPUState *cs);
#endif /* _INTERNALS_H_ */

5
gdbstub/softmmu.c
View file

@ -11,7 +11,6 @@
#include "qemu/osdep.h"
#include "exec/gdbstub.h"
#include "exec/hwaddr.h"
#include "sysemu/cpus.h"
#include "internals.h"
@ -24,7 +23,7 @@ bool gdb_supports_guest_debug(void)
return false;
}
int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len)
int gdb_breakpoint_insert(CPUState *cs, int type, vaddr addr, vaddr len)
{
const AccelOpsClass *ops = cpus_get_accel();
if (ops->insert_breakpoint) {
@ -33,7 +32,7 @@ int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len)
return -ENOSYS;
}
int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len)
int gdb_breakpoint_remove(CPUState *cs, int type, vaddr addr, vaddr len)
{
const AccelOpsClass *ops = cpus_get_accel();
if (ops->remove_breakpoint) {

5
gdbstub/user.c
View file

@ -9,7 +9,6 @@
*/
#include "qemu/osdep.h"
#include "exec/hwaddr.h"
#include "exec/gdbstub.h"
#include "hw/core/cpu.h"
#include "internals.h"
@ -20,7 +19,7 @@ bool gdb_supports_guest_debug(void)
return true;
}
int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len)
int gdb_breakpoint_insert(CPUState *cs, int type, vaddr addr, vaddr len)
{
CPUState *cpu;
int err = 0;
@ -41,7 +40,7 @@ int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len)
}
}
int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len)
int gdb_breakpoint_remove(CPUState *cs, int type, vaddr addr, vaddr len)
{
CPUState *cpu;
int err = 0;

10
hw/acpi/ich9.c
View file

@ -36,7 +36,7 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9_tco.h"
#include "hw/i386/ich9.h"
#include "hw/southbridge/ich9.h"
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"
@ -291,9 +291,7 @@ static void pm_powerdown_req(Notifier *n, void *opaque)
acpi_pm1_evt_power_down(&pm->acpi_regs);
}
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
bool smm_enabled,
qemu_irq sci_irq)
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq)
{
memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
memory_region_set_enabled(&pm->io, false);
@ -303,7 +301,7 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4,
pm->s4_val, !pm->smm_compat && !smm_enabled);
pm->s4_val, !pm->smm_compat && !pm->smm_enabled);
acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
@ -314,8 +312,6 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
"acpi-smi", 8);
memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
pm->smm_enabled = smm_enabled;
if (pm->enable_tco) {
acpi_pm_tco_init(&pm->tco_regs, &pm->io);
}

2
hw/acpi/ich9_tco.c
View file

@ -9,7 +9,7 @@
#include "qemu/osdep.h"
#include "sysemu/watchdog.h"
#include "hw/i386/ich9.h"
#include "hw/southbridge/ich9.h"
#include "migration/vmstate.h"
#include "hw/acpi/ich9_tco.h"

2
hw/arm/sbsa-ref.c
View file

@ -554,7 +554,7 @@ static void create_ahci(const SBSAMachineState *sms)
if (hd[i] == NULL) {
continue;
}
ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]);
}
}

45
hw/audio/ac97.c
View file

@ -26,43 +26,7 @@
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "qom/object.h"
enum {
AC97_Reset = 0x00,
AC97_Master_Volume_Mute = 0x02,
AC97_Headphone_Volume_Mute = 0x04,
AC97_Master_Volume_Mono_Mute = 0x06,
AC97_Master_Tone_RL = 0x08,
AC97_PC_BEEP_Volume_Mute = 0x0A,
AC97_Phone_Volume_Mute = 0x0C,
AC97_Mic_Volume_Mute = 0x0E,
AC97_Line_In_Volume_Mute = 0x10,
AC97_CD_Volume_Mute = 0x12,
AC97_Video_Volume_Mute = 0x14,
AC97_Aux_Volume_Mute = 0x16,
AC97_PCM_Out_Volume_Mute = 0x18,
AC97_Record_Select = 0x1A,
AC97_Record_Gain_Mute = 0x1C,
AC97_Record_Gain_Mic_Mute = 0x1E,
AC97_General_Purpose = 0x20,
AC97_3D_Control = 0x22,
AC97_AC_97_RESERVED = 0x24,
AC97_Powerdown_Ctrl_Stat = 0x26,
AC97_Extended_Audio_ID = 0x28,
AC97_Extended_Audio_Ctrl_Stat = 0x2A,
AC97_PCM_Front_DAC_Rate = 0x2C,
AC97_PCM_Surround_DAC_Rate = 0x2E,
AC97_PCM_LFE_DAC_Rate = 0x30,
AC97_PCM_LR_ADC_Rate = 0x32,
AC97_MIC_ADC_Rate = 0x34,
AC97_6Ch_Vol_C_LFE_Mute = 0x36,
AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
AC97_Vendor_Reserved = 0x58,
AC97_Sigmatel_Analog = 0x6c, /* We emulate a Sigmatel codec */
AC97_Sigmatel_Dac2Invert = 0x6e, /* We emulate a Sigmatel codec */
AC97_Vendor_ID1 = 0x7c,
AC97_Vendor_ID2 = 0x7e
};
#include "ac97.h"
#define SOFT_VOLUME
#define SR_FIFOE 16 /* rwc */
@ -121,11 +85,6 @@ enum {
#define BD_IOC (1 << 31)
#define BD_BUP (1 << 30)
#define EACS_VRA 1
#define EACS_VRM 8
#define MUTE_SHIFT 15
#define TYPE_AC97 "AC97"
OBJECT_DECLARE_SIMPLE_TYPE(AC97LinkState, AC97)
@ -1295,7 +1254,7 @@ static const MemoryRegionOps ac97_io_nabm_ops = {
static void ac97_on_reset(DeviceState *dev)
{
AC97LinkState *s = container_of(dev, AC97LinkState, dev.qdev);
AC97LinkState *s = AC97(dev);
reset_bm_regs(s, &s->bm_regs[0]);
reset_bm_regs(s, &s->bm_regs[1]);

65
hw/audio/ac97.h Normal file
View file

@ -0,0 +1,65 @@
/*
* Copyright (C) 2006 InnoTek Systemberatung GmbH
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* you can redistribute it and/or modify it under the terms of the GNU
* General Public License as published by the Free Software Foundation,
* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
* distribution. VirtualBox OSE is distributed in the hope that it will
* be useful, but WITHOUT ANY WARRANTY of any kind.
*
* If you received this file as part of a commercial VirtualBox
* distribution, then only the terms of your commercial VirtualBox
* license agreement apply instead of the previous paragraph.
*
* Contributions after 2012-01-13 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
*/
#ifndef AC97_H
#define AC97_H
enum {
AC97_Reset = 0x00,
AC97_Master_Volume_Mute = 0x02,
AC97_Headphone_Volume_Mute = 0x04,
AC97_Master_Volume_Mono_Mute = 0x06,
AC97_Master_Tone_RL = 0x08,
AC97_PC_BEEP_Volume_Mute = 0x0A,
AC97_Phone_Volume_Mute = 0x0C,
AC97_Mic_Volume_Mute = 0x0E,
AC97_Line_In_Volume_Mute = 0x10,
AC97_CD_Volume_Mute = 0x12,
AC97_Video_Volume_Mute = 0x14,
AC97_Aux_Volume_Mute = 0x16,
AC97_PCM_Out_Volume_Mute = 0x18,
AC97_Record_Select = 0x1A,
AC97_Record_Gain_Mute = 0x1C,
AC97_Record_Gain_Mic_Mute = 0x1E,
AC97_General_Purpose = 0x20,
AC97_3D_Control = 0x22,
AC97_AC_97_RESERVED = 0x24,
AC97_Powerdown_Ctrl_Stat = 0x26,
AC97_Extended_Audio_ID = 0x28,
AC97_Extended_Audio_Ctrl_Stat = 0x2A,
AC97_PCM_Front_DAC_Rate = 0x2C,
AC97_PCM_Surround_DAC_Rate = 0x2E,
AC97_PCM_LFE_DAC_Rate = 0x30,
AC97_PCM_LR_ADC_Rate = 0x32,
AC97_MIC_ADC_Rate = 0x34,
AC97_6Ch_Vol_C_LFE_Mute = 0x36,
AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
AC97_Vendor_Reserved = 0x58,
AC97_Sigmatel_Analog = 0x6c, /* We emulate a Sigmatel codec */
AC97_Sigmatel_Dac2Invert = 0x6e, /* We emulate a Sigmatel codec */
AC97_Vendor_ID1 = 0x7c,
AC97_Vendor_ID2 = 0x7e
};
#define EACS_VRA 1
#define EACS_VRM 8
#define MUTE_SHIFT 15
#endif /* AC97_H */

5
hw/audio/cs4231a.c
View file

@ -668,16 +668,17 @@ static void cs4231a_initfn (Object *obj)
static void cs4231a_realizefn (DeviceState *dev, Error **errp)
{
ISADevice *d = ISA_DEVICE (dev);
ISABus *bus = isa_bus_from_device(d);
CSState *s = CS4231A (dev);
IsaDmaClass *k;
s->isa_dma = isa_get_dma(isa_bus_from_device(d), s->dma);
s->isa_dma = isa_bus_get_dma(bus, s->dma);
if (!s->isa_dma) {
error_setg(errp, "ISA controller does not support DMA");
return;
}
s->pic = isa_get_irq(d, s->irq);
s->pic = isa_bus_get_irq(bus, s->irq);
k = ISADMA_GET_CLASS(s->isa_dma);
k->register_channel(s->isa_dma, s->dma, cs_dma_read, s);

10
hw/audio/es1370.c
View file

@ -256,6 +256,9 @@ static void print_sctl (uint32_t val)
#define lwarn(...)
#endif
#define TYPE_ES1370 "ES1370"
OBJECT_DECLARE_SIMPLE_TYPE(ES1370State, ES1370)
struct chan {
uint32_t shift;
uint32_t leftover;
@ -278,7 +281,6 @@ struct ES1370State {
uint32_t codec;
uint32_t sctl;
};
typedef struct ES1370State ES1370State;
struct chan_bits {
uint32_t ctl_en;
@ -292,9 +294,6 @@ struct chan_bits {
uint32_t *old_freq, uint32_t *new_freq);
};
#define TYPE_ES1370 "ES1370"
OBJECT_DECLARE_SIMPLE_TYPE(ES1370State, ES1370)
static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
uint32_t *old_freq, uint32_t *new_freq);
static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
@ -844,7 +843,8 @@ static const VMStateDescription vmstate_es1370 = {
static void es1370_on_reset(DeviceState *dev)
{
ES1370State *s = container_of(dev, ES1370State, dev.qdev);
ES1370State *s = ES1370(dev);
es1370_reset (s);
}

5
hw/audio/gus.c
View file

@ -236,11 +236,12 @@ static const MemoryRegionPortio gus_portio_list2[] = {
static void gus_realizefn (DeviceState *dev, Error **errp)
{
ISADevice *d = ISA_DEVICE(dev);
ISABus *bus = isa_bus_from_device(d);
GUSState *s = GUS (dev);
IsaDmaClass *k;
struct audsettings as;
s->isa_dma = isa_get_dma(isa_bus_from_device(d), s->emu.gusdma);
s->isa_dma = isa_bus_get_dma(bus, s->emu.gusdma);
if (!s->isa_dma) {
error_setg(errp, "ISA controller does not support DMA");
return;
@ -282,7 +283,7 @@ static void gus_realizefn (DeviceState *dev, Error **errp)
s->emu.himemaddr = s->himem;
s->emu.gusdatapos = s->emu.himemaddr + 1024 * 1024 + 32;
s->emu.opaque = s;
s->pic = isa_get_irq(d, s->emu.gusirq);
s->pic = isa_bus_get_irq(bus, s->emu.gusirq);
AUD_set_active_out (s->voice, 1);
}

7
hw/audio/hda-codec.c
View file

@ -145,7 +145,9 @@ static const char *fmt2name[] = {
[ AUDIO_FORMAT_S32 ] = "PCM-S32",
};
typedef struct HDAAudioState HDAAudioState;
#define TYPE_HDA_AUDIO "hda-audio"
OBJECT_DECLARE_SIMPLE_TYPE(HDAAudioState, HDA_AUDIO)
typedef struct HDAAudioStream HDAAudioStream;
struct HDAAudioStream {
@ -171,9 +173,6 @@ struct HDAAudioStream {
int64_t buft_start;
};
#define TYPE_HDA_AUDIO "hda-audio"
OBJECT_DECLARE_SIMPLE_TYPE(HDAAudioState, HDA_AUDIO)
struct HDAAudioState {
HDACodecDevice hda;
const char *name;

7
hw/audio/sb16.c
View file

@ -1398,17 +1398,18 @@ static void sb16_initfn (Object *obj)
static void sb16_realizefn (DeviceState *dev, Error **errp)
{
ISADevice *isadev = ISA_DEVICE (dev);
ISABus *bus = isa_bus_from_device(isadev);
SB16State *s = SB16 (dev);
IsaDmaClass *k;
s->isa_hdma = isa_get_dma(isa_bus_from_device(isadev), s->hdma);
s->isa_dma = isa_get_dma(isa_bus_from_device(isadev), s->dma);
s->isa_hdma = isa_bus_get_dma(bus, s->hdma);
s->isa_dma = isa_bus_get_dma(bus, s->dma);
if (!s->isa_dma || !s->isa_hdma) {
error_setg(errp, "ISA controller does not support DMA");
return;
}
s->pic = isa_get_irq(isadev, s->irq);
s->pic = isa_bus_get_irq(bus, s->irq);
s->mixer_regs[0x80] = magic_of_irq (s->irq);
s->mixer_regs[0x81] = (1 << s->dma) | (1 << s->hdma);

5
hw/block/fdc-isa.c
View file

@ -86,6 +86,7 @@ static const MemoryRegionPortio fdc_portio_list[] = {
static void isabus_fdc_realize(DeviceState *dev, Error **errp)
{
ISADevice *isadev = ISA_DEVICE(dev);
ISABus *bus = isa_bus_from_device(isadev);
FDCtrlISABus *isa = ISA_FDC(dev);
FDCtrl *fdctrl = &isa->state;
Error *err = NULL;
@ -94,11 +95,11 @@ static void isabus_fdc_realize(DeviceState *dev, Error **errp)
isa->iobase, fdc_portio_list, fdctrl,
"fdc");
fdctrl->irq = isa_get_irq(isadev, isa->irq);
fdctrl->irq = isa_bus_get_irq(bus, isa->irq);
fdctrl->dma_chann = isa->dma;
if (fdctrl->dma_chann != -1) {
IsaDmaClass *k;
fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
fdctrl->dma = isa_bus_get_dma(bus, isa->dma);
if (!fdctrl->dma) {
error_setg(errp, "ISA controller does not support DMA");
return;

2
hw/core/ptimer.c
View file

@ -10,7 +10,7 @@
#include "hw/ptimer.h"
#include "migration/vmstate.h"
#include "qemu/host-utils.h"
#include "sysemu/replay.h"
#include "exec/replay-core.h"
#include "sysemu/cpu-timers.h"
#include "sysemu/qtest.h"
#include "block/aio.h"

2
hw/core/qdev.c
View file

@ -330,7 +330,7 @@ bool qdev_machine_modified(void)
return qdev_hot_added || qdev_hot_removed;
}
BusState *qdev_get_parent_bus(DeviceState *dev)
BusState *qdev_get_parent_bus(const DeviceState *dev)
{
return dev->parent_bus;
}

127
hw/display/sm501.c
View file

@ -28,6 +28,7 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/char/serial.h"
#include "ui/console.h"
#include "hw/sysbus.h"
@ -691,7 +692,7 @@ static void sm501_2d_operation(SM501State *s)
unsigned int dst_pitch = (s->twoD_pitch >> 16) & 0x1FFF;
int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0;
int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt);
bool overlap = false;
bool overlap = false, fallback = false;
if ((s->twoD_stretch >> 16) & 0xF) {
qemu_log_mask(LOG_UNIMP, "sm501: only XY addressing is supported.\n");
@ -753,7 +754,7 @@ static void sm501_2d_operation(SM501State *s)
}
if ((rop_mode && rop == 0x5) || (!rop_mode && rop == 0x55)) {
/* Invert dest, is there a way to do this with pixman? */
/* DSTINVERT, is there a way to do this with pixman? */
unsigned int x, y, i;
uint8_t *d = s->local_mem + dst_base;
@ -763,6 +764,34 @@ static void sm501_2d_operation(SM501State *s)
stn_he_p(&d[i], bypp, ~ldn_he_p(&d[i], bypp));
}
}
} else if (!rop_mode && rop == 0x99) {
/* DSxn, is there a way to do this with pixman? */
unsigned int x, y, i, j;
uint8_t *sp = s->local_mem + src_base;
uint8_t *d = s->local_mem + dst_base;
for (y = 0; y < height; y++) {
i = (dst_x + (dst_y + y) * dst_pitch) * bypp;
j = (src_x + (src_y + y) * src_pitch) * bypp;
for (x = 0; x < width; x++, i += bypp, j += bypp) {
stn_he_p(&d[i], bypp,
~(ldn_he_p(&sp[j], bypp) ^ ldn_he_p(&d[i], bypp)));
}
}
} else if (!rop_mode && rop == 0xee) {
/* SRCPAINT, is there a way to do this with pixman? */
unsigned int x, y, i, j;
uint8_t *sp = s->local_mem + src_base;
uint8_t *d = s->local_mem + dst_base;
for (y = 0; y < height; y++) {
i = (dst_x + (dst_y + y) * dst_pitch) * bypp;
j = (src_x + (src_y + y) * src_pitch) * bypp;
for (x = 0; x < width; x++, i += bypp, j += bypp) {
stn_he_p(&d[i], bypp,
ldn_he_p(&sp[j], bypp) | ldn_he_p(&d[i], bypp));
}
}
} else {
/* Do copy src for unimplemented ops, better than unpainted area */
if ((rop_mode && (rop != 0xc || rop2_source_is_pattern)) ||
@ -806,25 +835,48 @@ static void sm501_2d_operation(SM501State *s)
if (tmp_stride * sizeof(uint32_t) * height > sizeof(tmp_buf)) {
tmp = g_malloc(tmp_stride * sizeof(uint32_t) * height);
}
pixman_blt((uint32_t *)&s->local_mem[src_base], tmp,
src_pitch * bypp / sizeof(uint32_t),
tmp_stride, 8 * bypp, 8 * bypp,
src_x, src_y, 0, 0, width, height);
pixman_blt(tmp, (uint32_t *)&s->local_mem[dst_base],
tmp_stride,
dst_pitch * bypp / sizeof(uint32_t),
8 * bypp, 8 * bypp,
0, 0, dst_x, dst_y, width, height);
fallback = !pixman_blt((uint32_t *)&s->local_mem[src_base],
tmp,
src_pitch * bypp / sizeof(uint32_t),
tmp_stride,
8 * bypp, 8 * bypp,
src_x, src_y, 0, 0, width, height);
if (!fallback) {
fallback = !pixman_blt(tmp,
(uint32_t *)&s->local_mem[dst_base],
tmp_stride,
dst_pitch * bypp / sizeof(uint32_t),
8 * bypp, 8 * bypp,
0, 0, dst_x, dst_y, width, height);
}
if (tmp != tmp_buf) {
g_free(tmp);
}
} else {
pixman_blt((uint32_t *)&s->local_mem[src_base],
(uint32_t *)&s->local_mem[dst_base],
src_pitch * bypp / sizeof(uint32_t),
dst_pitch * bypp / sizeof(uint32_t),
8 * bypp, 8 * bypp,
src_x, src_y, dst_x, dst_y, width, height);
fallback = !pixman_blt((uint32_t *)&s->local_mem[src_base],
(uint32_t *)&s->local_mem[dst_base],
src_pitch * bypp / sizeof(uint32_t),
dst_pitch * bypp / sizeof(uint32_t),
8 * bypp, 8 * bypp, src_x, src_y,
dst_x, dst_y, width, height);
}
if (fallback) {
uint8_t *sp = s->local_mem + src_base;
uint8_t *d = s->local_mem + dst_base;
unsigned int y, i, j;
for (y = 0; y < height; y++) {
if (overlap) { /* overlap also means rtl */
i = (dst_y + height - 1 - y) * dst_pitch;
i = (dst_x + i) * bypp;
j = (src_y + height - 1 - y) * src_pitch;
j = (src_x + j) * bypp;
memmove(&d[i], &sp[j], width * bypp);
} else {
i = (dst_x + (dst_y + y) * dst_pitch) * bypp;
j = (src_x + (src_y + y) * src_pitch) * bypp;
memcpy(&d[i], &sp[j], width * bypp);
}
}
}
}
break;
@ -839,13 +891,19 @@ static void sm501_2d_operation(SM501State *s)
color = cpu_to_le16(color);
}
if (width == 1 && height == 1) {
unsigned int i = (dst_x + dst_y * dst_pitch) * bypp;
stn_he_p(&s->local_mem[dst_base + i], bypp, color);
} else {
pixman_fill((uint32_t *)&s->local_mem[dst_base],
dst_pitch * bypp / sizeof(uint32_t),
8 * bypp, dst_x, dst_y, width, height, color);
if ((width == 1 && height == 1) ||
!pixman_fill((uint32_t *)&s->local_mem[dst_base],
dst_pitch * bypp / sizeof(uint32_t), 8 * bypp,
dst_x, dst_y, width, height, color)) {
/* fallback when pixman failed or we don't want to call it */
uint8_t *d = s->local_mem + dst_base;
unsigned int x, y, i;
for (y = 0; y < height; y++, i += dst_pitch * bypp) {
i = (dst_x + (dst_y + y) * dst_pitch) * bypp;
for (x = 0; x < width; x++, i += bypp) {
stn_he_p(&d[i], bypp, color);
}
}
}
break;
}
@ -1943,15 +2001,14 @@ struct SM501SysBusState {
/*< public >*/
SM501State state;
uint32_t vram_size;
uint32_t base;
SerialMM serial;
OHCISysBusState ohci;
};
static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
{
SM501SysBusState *s = SYSBUS_SM501(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
DeviceState *usb_dev;
MemoryRegion *mr;
sm501_init(&s->state, dev, s->vram_size);
@ -1964,13 +2021,10 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->state.mmio_region);
/* bridge to usb host emulation module */
usb_dev = qdev_new("sysbus-ohci");
qdev_prop_set_uint32(usb_dev, "num-ports", 2);
qdev_prop_set_uint64(usb_dev, "dma-offset", s->base);
sysbus_realize_and_unref(SYS_BUS_DEVICE(usb_dev), &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->ohci), &error_fatal);
memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST,
sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0));
sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ohci), 0));
sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->ohci));
/* bridge to serial emulation module */
sysbus_realize(SYS_BUS_DEVICE(&s->serial), &error_fatal);
@ -1981,7 +2035,6 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
static Property sm501_sysbus_properties[] = {
DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0),
DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0),
DEFINE_PROP_END_OF_LIST(),
};
@ -2017,15 +2070,19 @@ static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
static void sm501_sysbus_init(Object *o)
{
SM501SysBusState *sm501 = SYSBUS_SM501(o);
OHCISysBusState *ohci = &sm501->ohci;
SerialMM *smm = &sm501->serial;
object_initialize_child(o, "ohci", ohci, TYPE_SYSBUS_OHCI);
object_property_add_alias(o, "dma-offset", OBJECT(ohci), "dma-offset");
qdev_prop_set_uint32(DEVICE(ohci), "num-ports", 2);
object_initialize_child(o, "serial", smm, TYPE_SERIAL_MM);
qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2);
qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
object_property_add_alias(o, "chardev",
OBJECT(smm), "chardev");
object_property_add_alias(o, "chardev", OBJECT(smm), "chardev");
}
static const TypeInfo sm501_sysbus_info = {

2
hw/dma/i82374.c
View file

@ -125,7 +125,7 @@ static void i82374_realize(DeviceState *dev, Error **errp)
I82374State *s = I82374(dev);
ISABus *isa_bus = isa_bus_from_device(ISA_DEVICE(dev));
if (isa_get_dma(isa_bus, 0)) {
if (isa_bus_get_dma(isa_bus, 0)) {
error_setg(errp, "DMA already initialized on ISA bus");
return;
}

2
hw/hppa/machine.c
View file

@ -98,7 +98,7 @@ static ISABus *hppa_isa_bus(void)
isa_irqs = i8259_init(isa_bus,
/* qemu_allocate_irq(dino_set_isa_irq, s, 0)); */
NULL);
isa_bus_irqs(isa_bus, isa_irqs);
isa_bus_register_input_irqs(isa_bus, isa_irqs);
return isa_bus;
}

39
hw/i2c/smbus_ich9.c
View file

@ -27,7 +27,7 @@
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "hw/i386/ich9.h"
#include "hw/southbridge/ich9.h"
#include "qom/object.h"
#include "hw/acpi/acpi_aml_interface.h"
@ -80,6 +80,18 @@ static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
}
}
static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
{
ICH9SMBState *s = pmsmb->opaque;
if (enabled == s->irq_enabled) {
return;
}
s->irq_enabled = enabled;
pci_set_irq(&s->dev, enabled);
}
static void ich9_smbus_realize(PCIDevice *d, Error **errp)
{
ICH9SMBState *s = ICH9_SMB_DEVICE(d);
@ -93,6 +105,9 @@ static void ich9_smbus_realize(PCIDevice *d, Error **errp)
pm_smbus_init(&d->qdev, &s->smb, false);
pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
&s->smb.io);
s->smb.set_irq = ich9_smb_set_irq;
s->smb.opaque = s;
}
static void build_ich9_smb_aml(AcpiDevAmlIf *adev, Aml *scope)
@ -125,28 +140,6 @@ static void ich9_smb_class_init(ObjectClass *klass, void *data)
adevc->build_dev_aml = build_ich9_smb_aml;
}
static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
{
ICH9SMBState *s = pmsmb->opaque;
if (enabled == s->irq_enabled) {
return;
}
s->irq_enabled = enabled;
pci_set_irq(&s->dev, enabled);
}
I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
{
PCIDevice *d =
pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
ICH9SMBState *s = ICH9_SMB_DEVICE(d);
s->smb.set_irq = ich9_smb_set_irq;
s->smb.opaque = s;
return s->smb.smbus;
}
static const TypeInfo ich9_smb_info = {
.name = TYPE_ICH9_SMB_DEVICE,
.parent = TYPE_PCI_DEVICE,

3
hw/i386/acpi-build.c
View file

@ -55,10 +55,11 @@
#include "hw/hyperv/vmbus-bridge.h"
/* Supported chipsets: */
#include "hw/southbridge/ich9.h"
#include "hw/southbridge/piix.h"
#include "hw/acpi/pcihp.h"
#include "hw/i386/fw_cfg.h"
#include "hw/i386/ich9.h"
#include "hw/i386/pc.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci-host/i440fx.h"
#include "hw/pci-host/q35.h"

3
hw/i386/kvm/ioapic.c
View file

@ -12,9 +12,8 @@
#include "qemu/osdep.h"
#include "monitor/monitor.h"
#include "hw/i386/x86.h"
#include "hw/qdev-properties.h"
#include "hw/i386/ioapic_internal.h"
#include "hw/intc/ioapic_internal.h"
#include "hw/intc/kvm_irqcount.h"
#include "sysemu/kvm.h"

30
hw/i386/microvm.c
View file

@ -57,14 +57,14 @@
#define MICROVM_QBOOT_FILENAME "qboot.rom"
#define MICROVM_BIOS_FILENAME "bios-microvm.bin"
static void microvm_set_rtc(MicrovmMachineState *mms, ISADevice *s)
static void microvm_set_rtc(MicrovmMachineState *mms, MC146818RtcState *s)
{
X86MachineState *x86ms = X86_MACHINE(mms);
int val;
val = MIN(x86ms->below_4g_mem_size / KiB, 640);
rtc_set_memory(s, 0x15, val);
rtc_set_memory(s, 0x16, val >> 8);
mc146818rtc_set_cmos_data(s, 0x15, val);
mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
/* extended memory (next 64MiB) */
if (x86ms->below_4g_mem_size > 1 * MiB) {
val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
@ -74,10 +74,10 @@ static void microvm_set_rtc(MicrovmMachineState *mms, ISADevice *s)
if (val > 65535) {
val = 65535;
}
rtc_set_memory(s, 0x17, val);
rtc_set_memory(s, 0x18, val >> 8);
rtc_set_memory(s, 0x30, val);
rtc_set_memory(s, 0x31, val >> 8);
mc146818rtc_set_cmos_data(s, 0x17, val);
mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
mc146818rtc_set_cmos_data(s, 0x30, val);
mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
/* memory between 16MiB and 4GiB */
if (x86ms->below_4g_mem_size > 16 * MiB) {
val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
@ -87,13 +87,13 @@ static void microvm_set_rtc(MicrovmMachineState *mms, ISADevice *s)
if (val > 65535) {
val = 65535;
}
rtc_set_memory(s, 0x34, val);
rtc_set_memory(s, 0x35, val >> 8);
mc146818rtc_set_cmos_data(s, 0x34, val);
mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
/* memory above 4GiB */
val = x86ms->above_4g_mem_size / 65536;
rtc_set_memory(s, 0x5b, val);
rtc_set_memory(s, 0x5c, val >> 8);
rtc_set_memory(s, 0x5d, val >> 16);
mc146818rtc_set_cmos_data(s, 0x5b, val);
mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
}
static void create_gpex(MicrovmMachineState *mms)
@ -161,7 +161,6 @@ static void microvm_devices_init(MicrovmMachineState *mms)
const char *default_firmware;
X86MachineState *x86ms = X86_MACHINE(mms);
ISABus *isa_bus;
ISADevice *rtc_state;
GSIState *gsi_state;
int ioapics;
int i;
@ -174,7 +173,7 @@ static void microvm_devices_init(MicrovmMachineState *mms)
isa_bus = isa_bus_new(NULL, get_system_memory(), get_system_io(),
&error_abort);
isa_bus_irqs(isa_bus, x86ms->gsi);
isa_bus_register_input_irqs(isa_bus, x86ms->gsi);
ioapic_init_gsi(gsi_state, "machine");
if (ioapics > 1) {
@ -267,8 +266,7 @@ static void microvm_devices_init(MicrovmMachineState *mms)
if (mms->rtc == ON_OFF_AUTO_ON ||
(mms->rtc == ON_OFF_AUTO_AUTO && !kvm_enabled())) {
rtc_state = mc146818_rtc_init(isa_bus, 2000, NULL);
microvm_set_rtc(mms, rtc_state);
microvm_set_rtc(mms, mc146818_rtc_init(isa_bus, 2000, NULL));
}
if (mms->isa_serial) {

83
hw/i386/pc.c
View file

@ -28,13 +28,13 @@
#include "hw/i386/pc.h"
#include "hw/char/serial.h"
#include "hw/char/parallel.h"
#include "hw/i386/apic.h"
#include "hw/i386/topology.h"
#include "hw/i386/fw_cfg.h"
#include "hw/i386/vmport.h"
#include "sysemu/cpus.h"
#include "hw/block/fdc.h"
#include "hw/ide.h"
#include "hw/ide/internal.h"
#include "hw/ide/isa.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci-bridge/pci_expander_bridge.h"
@ -47,6 +47,7 @@
#include "multiboot.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/intc/i8259.h"
#include "hw/intc/ioapic.h"
#include "hw/timer/i8254.h"
#include "hw/input/i8042.h"
#include "hw/irq.h"
@ -405,7 +406,7 @@ GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
if (kvm_ioapic_in_kernel()) {
kvm_pc_setup_irq_routing(pci_enabled);
}
*irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
*irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
return s;
}
@ -438,19 +439,19 @@ static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
#define REG_EQUIPMENT_BYTE 0x14
static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
int16_t cylinders, int8_t heads, int8_t sectors)
{
rtc_set_memory(s, type_ofs, 47);
rtc_set_memory(s, info_ofs, cylinders);
rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
rtc_set_memory(s, info_ofs + 2, heads);
rtc_set_memory(s, info_ofs + 3, 0xff);
rtc_set_memory(s, info_ofs + 4, 0xff);
rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
rtc_set_memory(s, info_ofs + 6, cylinders);
rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
rtc_set_memory(s, info_ofs + 8, sectors);
mc146818rtc_set_cmos_data(s, type_ofs, 47);
mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
}
/* convert boot_device letter to something recognizable by the bios */
@ -470,7 +471,8 @@ static int boot_device2nibble(char boot_device)
return 0;
}
static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
static void set_boot_dev(MC146818RtcState *s, const char *boot_device,
Error **errp)
{
#define PC_MAX_BOOT_DEVICES 3
int nbds, bds[3] = { 0, };
@ -489,8 +491,8 @@ static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
return;
}
}
rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
}
static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
@ -498,7 +500,7 @@ static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
set_boot_dev(opaque, boot_device, errp);
}
static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
{
int val, nb, i;
FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
@ -512,9 +514,9 @@ static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
}
val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
cmos_get_fd_drive_type(fd_type[1]);
rtc_set_memory(rtc_state, 0x10, val);
mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
nb = 0;
if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
nb++;
@ -532,11 +534,11 @@ static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
val |= 0x41; /* 2 drives, ready for boot */
break;
}
rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
}
typedef struct pc_cmos_init_late_arg {
ISADevice *rtc_state;
MC146818RtcState *rtc_state;
BusState *idebus[2];
} pc_cmos_init_late_arg;
@ -603,7 +605,7 @@ static ISADevice *pc_find_fdc0(void)
static void pc_cmos_init_late(void *opaque)
{
pc_cmos_init_late_arg *arg = opaque;
ISADevice *s = arg->rtc_state;
MC146818RtcState *s = arg->rtc_state;
int16_t cylinders;
int8_t heads, sectors;
int val;
@ -620,7 +622,7 @@ static void pc_cmos_init_late(void *opaque)
cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
val |= 0x0f;
}
rtc_set_memory(s, 0x12, val);
mc146818rtc_set_cmos_data(s, 0x12, val);
val = 0;
for (i = 0; i < 4; i++) {
@ -636,7 +638,7 @@ static void pc_cmos_init_late(void *opaque)
val |= trans << (i * 2);
}
}
rtc_set_memory(s, 0x39, val);
mc146818rtc_set_cmos_data(s, 0x39, val);
pc_cmos_init_floppy(s, pc_find_fdc0());
@ -645,19 +647,20 @@ static void pc_cmos_init_late(void *opaque)
void pc_cmos_init(PCMachineState *pcms,
BusState *idebus0, BusState *idebus1,
ISADevice *s)
ISADevice *rtc)
{
int val;
static pc_cmos_init_late_arg arg;
X86MachineState *x86ms = X86_MACHINE(pcms);
MC146818RtcState *s = MC146818_RTC(rtc);
/* various important CMOS locations needed by PC/Bochs bios */
/* memory size */
/* base memory (first MiB) */
val = MIN(x86ms->below_4g_mem_size / KiB, 640);
rtc_set_memory(s, 0x15, val);
rtc_set_memory(s, 0x16, val >> 8);
mc146818rtc_set_cmos_data(s, 0x15, val);
mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
/* extended memory (next 64MiB) */
if (x86ms->below_4g_mem_size > 1 * MiB) {
val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
@ -666,10 +669,10 @@ void pc_cmos_init(PCMachineState *pcms,
}
if (val > 65535)
val = 65535;
rtc_set_memory(s, 0x17, val);
rtc_set_memory(s, 0x18, val >> 8);
rtc_set_memory(s, 0x30, val);
rtc_set_memory(s, 0x31, val >> 8);
mc146818rtc_set_cmos_data(s, 0x17, val);
mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
mc146818rtc_set_cmos_data(s, 0x30, val);
mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
/* memory between 16MiB and 4GiB */
if (x86ms->below_4g_mem_size > 16 * MiB) {
val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
@ -678,13 +681,13 @@ void pc_cmos_init(PCMachineState *pcms,
}
if (val > 65535)
val = 65535;
rtc_set_memory(s, 0x34, val);
rtc_set_memory(s, 0x35, val >> 8);
mc146818rtc_set_cmos_data(s, 0x34, val);
mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
/* memory above 4GiB */
val = x86ms->above_4g_mem_size / 65536;
rtc_set_memory(s, 0x5b, val);
rtc_set_memory(s, 0x5c, val >> 8);
rtc_set_memory(s, 0x5d, val >> 16);
mc146818rtc_set_cmos_data(s, 0x5b, val);
mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
object_property_add_link(OBJECT(pcms), "rtc_state",
TYPE_ISA_DEVICE,
@ -699,7 +702,7 @@ void pc_cmos_init(PCMachineState *pcms,
val = 0;
val |= 0x02; /* FPU is there */
val |= 0x04; /* PS/2 mouse installed */
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
/* hard drives and FDC */
arg.rtc_state = s;
@ -1296,14 +1299,14 @@ void pc_basic_device_init(struct PCMachineState *pcms,
sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
for (i = 0; i < GSI_NUM_PINS; i++) {
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
}
pit_isa_irq = -1;
pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
}
*rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
*rtc_state = ISA_DEVICE(mc146818_rtc_init(isa_bus, 2000, rtc_irq));
qemu_register_boot_set(pc_boot_set, *rtc_state);

3
hw/i386/pc_piix.c
View file

@ -39,6 +39,7 @@
#include "hw/pci/pci_ids.h"
#include "hw/usb.h"
#include "net/net.h"
#include "hw/ide/isa.h"
#include "hw/ide/pci.h"
#include "hw/ide/piix.h"
#include "hw/irq.h"
@ -246,7 +247,7 @@ static void pc_init1(MachineState *machine,
i8257_dma_init(isa_bus, 0);
pcms->hpet_enabled = false;
}
isa_bus_irqs(isa_bus, x86ms->gsi);
isa_bus_register_input_irqs(isa_bus, x86ms->gsi);
if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
pc_i8259_create(isa_bus, gsi_state->i8259_irq);

34
hw/i386/pc_q35.c
View file

@ -40,13 +40,14 @@
#include "hw/qdev-properties.h"
#include "hw/i386/x86.h"
#include "hw/i386/pc.h"
#include "hw/i386/ich9.h"
#include "hw/i386/amd_iommu.h"
#include "hw/i386/intel_iommu.h"
#include "hw/display/ramfb.h"
#include "hw/firmware/smbios.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
#include "hw/intc/ioapic.h"
#include "hw/southbridge/ich9.h"
#include "hw/usb.h"
#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
@ -132,7 +133,6 @@ static void pc_q35_init(MachineState *machine)
GSIState *gsi_state;
ISABus *isa_bus;
int i;
ICH9LPCState *ich9_lpc;
PCIDevice *ahci;
ram_addr_t lowmem;
DriveInfo *hd[MAX_SATA_PORTS];
@ -236,9 +236,11 @@ static void pc_q35_init(MachineState *machine)
phb = PCI_HOST_BRIDGE(q35_host);
host_bus = phb->bus;
/* create ISA bus */
lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
ICH9_LPC_FUNC), true,
TYPE_ICH9_LPC_DEVICE);
lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true,
TYPE_ICH9_LPC_DEVICE);
qdev_prop_set_bit(DEVICE(lpc), "smm-enabled",
x86_machine_is_smm_enabled(x86ms));
pci_realize_and_unref(lpc, host_bus, &error_fatal);
object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
TYPE_HOTPLUG_HANDLER,
@ -265,15 +267,11 @@ static void pc_q35_init(MachineState *machine)
/* irq lines */
gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
ich9_lpc = ICH9_LPC_DEVICE(lpc);
lpc_dev = DEVICE(lpc);
for (i = 0; i < GSI_NUM_PINS; i++) {
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
}
pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc, ICH9_LPC_NB_PIRQS);
pci_bus_map_irqs(host_bus, ich9_lpc_map_irq);
pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
isa_bus = ich9_lpc->isa_bus;
isa_bus = ISA_BUS(qdev_get_child_bus(lpc_dev, "isa.0"));
if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
pc_i8259_create(isa_bus, gsi_state->i8259_irq);
@ -296,9 +294,6 @@ static void pc_q35_init(MachineState *machine)
pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy,
0xff0104);
/* connect pm stuff to lpc */
ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms));
if (pcms->sata_enabled) {
/* ahci and SATA device, for q35 1 ahci controller is built-in */
ahci = pci_create_simple_multifunction(host_bus,
@ -320,10 +315,15 @@ static void pc_q35_init(MachineState *machine)
}
if (pcms->smbus_enabled) {
PCIDevice *smb;
/* TODO: Populate SPD eeprom data. */
pcms->smbus = ich9_smb_init(host_bus,
PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
0xb100);
smb = pci_create_simple_multifunction(host_bus,
PCI_DEVFN(ICH9_SMB_DEV,
ICH9_SMB_FUNC),
true, TYPE_ICH9_SMB_DEVICE);
pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c"));
smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
}

10
hw/i386/x86.c
View file

@ -64,7 +64,7 @@
/* Physical Address of PVH entry point read from kernel ELF NOTE */
static size_t pvh_start_addr;
inline void init_topo_info(X86CPUTopoInfo *topo_info,
static void init_topo_info(X86CPUTopoInfo *topo_info,
const X86MachineState *x86ms)
{
MachineState *ms = MACHINE(x86ms);
@ -150,17 +150,19 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
}
}
void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
void x86_rtc_set_cpus_count(ISADevice *s, uint16_t cpus_count)
{
MC146818RtcState *rtc = MC146818_RTC(s);
if (cpus_count > 0xff) {
/*
* If the number of CPUs can't be represented in 8 bits, the
* BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
* to make old BIOSes fail more predictably.
*/
rtc_set_memory(rtc, 0x5f, 0);
mc146818rtc_set_cmos_data(rtc, 0x5f, 0);
} else {
rtc_set_memory(rtc, 0x5f, cpus_count - 1);
mc146818rtc_set_cmos_data(rtc, 0x5f, cpus_count - 1);
}
}

1
hw/i386/xen/xen_platform.c
View file

@ -25,7 +25,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/ide.h"
#include "hw/ide/pci.h"
#include "hw/pci/pci.h"
#include "hw/xen/xen_common.h"

13
hw/ide/ahci.c
View file

@ -22,6 +22,7 @@
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/pci/msi.h"
#include "hw/pci/pci.h"
#include "hw/qdev-properties.h"
@ -1085,8 +1086,8 @@ static void execute_ncq_command(NCQTransferState *ncq_tfs)
ncq_cb, ncq_tfs);
break;
case WRITE_FPDMA_QUEUED:
trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag,
ncq_tfs->sector_count, ncq_tfs->lba);
trace_execute_ncq_command_write(ad->hba, port, ncq_tfs->tag,
ncq_tfs->sector_count, ncq_tfs->lba);
dma_acct_start(ide_state->blk, &ncq_tfs->acct,
&ncq_tfs->sglist, BLOCK_ACCT_WRITE);
ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist,
@ -1268,7 +1269,7 @@ static void handle_reg_h2d_fis(AHCIState *s, int port,
cmd->status = 0;
/* We're ready to process the command in FIS byte 2. */
ide_exec_cmd(&s->dev[port].port, cmd_fis[2]);
ide_bus_exec_cmd(&s->dev[port].port, cmd_fis[2]);
}
static int handle_cmd(AHCIState *s, int port, uint8_t slot)
@ -1553,13 +1554,13 @@ void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
AHCIDevice *ad = &s->dev[i];
ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1);
ide_init2(&ad->port, irqs[i]);
ide_bus_init_output_irq(&ad->port, irqs[i]);
ad->hba = s;
ad->port_no = i;
ad->port.dma = &ad->dma;
ad->port.dma->ops = &ahci_dma_ops;
ide_register_restart_cb(&ad->port);
ide_bus_register_restart_cb(&ad->port);
}
g_free(irqs);
}
@ -1841,7 +1842,7 @@ void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd)
if (hd[i] == NULL) {
continue;
}
ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]);
}
}

13
hw/ide/atapi.c
View file

@ -27,6 +27,7 @@
#include "hw/ide/internal.h"
#include "hw/scsi/scsi.h"
#include "sysemu/block-backend.h"
#include "scsi/constants.h"
#include "trace.h"
#define ATAPI_SECTOR_BITS (2 + BDRV_SECTOR_BITS)
@ -178,7 +179,7 @@ void ide_atapi_cmd_ok(IDEState *s)
s->status = READY_STAT | SEEK_STAT;
s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
ide_transfer_stop(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
@ -190,7 +191,7 @@ void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
s->sense_key = sense_key;
s->asc = asc;
ide_transfer_stop(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
void ide_atapi_io_error(IDEState *s, int ret)
@ -253,7 +254,7 @@ void ide_atapi_cmd_reply_end(IDEState *s)
} else {
/* a new transfer is needed */
s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
byte_count_limit = atapi_byte_count_limit(s);
trace_ide_atapi_cmd_reply_end_bcl(s, byte_count_limit);
size = s->packet_transfer_size;
@ -293,7 +294,7 @@ void ide_atapi_cmd_reply_end(IDEState *s)
/* end of transfer */
trace_ide_atapi_cmd_reply_end_eot(s, s->status);
ide_atapi_cmd_ok(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
/* send a reply of 'size' bytes in s->io_buffer to an ATAPI command */
@ -339,7 +340,7 @@ static void ide_atapi_cmd_check_status(IDEState *s)
s->error = MC_ERR | (UNIT_ATTENTION << 4);
s->status = ERR_STAT;
s->nsector = 0;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
/* ATAPI DMA support */
@ -383,7 +384,7 @@ static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret)
if (s->packet_transfer_size <= 0) {
s->status = READY_STAT | SEEK_STAT;
s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
goto eot;
}

4
hw/ide/cmd646.c
View file

@ -294,11 +294,11 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
qdev_init_gpio_in(ds, cmd646_set_irq, 2);
for (i = 0; i < 2; i++) {
ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i));
ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_register_restart_cb(&d->bus[i]);
ide_bus_register_restart_cb(&d->bus[i]);
}
}

80
hw/ide/core.c
View file

@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/isa/isa.h"
#include "migration/vmstate.h"
#include "qemu/error-report.h"
@ -653,7 +654,7 @@ void ide_set_sector(IDEState *s, int64_t sector_num)
static void ide_rw_error(IDEState *s) {
ide_abort_command(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
static void ide_buffered_readv_cb(void *opaque, int ret)
@ -772,7 +773,7 @@ static void ide_sector_read_cb(void *opaque, int ret)
s->nsector -= n;
/* Allow the guest to read the io_buffer */
ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
static void ide_sector_read(IDEState *s)
@ -836,7 +837,7 @@ void ide_dma_error(IDEState *s)
dma_buf_commit(s, 0);
ide_abort_command(s);
ide_set_inactive(s, false);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
int ide_handle_rw_error(IDEState *s, int error, int op)
@ -906,7 +907,7 @@ static void ide_dma_cb(void *opaque, int ret)
/* end of transfer ? */
if (s->nsector == 0) {
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
goto eot;
}
@ -1006,7 +1007,7 @@ static void ide_sector_write(IDEState *s);
static void ide_sector_write_timer_cb(void *opaque)
{
IDEState *s = opaque;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
static void ide_sector_write_cb(void *opaque, int ret)
@ -1054,7 +1055,7 @@ static void ide_sector_write_cb(void *opaque, int ret)
timer_mod(s->sector_write_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(NANOSECONDS_PER_SECOND / 1000));
} else {
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
}
@ -1105,7 +1106,7 @@ static void ide_flush_cb(void *opaque, int ret)
}
s->status = READY_STAT | SEEK_STAT;
ide_cmd_done(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
static void ide_flush_cache(IDEState *s)
@ -1194,7 +1195,7 @@ static void ide_cd_change_cb(void *opaque, bool load, Error **errp)
s->cdrom_changed = 1;
s->events.new_media = true;
s->events.eject_request = false;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
static void ide_cd_eject_request_cb(void *opaque, bool force)
@ -1205,7 +1206,7 @@ static void ide_cd_eject_request_cb(void *opaque, bool force)
if (force) {
s->tray_locked = false;
}
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
static void ide_cmd_lba48_transform(IDEState *s, int lba48)
@ -1264,7 +1265,7 @@ const char *ATA_IOPORT_WR_lookup[ATA_IOPORT_WR_NUM_REGISTERS] = {
void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
int reg_num = addr & 7;
trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, s);
@ -1326,7 +1327,7 @@ void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
case ATA_IOPORT_WR_COMMAND:
ide_clear_hob(bus);
qemu_irq_lower(bus->irq);
ide_exec_cmd(bus, val);
ide_bus_exec_cmd(bus, val);
break;
}
}
@ -1439,7 +1440,7 @@ static bool cmd_identify(IDEState *s, uint8_t cmd)
}
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
} else {
if (s->drive_kind == IDE_CD) {
@ -1629,7 +1630,7 @@ static bool cmd_specify(IDEState *s, uint8_t cmd)
if (s->blk && s->drive_kind != IDE_CD) {
s->heads = (s->select & (ATA_DEV_HS)) + 1;
s->sectors = s->nsector;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
} else {
ide_abort_command(s);
}
@ -1730,7 +1731,7 @@ static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
ide_atapi_identify(s);
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
}
@ -1755,7 +1756,7 @@ static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
* They are part of the regular output (this is why ERR_STAT isn't set)
* Device 0 passed, Device 1 passed or not present. */
s->error = 0x01;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
return false;
@ -1787,7 +1788,7 @@ static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
{
s->error = 0x09; /* miscellaneous error */
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
}
@ -1826,7 +1827,7 @@ static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
s->io_buffer[0x1a] = 0x01; /* Hot count */
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
}
@ -1850,7 +1851,7 @@ static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
s->status = 0x00; /* NOTE: READY is _not_ set */
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
}
@ -1933,7 +1934,7 @@ static bool cmd_smart(IDEState *s, uint8_t cmd)
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
case SMART_READ_DATA:
@ -1974,7 +1975,7 @@ static bool cmd_smart(IDEState *s, uint8_t cmd)
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
case SMART_READ_LOG:
@ -2013,7 +2014,7 @@ static bool cmd_smart(IDEState *s, uint8_t cmd)
}
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
case SMART_EXECUTE_OFFLINE:
@ -2122,13 +2123,13 @@ static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
&& (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
}
void ide_exec_cmd(IDEBus *bus, uint32_t val)
void ide_bus_exec_cmd(IDEBus *bus, uint32_t val)
{
IDEState *s;
bool complete;
s = idebus_active_if(bus);
trace_ide_exec_cmd(bus, s, val);
s = ide_bus_active_if(bus);
trace_ide_bus_exec_cmd(bus, s, val);
/* ignore commands to non existent slave */
if (s != bus->ifs && !s->blk) {
@ -2145,7 +2146,7 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val)
if (!ide_cmd_permitted(s, val)) {
ide_abort_command(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return;
}
@ -2163,7 +2164,7 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val)
}
ide_cmd_done(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
}
@ -2194,7 +2195,7 @@ const char *ATA_IOPORT_RR_lookup[ATA_IOPORT_RR_NUM_REGISTERS] = {
uint32_t ide_ioport_read(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint32_t reg_num;
int ret, hob;
@ -2280,7 +2281,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
uint32_t ide_status_read(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
int ret;
if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
@ -2369,7 +2370,7 @@ static bool ide_is_pio_out(IDEState *s)
void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
trace_ide_data_writew(addr, val, bus, s);
@ -2405,7 +2406,7 @@ void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
uint32_t ide_data_readw(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
int ret;
@ -2443,7 +2444,7 @@ uint32_t ide_data_readw(void *opaque, uint32_t addr)
void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
trace_ide_data_writel(addr, val, bus, s);
@ -2471,7 +2472,7 @@ void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
uint32_t ide_data_readl(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
int ret;
@ -2710,7 +2711,7 @@ static void ide_restart_bh(void *opaque)
return;
}
s = idebus_active_if(bus);
s = ide_bus_active_if(bus);
is_read = (bus->error_status & IDE_RETRY_READ) != 0;
/* The error status must be cleared before resubmitting the request: The
@ -2758,7 +2759,7 @@ static void ide_restart_cb(void *opaque, bool running, RunState state)
}
}
void ide_register_restart_cb(IDEBus *bus)
void ide_bus_register_restart_cb(IDEBus *bus)
{
if (bus->dma->ops->restart_dma) {
bus->vmstate = qemu_add_vm_change_state_handler(ide_restart_cb, bus);
@ -2770,7 +2771,7 @@ static IDEDMA ide_dma_nop = {
.aiocb = NULL,
};
void ide_init2(IDEBus *bus, qemu_irq irq)
void ide_bus_init_output_irq(IDEBus *bus, qemu_irq irq_out)
{
int i;
@ -2778,10 +2779,17 @@ void ide_init2(IDEBus *bus, qemu_irq irq)
ide_init1(bus, i);
ide_reset(&bus->ifs[i]);
}
bus->irq = irq;
bus->irq = irq_out;
bus->dma = &ide_dma_nop;
}
void ide_bus_set_irq(IDEBus *bus)
{
if (!(bus->cmd & IDE_CTRL_DISABLE_IRQ)) {
qemu_irq_raise(bus->irq);
}
}
void ide_exit(IDEState *s)
{
timer_free(s->sector_write_timer);

1
hw/ide/ich.c
View file

@ -61,6 +61,7 @@
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/pci/msi.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"

10
hw/ide/ioport.c
View file

@ -25,16 +25,6 @@
#include "qemu/osdep.h"
#include "hw/isa/isa.h"
#include "qemu/error-report.h"
#include "qemu/timer.h"
#include "sysemu/blockdev.h"
#include "sysemu/dma.h"
#include "hw/block/block.h"
#include "sysemu/block-backend.h"
#include "qapi/error.h"
#include "qemu/cutils.h"
#include "sysemu/replay.h"
#include "hw/ide/internal.h"
#include "trace.h"

22
hw/ide/isa.c
View file

@ -31,23 +31,20 @@
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "hw/ide/isa.h"
#include "hw/ide/internal.h"
#include "qom/object.h"
/***********************************************************/
/* ISA IDE definitions */
#define TYPE_ISA_IDE "isa-ide"
OBJECT_DECLARE_SIMPLE_TYPE(ISAIDEState, ISA_IDE)
struct ISAIDEState {
ISADevice parent_obj;
IDEBus bus;
uint32_t iobase;
uint32_t iobase2;
uint32_t isairq;
qemu_irq irq;
uint32_t irqnum;
};
static void isa_ide_reset(DeviceState *d)
@ -75,13 +72,12 @@ static void isa_ide_realizefn(DeviceState *dev, Error **errp)
ide_bus_init(&s->bus, sizeof(s->bus), dev, 0, 2);
ide_init_ioport(&s->bus, isadev, s->iobase, s->iobase2);
s->irq = isa_get_irq(isadev, s->isairq);
ide_init2(&s->bus, s->irq);
ide_bus_init_output_irq(&s->bus, isa_get_irq(isadev, s->irqnum));
vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_isa, s);
ide_register_restart_cb(&s->bus);
ide_bus_register_restart_cb(&s->bus);
}
ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int isairq,
ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int irqnum,
DriveInfo *hd0, DriveInfo *hd1)
{
DeviceState *dev;
@ -92,15 +88,15 @@ ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int isairq,
dev = DEVICE(isadev);
qdev_prop_set_uint32(dev, "iobase", iobase);
qdev_prop_set_uint32(dev, "iobase2", iobase2);
qdev_prop_set_uint32(dev, "irq", isairq);
qdev_prop_set_uint32(dev, "irq", irqnum);
isa_realize_and_unref(isadev, bus, &error_fatal);
s = ISA_IDE(dev);
if (hd0) {
ide_create_drive(&s->bus, 0, hd0);
ide_bus_create_drive(&s->bus, 0, hd0);
}
if (hd1) {
ide_create_drive(&s->bus, 1, hd1);
ide_bus_create_drive(&s->bus, 1, hd1);
}
return isadev;
}
@ -108,7 +104,7 @@ ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int isairq,
static Property isa_ide_properties[] = {
DEFINE_PROP_UINT32("iobase", ISAIDEState, iobase, 0x1f0),
DEFINE_PROP_UINT32("iobase2", ISAIDEState, iobase2, 0x3f6),
DEFINE_PROP_UINT32("irq", ISAIDEState, isairq, 14),
DEFINE_PROP_UINT32("irq", ISAIDEState, irqnum, 14),
DEFINE_PROP_END_OF_LIST(),
};

15
hw/ide/macio.c
View file

@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/ppc/mac_dbdma.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
@ -59,7 +60,7 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
{
DBDMA_io *io = opaque;
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
IDEState *s = ide_bus_active_if(&m->bus);
int64_t offset;
MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
@ -135,7 +136,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
{
DBDMA_io *io = opaque;
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
IDEState *s = ide_bus_active_if(&m->bus);
int64_t offset;
MACIO_DPRINTF("pmac_ide_transfer_cb\n");
@ -159,7 +160,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
MACIO_DPRINTF("End of IDE transfer\n");
qemu_sglist_destroy(&s->sg);
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
m->dma_active = false;
goto done;
}
@ -219,7 +220,7 @@ done:
static void pmac_ide_transfer(DBDMA_io *io)
{
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
IDEState *s = ide_bus_active_if(&m->bus);
MACIO_DPRINTF("\n");
@ -250,7 +251,7 @@ static void pmac_ide_transfer(DBDMA_io *io)
static void pmac_ide_flush(DBDMA_io *io)
{
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
IDEState *s = ide_bus_active_if(&m->bus);
if (s->bus->dma->aiocb) {
blk_drain(s->blk);
@ -419,7 +420,7 @@ static void macio_ide_realizefn(DeviceState *dev, Error **errp)
{
MACIOIDEState *s = MACIO_IDE(dev);
ide_init2(&s->bus, s->ide_irq);
ide_bus_init_output_irq(&s->bus, s->ide_irq);
/* Register DMA callbacks */
s->dma.ops = &dbdma_ops;
@ -500,7 +501,7 @@ void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
for (i = 0; i < 2; i++) {
if (hd_table[i]) {
ide_create_drive(&s->bus, i, hd_table[i]);
ide_bus_create_drive(&s->bus, i, hd_table[i]);
}
}
}

9
hw/ide/microdrive.c
View file

@ -29,6 +29,7 @@
#include "qapi/error.h"
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "hw/irq.h"
#include "hw/ide/internal.h"
#include "qom/object.h"
@ -249,14 +250,14 @@ static uint16_t md_common_read(PCMCIACardState *card, uint32_t at)
case 0xd: /* Error */
return ide_ioport_read(&s->bus, 0x1);
case 0xe: /* Alternate Status */
ifs = idebus_active_if(&s->bus);
ifs = ide_bus_active_if(&s->bus);
if (ifs->blk) {
return ifs->status;
} else {
return 0;
}
case 0xf: /* Device Address */
ifs = idebus_active_if(&s->bus);
ifs = ide_bus_active_if(&s->bus);
return 0xc2 | ((~ifs->select << 2) & 0x3c);
default:
return ide_ioport_read(&s->bus, at);
@ -565,7 +566,7 @@ PCMCIACardState *dscm1xxxx_init(DriveInfo *dinfo)
qdev_realize(DEVICE(md), NULL, &error_fatal);
if (dinfo != NULL) {
ide_create_drive(&md->bus, 0, dinfo);
ide_bus_create_drive(&md->bus, 0, dinfo);
}
md->bus.ifs[0].drive_kind = IDE_CFATA;
md->bus.ifs[0].mdata_size = METADATA_SIZE;
@ -598,7 +599,7 @@ static void microdrive_realize(DeviceState *dev, Error **errp)
{
MicroDriveState *md = MICRODRIVE(dev);
ide_init2(&md->bus, qemu_allocate_irq(md_set_irq, md, 0));
ide_bus_init_output_irq(&md->bus, qemu_allocate_irq(md_set_irq, md, 0));
}
static void microdrive_init(Object *obj)

37
hw/ide/mmio.c
View file

@ -29,9 +29,9 @@
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "hw/ide/mmio.h"
#include "hw/ide/internal.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
/***********************************************************/
/* MMIO based ide port
@ -39,11 +39,6 @@
* dedicated ide controller, which is often seen on embedded boards.
*/
#define TYPE_MMIO_IDE "mmio-ide"
typedef struct MMIOIDEState MMIOState;
DECLARE_INSTANCE_CHECKER(MMIOState, MMIO_IDE,
TYPE_MMIO_IDE)
struct MMIOIDEState {
/*< private >*/
SysBusDevice parent_obj;
@ -58,7 +53,7 @@ struct MMIOIDEState {
static void mmio_ide_reset(DeviceState *dev)
{
MMIOState *s = MMIO_IDE(dev);
MMIOIDEState *s = MMIO_IDE(dev);
ide_bus_reset(&s->bus);
}
@ -66,7 +61,7 @@ static void mmio_ide_reset(DeviceState *dev)
static uint64_t mmio_ide_read(void *opaque, hwaddr addr,
unsigned size)
{
MMIOState *s = opaque;
MMIOIDEState *s = opaque;
addr >>= s->shift;
if (addr & 7)
return ide_ioport_read(&s->bus, addr);
@ -77,7 +72,7 @@ static uint64_t mmio_ide_read(void *opaque, hwaddr addr,
static void mmio_ide_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
MMIOIDEState *s = opaque;
addr >>= s->shift;
if (addr & 7)
ide_ioport_write(&s->bus, addr, val);
@ -94,14 +89,14 @@ static const MemoryRegionOps mmio_ide_ops = {
static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr,
unsigned size)
{
MMIOState *s= opaque;
MMIOIDEState *s = opaque;
return ide_status_read(&s->bus, 0);
}
static void mmio_ide_ctrl_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
MMIOIDEState *s = opaque;
ide_ctrl_write(&s->bus, 0, val);
}
@ -116,8 +111,8 @@ static const VMStateDescription vmstate_ide_mmio = {
.version_id = 3,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_IDE_BUS(bus, MMIOState),
VMSTATE_IDE_DRIVES(bus.ifs, MMIOState),
VMSTATE_IDE_BUS(bus, MMIOIDEState),
VMSTATE_IDE_DRIVES(bus.ifs, MMIOIDEState),
VMSTATE_END_OF_LIST()
}
};
@ -125,9 +120,9 @@ static const VMStateDescription vmstate_ide_mmio = {
static void mmio_ide_realizefn(DeviceState *dev, Error **errp)
{
SysBusDevice *d = SYS_BUS_DEVICE(dev);
MMIOState *s = MMIO_IDE(dev);
MMIOIDEState *s = MMIO_IDE(dev);
ide_init2(&s->bus, s->irq);
ide_bus_init_output_irq(&s->bus, s->irq);
memory_region_init_io(&s->iomem1, OBJECT(s), &mmio_ide_ops, s,
"ide-mmio.1", 16 << s->shift);
@ -140,14 +135,14 @@ static void mmio_ide_realizefn(DeviceState *dev, Error **errp)
static void mmio_ide_initfn(Object *obj)
{
SysBusDevice *d = SYS_BUS_DEVICE(obj);
MMIOState *s = MMIO_IDE(obj);
MMIOIDEState *s = MMIO_IDE(obj);
ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
sysbus_init_irq(d, &s->irq);
}
static Property mmio_ide_properties[] = {
DEFINE_PROP_UINT32("shift", MMIOState, shift, 0),
DEFINE_PROP_UINT32("shift", MMIOIDEState, shift, 0),
DEFINE_PROP_END_OF_LIST()
};
@ -164,7 +159,7 @@ static void mmio_ide_class_init(ObjectClass *oc, void *data)
static const TypeInfo mmio_ide_type_info = {
.name = TYPE_MMIO_IDE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MMIOState),
.instance_size = sizeof(MMIOIDEState),
.instance_init = mmio_ide_initfn,
.class_init = mmio_ide_class_init,
};
@ -176,13 +171,13 @@ static void mmio_ide_register_types(void)
void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1)
{
MMIOState *s = MMIO_IDE(dev);
MMIOIDEState *s = MMIO_IDE(dev);
if (hd0 != NULL) {
ide_create_drive(&s->bus, 0, hd0);
ide_bus_create_drive(&s->bus, 0, hd0);
}
if (hd1 != NULL) {
ide_create_drive(&s->bus, 1, hd1);
ide_bus_create_drive(&s->bus, 1, hd1);
}
}

11
hw/ide/pci.c
View file

@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"
#include "sysemu/dma.h"
@ -103,6 +104,12 @@ const MemoryRegionOps pci_ide_data_le_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static IDEState *bmdma_active_if(BMDMAState *bmdma)
{
assert(bmdma->bus->retry_unit != (uint8_t)-1);
return bmdma->bus->ifs + bmdma->bus->retry_unit;
}
static void bmdma_start_dma(const IDEDMA *dma, IDEState *s,
BlockCompletionFunc *dma_cb)
{
@ -295,7 +302,7 @@ void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
/* Ignore writes to SSBM if it keeps the old value */
if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
if (!(val & BM_CMD_START)) {
ide_cancel_dma_sync(idebus_active_if(bm->bus));
ide_cancel_dma_sync(ide_bus_active_if(bm->bus));
bm->status &= ~BM_STATUS_DMAING;
} else {
bm->cur_addr = bm->addr;
@ -488,7 +495,7 @@ void pci_ide_create_devs(PCIDevice *dev)
ide_drive_get(hd_table, ARRAY_SIZE(hd_table));
for (i = 0; i < 4; i++) {
if (hd_table[i]) {
ide_create_drive(d->bus + bus[i], unit[i], hd_table[i]);
ide_bus_create_drive(d->bus + bus[i], unit[i], hd_table[i]);
}
}
}

46
hw/ide/piix.c
View file

@ -28,14 +28,9 @@
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "sysemu/dma.h"
#include "hw/pci/pci.h"
#include "hw/ide/piix.h"
#include "hw/ide/pci.h"
#include "trace.h"
@ -126,7 +121,7 @@ static void piix_ide_reset(DeviceState *dev)
pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */
}
static int pci_piix_init_ports(PCIIDEState *d)
static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp)
{
static const struct {
int iobase;
@ -136,30 +131,29 @@ static int pci_piix_init_ports(PCIIDEState *d)
{0x1f0, 0x3f6, 14},
{0x170, 0x376, 15},
};
int i, ret;
int ret;
for (i = 0; i < 2; i++) {
ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
port_info[i].iobase2);
if (ret) {
return ret;
}
ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_register_restart_cb(&d->bus[i]);
ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
port_info[i].iobase2);
if (ret) {
error_setg_errno(errp, -ret, "Failed to realize %s port %u",
object_get_typename(OBJECT(d)), i);
return false;
}
ide_bus_init_output_irq(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
return 0;
bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_bus_register_restart_cb(&d->bus[i]);
return true;
}
static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
{
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
int rc;
pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
@ -168,10 +162,10 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d);
rc = pci_piix_init_ports(d);
if (rc) {
error_setg_errno(errp, -rc, "Failed to realize %s",
object_get_typename(OBJECT(dev)));
for (unsigned i = 0; i < 2; i++) {
if (!pci_piix_init_bus(d, i, errp)) {
return;
}
}
}

2
hw/ide/qdev.c
View file

@ -124,7 +124,7 @@ static void ide_qdev_realize(DeviceState *qdev, Error **errp)
dc->realize(dev, errp);
}
IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive)
IDEDevice *ide_bus_create_drive(IDEBus *bus, int unit, DriveInfo *drive)
{
DeviceState *dev;

4
hw/ide/sii3112.c
View file

@ -284,11 +284,11 @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
qdev_init_gpio_in(ds, sii3112_set_irq, 2);
for (i = 0; i < 2; i++) {
ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1);
ide_init2(&s->bus[i], qdev_get_gpio_in(ds, i));
ide_bus_init_output_irq(&s->bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(&s->bus[i], &s->bmdma[i], s);
s->bmdma[i].bus = &s->bus[i];
ide_register_restart_cb(&s->bus[i]);
ide_bus_register_restart_cb(&s->bus[i]);
}
}

3
hw/ide/trace-events
View file

@ -12,7 +12,7 @@ ide_data_writew(uint32_t addr, uint32_t val, void *bus, void *s)
ide_data_readl(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO rd @ 0x%"PRIx32" (Data: Long); val 0x%08"PRIx32"; bus %p; IDEState %p"
ide_data_writel(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO wr @ 0x%"PRIx32" (Data: Long); val 0x%08"PRIx32"; bus %p; IDEState %p"
# misc
ide_exec_cmd(void *bus, void *state, uint32_t cmd) "IDE exec cmd: bus %p; state %p; cmd 0x%02x"
ide_bus_exec_cmd(void *bus, void *state, uint32_t cmd) "IDE exec cmd: bus %p; state %p; cmd 0x%02x"
ide_cancel_dma_sync_buffered(void *fn, void *req) "invoking cb %p of buffered request %p with -ECANCELED"
ide_cancel_dma_sync_remaining(void) "draining all remaining requests"
ide_sector_read(int64_t sector_num, int nsectors) "sector=%"PRId64" nsectors=%d"
@ -91,6 +91,7 @@ ahci_populate_sglist_short_map(void *s, int port) "ahci(%p)[%d]: mapped less tha
ahci_populate_sglist_bad_offset(void *s, int port, int off_idx, int64_t off_pos) "ahci(%p)[%d]: Incorrect offset! off_idx: %d, off_pos: %"PRId64
ncq_finish(void *s, int port, uint8_t tag) "ahci(%p)[%d][tag:%d]: NCQ transfer finished"
execute_ncq_command_read(void *s, int port, uint8_t tag, int count, int64_t lba) "ahci(%p)[%d][tag:%d]: NCQ reading %d sectors from LBA %"PRId64
execute_ncq_command_write(void *s, int port, uint8_t tag, int count, int64_t lba) "ahci(%p)[%d][tag:%d]: NCQ writing %d sectors to LBA %"PRId64
execute_ncq_command_unsup(void *s, int port, uint8_t tag, uint8_t cmd) "ahci(%p)[%d][tag:%d]: error: unsupported NCQ command (0x%02x) received"
process_ncq_command_mismatch(void *s, int port, uint8_t tag, uint8_t slot) "ahci(%p)[%d][tag:%d]: Warning: NCQ slot (%d) did not match the given tag"
process_ncq_command_aux(void *s, int port, uint8_t tag) "ahci(%p)[%d][tag:%d]: Warn: Attempt to use NCQ auxiliary fields"

16
hw/ide/via.c
View file

@ -90,7 +90,7 @@ static void bmdma_setup_bar(PCIIDEState *d)
int i;
memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16);
for(i = 0;i < 2; i++) {
for (i = 0; i < ARRAY_SIZE(d->bmdma); i++) {
BMDMAState *bm = &d->bmdma[i];
memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm,
@ -122,7 +122,7 @@ static void via_ide_reset(DeviceState *dev)
uint8_t *pci_conf = pd->config;
int i;
for (i = 0; i < 2; i++) {
for (i = 0; i < ARRAY_SIZE(d->bus); i++) {
ide_bus_reset(&d->bus[i]);
}
@ -188,14 +188,14 @@ static void via_ide_realize(PCIDevice *dev, Error **errp)
bmdma_setup_bar(d);
pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
qdev_init_gpio_in(ds, via_ide_set_irq, 2);
for (i = 0; i < 2; i++) {
ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i));
qdev_init_gpio_in(ds, via_ide_set_irq, ARRAY_SIZE(d->bus));
for (i = 0; i < ARRAY_SIZE(d->bus); i++) {
ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, MAX_IDE_DEVS);
ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_register_restart_cb(&d->bus[i]);
ide_bus_register_restart_cb(&d->bus[i]);
}
}
@ -204,7 +204,7 @@ static void via_ide_exitfn(PCIDevice *dev)
PCIIDEState *d = PCI_IDE(dev);
unsigned i;
for (i = 0; i < 2; ++i) {
for (i = 0; i < ARRAY_SIZE(d->bmdma); ++i) {
memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
}

2
hw/intc/apic.c
View file

@ -20,7 +20,7 @@
#include "qemu/thread.h"
#include "hw/i386/apic_internal.h"
#include "hw/i386/apic.h"
#include "hw/i386/ioapic.h"
#include "hw/intc/ioapic.h"
#include "hw/intc/i8259.h"
#include "hw/intc/kvm_irqcount.h"
#include "hw/pci/msi.h"

4
hw/intc/i8259.c
View file

@ -406,7 +406,7 @@ static void pic_realize(DeviceState *dev, Error **errp)
pc->parent_realize(dev, errp);
}
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_in)
{
qemu_irq *irq_set;
DeviceState *dev;
@ -418,7 +418,7 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
isadev = i8259_init_chip(TYPE_I8259, bus, true);
dev = DEVICE(isadev);
qdev_connect_gpio_out(dev, 0, parent_irq);
qdev_connect_gpio_out(dev, 0, parent_irq_in);
for (i = 0 ; i < 8; i++) {
irq_set[i] = qdev_get_gpio_in(dev, i);
}

4
hw/intc/ioapic.c
View file

@ -24,10 +24,10 @@
#include "qapi/error.h"
#include "monitor/monitor.h"
#include "hw/i386/apic.h"
#include "hw/i386/ioapic.h"
#include "hw/i386/ioapic_internal.h"
#include "hw/i386/x86.h"
#include "hw/intc/i8259.h"
#include "hw/intc/ioapic.h"
#include "hw/intc/ioapic_internal.h"
#include "hw/pci/msi.h"
#include "hw/qdev-properties.h"
#include "sysemu/kvm.h"

4
hw/intc/ioapic_common.c
View file

@ -24,9 +24,9 @@
#include "qemu/module.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "hw/i386/ioapic.h"
#include "hw/i386/ioapic_internal.h"
#include "hw/intc/intc.h"
#include "hw/intc/ioapic.h"
#include "hw/intc/ioapic_internal.h"
#include "hw/sysbus.h"
/* ioapic_no count start from 0 to MAX_IOAPICS,

8
include/hw/i386/ioapic_internal.h → hw/intc/ioapic_internal.h
View file

@ -19,11 +19,11 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef QEMU_IOAPIC_INTERNAL_H
#define QEMU_IOAPIC_INTERNAL_H
#ifndef HW_INTC_IOAPIC_INTERNAL_H
#define HW_INTC_IOAPIC_INTERNAL_H
#include "exec/memory.h"
#include "hw/i386/ioapic.h"
#include "hw/intc/ioapic.h"
#include "hw/sysbus.h"
#include "qemu/notify.h"
#include "qom/object.h"
@ -115,4 +115,4 @@ void ioapic_reset_common(DeviceState *dev);
void ioapic_stat_update_irq(IOAPICCommonState *s, int irq, int level);
#endif /* QEMU_IOAPIC_INTERNAL_H */
#endif /* HW_INTC_IOAPIC_INTERNAL_H */

19
hw/isa/i82378.c
View file

@ -32,8 +32,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(I82378State, I82378)
struct I82378State {
PCIDevice parent_obj;
qemu_irq out[2];
qemu_irq *i8259;
qemu_irq cpu_intr;
qemu_irq *isa_irqs_in;
MemoryRegion io;
};
@ -47,18 +47,12 @@ static const VMStateDescription vmstate_i82378 = {
},
};
static void i82378_request_out0_irq(void *opaque, int irq, int level)
{
I82378State *s = opaque;
qemu_set_irq(s->out[0], level);
}
static void i82378_request_pic_irq(void *opaque, int irq, int level)
{
DeviceState *dev = opaque;
I82378State *s = I82378(dev);
qemu_set_irq(s->i8259[irq], level);
qemu_set_irq(s->isa_irqs_in[irq], level);
}
static void i82378_realize(PCIDevice *pci, Error **errp)
@ -94,9 +88,8 @@ static void i82378_realize(PCIDevice *pci, Error **errp)
*/
/* 2 82C59 (irq) */
s->i8259 = i8259_init(isabus,
qemu_allocate_irq(i82378_request_out0_irq, s, 0));
isa_bus_irqs(isabus, s->i8259);
s->isa_irqs_in = i8259_init(isabus, s->cpu_intr);
isa_bus_register_input_irqs(isabus, s->isa_irqs_in);
/* 1 82C54 (pit) */
pit = i8254_pit_init(isabus, 0x40, 0, NULL);
@ -113,7 +106,7 @@ static void i82378_init(Object *obj)
DeviceState *dev = DEVICE(obj);
I82378State *s = I82378(obj);
qdev_init_gpio_out(dev, s->out, 1);
qdev_init_gpio_out(dev, &s->cpu_intr, 1);
qdev_init_gpio_in(dev, i82378_request_pic_irq, 16);
}

32
hw/isa/isa-bus.c
View file

@ -67,13 +67,20 @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space,
return isabus;
}
void isa_bus_irqs(ISABus *bus, qemu_irq *irqs)
void isa_bus_register_input_irqs(ISABus *bus, qemu_irq *irqs_in)
{
bus->irqs = irqs;
bus->irqs_in = irqs_in;
}
qemu_irq isa_bus_get_irq(ISABus *bus, unsigned irqnum)
{
assert(irqnum < ISA_NUM_IRQS);
assert(bus->irqs_in);
return bus->irqs_in[irqnum];
}
/*
* isa_get_irq() returns the corresponding qemu_irq entry for the i8259.
* isa_get_irq() returns the corresponding input qemu_irq entry for the i8259.
*
* This function is only for special cases such as the 'ferr', and
* temporary use for normal devices until they are converted to qdev.
@ -81,14 +88,13 @@ void isa_bus_irqs(ISABus *bus, qemu_irq *irqs)
qemu_irq isa_get_irq(ISADevice *dev, unsigned isairq)
{
assert(!dev || ISA_BUS(qdev_get_parent_bus(DEVICE(dev))) == isabus);
assert(isairq < ISA_NUM_IRQS);
return isabus->irqs[isairq];
return isa_bus_get_irq(isabus, isairq);
}
void isa_connect_gpio_out(ISADevice *isadev, int gpioirq, unsigned isairq)
{
qemu_irq irq = isa_get_irq(isadev, isairq);
qdev_connect_gpio_out(DEVICE(isadev), gpioirq, irq);
qemu_irq input_irq = isa_get_irq(isadev, isairq);
qdev_connect_gpio_out(DEVICE(isadev), gpioirq, input_irq);
}
void isa_bus_dma(ISABus *bus, IsaDma *dma8, IsaDma *dma16)
@ -99,7 +105,7 @@ void isa_bus_dma(ISABus *bus, IsaDma *dma8, IsaDma *dma16)
bus->dma[1] = dma16;
}
IsaDma *isa_get_dma(ISABus *bus, int nchan)
IsaDma *isa_bus_get_dma(ISABus *bus, int nchan)
{
assert(bus);
return bus->dma[nchan > 3 ? 1 : 0];
@ -114,7 +120,7 @@ static inline void isa_init_ioport(ISADevice *dev, uint16_t ioport)
void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start)
{
memory_region_add_subregion(isabus->address_space_io, start, io);
memory_region_add_subregion(isa_address_space_io(dev), start, io);
isa_init_ioport(dev, start);
}
@ -135,7 +141,7 @@ int isa_register_portio_list(ISADevice *dev,
isa_init_ioport(dev, start);
portio_list_init(piolist, OBJECT(dev), pio_start, opaque, name);
portio_list_add(piolist, isabus->address_space_io, start);
portio_list_add(piolist, isa_address_space_io(dev), start);
return 0;
}
@ -164,6 +170,11 @@ bool isa_realize_and_unref(ISADevice *dev, ISABus *bus, Error **errp)
return qdev_realize_and_unref(&dev->parent_obj, &bus->parent_obj, errp);
}
ISABus *isa_bus_from_device(ISADevice *dev)
{
return ISA_BUS(qdev_get_parent_bus(DEVICE(dev)));
}
ISADevice *isa_vga_init(ISABus *bus)
{
vga_interface_created = true;
@ -213,7 +224,6 @@ static const TypeInfo isa_device_type_info = {
.parent = TYPE_DEVICE,
.instance_size = sizeof(ISADevice),
.abstract = true,
.class_size = sizeof(ISADeviceClass),
.class_init = isa_device_class_init,
};

36
hw/isa/lpc_ich9.c
View file

@ -40,8 +40,8 @@
#include "hw/irq.h"
#include "hw/isa/apm.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
#include "hw/i386/ich9.h"
#include "hw/southbridge/ich9.h"
#include "hw/i386/pc.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9.h"
#include "hw/pci/pci_bus.h"
@ -57,8 +57,6 @@
/*****************************************************************************/
/* ICH9 LPC PCI to ISA bridge */
static void ich9_lpc_reset(DeviceState *qdev);
/* chipset configuration register
* to access chipset configuration registers, pci_[sg]et_{byte, word, long}
* are used.
@ -259,7 +257,7 @@ static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
qemu_set_irq(lpc->gsi[gsi], level);
}
void ich9_lpc_set_irq(void *opaque, int pirq, int level)
static void ich9_lpc_set_irq(void *opaque, int pirq, int level)
{
ICH9LPCState *lpc = opaque;
int pic_irq, pic_dis;
@ -275,7 +273,7 @@ void ich9_lpc_set_irq(void *opaque, int pirq, int level)
/* return the pirq number (PIRQ[A-H]:0-7) corresponding to
* a given device irq pin.
*/
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
{
BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
PCIBus *pci_bus = PCI_BUS(bus);
@ -286,7 +284,7 @@ int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
}
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
static PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
{
ICH9LPCState *lpc = opaque;
PCIINTxRoute route;
@ -407,14 +405,13 @@ static void smi_features_ok_callback(void *opaque)
lpc->smi_features_ok = 1;
}
void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
static void ich9_lpc_pm_init(ICH9LPCState *lpc)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
qemu_irq sci_irq;
FWCfgState *fw_cfg = fw_cfg_find();
sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq);
ich9_pm_init(PCI_DEVICE(lpc), &lpc->pm, sci_irq);
if (lpc->smi_host_features && fw_cfg) {
uint64_t host_features_le;
@ -440,8 +437,6 @@ void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
sizeof lpc->smi_features_ok,
true);
}
ich9_lpc_reset(DEVICE(lpc));
}
/* APM */
@ -680,6 +675,7 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
DeviceState *dev = DEVICE(d);
PCIBus *pci_bus = pci_get_bus(d);
ISABus *isa_bus;
if ((lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) &&
@ -709,8 +705,6 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc,
"lpc-rcrb-mmio", ICH9_CC_SIZE);
lpc->isa_bus = isa_bus;
ich9_cc_init(lpc);
apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc);
@ -723,11 +717,17 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
1);
qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, IOAPIC_NUM_PINS);
isa_bus_irqs(isa_bus, lpc->gsi);
isa_bus_register_input_irqs(isa_bus, lpc->gsi);
i8257_dma_init(isa_bus, 0);
pci_bus_irqs(pci_bus, ich9_lpc_set_irq, d, ICH9_LPC_NB_PIRQS);
pci_bus_map_irqs(pci_bus, ich9_lpc_map_irq);
pci_bus_set_route_irq_fn(pci_bus, ich9_route_intx_pin_to_irq);
ich9_lpc_pm_init(lpc);
}
static bool ich9_rst_cnt_needed(void *opaque)
@ -794,6 +794,7 @@ static const VMStateDescription vmstate_ich9_lpc = {
static Property ich9_lpc_properties[] = {
DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, false),
DEFINE_PROP_BOOL("smm-compat", ICH9LPCState, pm.smm_compat, false),
DEFINE_PROP_BOOL("smm-enabled", ICH9LPCState, pm.smm_enabled, false),
DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features,
ICH9_LPC_SMI_F_BROADCAST_BIT, true),
DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features,
@ -813,8 +814,7 @@ static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
{
Aml *field;
ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
BusState *bus = BUS(s->isa_bus);
BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");
Aml *sb_scope = aml_scope("\\_SB");
/* ICH9 PCI to ISA irq remapping */

4
hw/isa/piix4.c
View file

@ -47,7 +47,7 @@ struct PIIX4State {
qemu_irq cpu_intr;
qemu_irq *isa;
RTCState rtc;
MC146818RtcState rtc;
PCIIDEState ide;
UHCIState uhci;
PIIX4PMState pm;
@ -212,7 +212,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
s->isa = i8259_init(isa_bus, *i8259_out_irq);
/* initialize ISA irqs */
isa_bus_irqs(isa_bus, s->isa);
isa_bus_register_input_irqs(isa_bus, s->isa);
/* initialize pit */
i8254_pit_init(isa_bus, 0x40, 0, NULL);

18
hw/isa/vt82c686.c
View file

@ -548,9 +548,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(ViaISAState, VIA_ISA)
struct ViaISAState {
PCIDevice dev;
qemu_irq cpu_intr;
qemu_irq *isa_irqs;
qemu_irq *isa_irqs_in;
ViaSuperIOState via_sio;
RTCState rtc;
MC146818RtcState rtc;
PCIIDEState ide;
UHCIState uhci[2];
ViaPMState pm;
@ -595,13 +595,7 @@ static const TypeInfo via_isa_info = {
void via_isa_set_irq(PCIDevice *d, int n, int level)
{
ViaISAState *s = VIA_ISA(d);
qemu_set_irq(s->isa_irqs[n], level);
}
static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
{
ViaISAState *s = opaque;
qemu_set_irq(s->cpu_intr, level);
qemu_set_irq(s->isa_irqs_in[n], level);
}
static void via_isa_realize(PCIDevice *d, Error **errp)
@ -609,12 +603,10 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
ViaISAState *s = VIA_ISA(d);
DeviceState *dev = DEVICE(d);
PCIBus *pci_bus = pci_get_bus(d);
qemu_irq *isa_irq;
ISABus *isa_bus;
int i;
qdev_init_gpio_out(dev, &s->cpu_intr, 1);
isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1);
isa_bus = isa_bus_new(dev, pci_address_space(d), pci_address_space_io(d),
errp);
@ -622,8 +614,8 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
return;
}
s->isa_irqs = i8259_init(isa_bus, *isa_irq);
isa_bus_irqs(isa_bus, s->isa_irqs);
s->isa_irqs_in = i8259_init(isa_bus, s->cpu_intr);
isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in);
i8254_pit_init(isa_bus, 0x40, 0, NULL);
i8257_dma_init(isa_bus, 0);

2
hw/mips/jazz.c
View file

@ -249,7 +249,7 @@ static void mips_jazz_init(MachineState *machine,
/* ISA devices */
i8259 = i8259_init(isa_bus, env->irq[4]);
isa_bus_irqs(isa_bus, i8259);
isa_bus_register_input_irqs(isa_bus, i8259);
i8257_dma_init(isa_bus, 0);
pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
pcspk_init(isa_new(TYPE_PC_SPEAKER), isa_bus, pit);

1
hw/misc/macio/gpio.c
View file

@ -28,6 +28,7 @@
#include "migration/vmstate.h"
#include "hw/misc/macio/macio.h"
#include "hw/misc/macio/gpio.h"
#include "hw/irq.h"
#include "hw/nmi.h"
#include "qemu/log.h"
#include "qemu/module.h"

1
hw/nubus/nubus-device.c
View file

@ -80,6 +80,7 @@ static void nubus_device_realize(DeviceState *dev, Error **errp)
&error_abort);
ret = load_image_mr(path, &nd->decl_rom);
g_free(path);
g_free(name);
if (ret < 0) {
error_setg(errp, "could not load romfile \"%s\"", nd->romfile);
return;

2
hw/pci-bridge/i82801b11.c
View file

@ -45,7 +45,7 @@
#include "hw/pci/pci_bridge.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "hw/i386/ich9.h"
#include "hw/southbridge/ich9.h"
/*****************************************************************************/
/* ICH9 DMI-to-PCI bridge */

2
hw/pci/pci.c
View file

@ -1648,7 +1648,7 @@ void pci_device_set_intx_routing_notifier(PCIDevice *dev,
* 9.1: Interrupt routing. Table 9-1
*
* the PCI Express Base Specification, Revision 2.1
* 2.2.8.1: INTx interrutp signaling - Rules
* 2.2.8.1: INTx interrupt signaling - Rules
* the Implementation Note
* Table 2-20
*/

2
hw/ppc/pnv_lpc.c
View file

@ -837,7 +837,7 @@ ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)
irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS);
isa_bus_irqs(isa_bus, irqs);
isa_bus_register_input_irqs(isa_bus, irqs);
return isa_bus;
}

11
hw/ppc/prep.c
View file

@ -212,14 +212,13 @@ static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
{
uint16_t checksum = *(uint16_t *)opaque;
ISADevice *rtc;
if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
rtc = ISA_DEVICE(dev);
rtc_set_memory(rtc, 0x2e, checksum & 0xff);
rtc_set_memory(rtc, 0x3e, checksum & 0xff);
rtc_set_memory(rtc, 0x2f, checksum >> 8);
rtc_set_memory(rtc, 0x3f, checksum >> 8);
MC146818RtcState *rtc = MC146818_RTC(dev);
mc146818rtc_set_cmos_data(rtc, 0x2e, checksum & 0xff);
mc146818rtc_set_cmos_data(rtc, 0x3e, checksum & 0xff);
mc146818rtc_set_cmos_data(rtc, 0x2f, checksum >> 8);
mc146818rtc_set_cmos_data(rtc, 0x3f, checksum >> 8);
object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
"date");

4
hw/ppc/sam460ex.c
View file

@ -389,8 +389,8 @@ static void sam460ex_init(MachineState *machine)
/* MAL */
dev = qdev_new(TYPE_PPC4xx_MAL);
qdev_prop_set_uint32(dev, "txc-num", 4);
qdev_prop_set_uint32(dev, "rxc-num", 16);
qdev_prop_set_uint8(dev, "txc-num", 4);
qdev_prop_set_uint8(dev, "rxc-num", 16);
ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
object_unref(OBJECT(dev));
sbdev = SYS_BUS_DEVICE(dev);

2
hw/rtc/m48t59-isa.c
View file

@ -47,7 +47,7 @@ struct M48txxISAState {
};
struct M48txxISADeviceClass {
ISADeviceClass parent_class;
DeviceClass parent_class;
M48txxInfo info;
};

128
hw/rtc/mc146818rtc.c
View file

@ -71,19 +71,19 @@
#define RTC_ISA_BASE 0x70
static void rtc_set_time(RTCState *s);
static void rtc_update_time(RTCState *s);
static void rtc_set_cmos(RTCState *s, const struct tm *tm);
static inline int rtc_from_bcd(RTCState *s, int a);
static uint64_t get_next_alarm(RTCState *s);
static void rtc_set_time(MC146818RtcState *s);
static void rtc_update_time(MC146818RtcState *s);
static void rtc_set_cmos(MC146818RtcState *s, const struct tm *tm);
static inline int rtc_from_bcd(MC146818RtcState *s, int a);
static uint64_t get_next_alarm(MC146818RtcState *s);
static inline bool rtc_running(RTCState *s)
static inline bool rtc_running(MC146818RtcState *s)
{
return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
(s->cmos_data[RTC_REG_A] & 0x70) <= 0x20);
}
static uint64_t get_guest_rtc_ns(RTCState *s)
static uint64_t get_guest_rtc_ns(MC146818RtcState *s)
{
uint64_t guest_clock = qemu_clock_get_ns(rtc_clock);
@ -91,7 +91,7 @@ static uint64_t get_guest_rtc_ns(RTCState *s)
guest_clock - s->last_update + s->offset;
}
static void rtc_coalesced_timer_update(RTCState *s)
static void rtc_coalesced_timer_update(MC146818RtcState *s)
{
if (s->irq_coalesced == 0) {
timer_del(s->coalesced_timer);
@ -104,19 +104,19 @@ static void rtc_coalesced_timer_update(RTCState *s)
}
}
static QLIST_HEAD(, RTCState) rtc_devices =
static QLIST_HEAD(, MC146818RtcState) rtc_devices =
QLIST_HEAD_INITIALIZER(rtc_devices);
void qmp_rtc_reset_reinjection(Error **errp)
{
RTCState *s;
MC146818RtcState *s;
QLIST_FOREACH(s, &rtc_devices, link) {
s->irq_coalesced = 0;
}
}
static bool rtc_policy_slew_deliver_irq(RTCState *s)
static bool rtc_policy_slew_deliver_irq(MC146818RtcState *s)
{
kvm_reset_irq_delivered();
qemu_irq_raise(s->irq);
@ -125,7 +125,7 @@ static bool rtc_policy_slew_deliver_irq(RTCState *s)
static void rtc_coalesced_timer(void *opaque)
{
RTCState *s = opaque;
MC146818RtcState *s = opaque;
if (s->irq_coalesced != 0) {
s->cmos_data[RTC_REG_C] |= 0xc0;
@ -140,7 +140,7 @@ static void rtc_coalesced_timer(void *opaque)
rtc_coalesced_timer_update(s);
}
static uint32_t rtc_periodic_clock_ticks(RTCState *s)
static uint32_t rtc_periodic_clock_ticks(MC146818RtcState *s)
{
int period_code;
@ -157,8 +157,8 @@ static uint32_t rtc_periodic_clock_ticks(RTCState *s)
* handle periodic timer. @old_period indicates the periodic timer update
* is just due to period adjustment.
*/
static void
periodic_timer_update(RTCState *s, int64_t current_time, uint32_t old_period, bool period_change)
static void periodic_timer_update(MC146818RtcState *s, int64_t current_time,
uint32_t old_period, bool period_change)
{
uint32_t period;
int64_t cur_clock, next_irq_clock, lost_clock = 0;
@ -234,7 +234,7 @@ periodic_timer_update(RTCState *s, int64_t current_time, uint32_t old_period, bo
static void rtc_periodic_timer(void *opaque)
{
RTCState *s = opaque;
MC146818RtcState *s = opaque;
periodic_timer_update(s, s->next_periodic_time, s->period, false);
s->cmos_data[RTC_REG_C] |= REG_C_PF;
@ -255,7 +255,7 @@ static void rtc_periodic_timer(void *opaque)
}
/* handle update-ended timer */
static void check_update_timer(RTCState *s)
static void check_update_timer(MC146818RtcState *s)
{
uint64_t next_update_time;
uint64_t guest_nsec;
@ -306,7 +306,7 @@ static void check_update_timer(RTCState *s)
}
}
static inline uint8_t convert_hour(RTCState *s, uint8_t hour)
static inline uint8_t convert_hour(MC146818RtcState *s, uint8_t hour)
{
if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
hour %= 12;
@ -317,7 +317,7 @@ static inline uint8_t convert_hour(RTCState *s, uint8_t hour)
return hour;
}
static uint64_t get_next_alarm(RTCState *s)
static uint64_t get_next_alarm(MC146818RtcState *s)
{
int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec;
int32_t hour, min, sec;
@ -410,7 +410,7 @@ static uint64_t get_next_alarm(RTCState *s)
static void rtc_update_timer(void *opaque)
{
RTCState *s = opaque;
MC146818RtcState *s = opaque;
int32_t irqs = REG_C_UF;
int32_t new_irqs;
@ -439,7 +439,7 @@ static void rtc_update_timer(void *opaque)
static void cmos_ioport_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
RTCState *s = opaque;
MC146818RtcState *s = opaque;
uint32_t old_period;
bool update_periodic_timer;
@ -557,7 +557,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr,
}
}
static inline int rtc_to_bcd(RTCState *s, int a)
static inline int rtc_to_bcd(MC146818RtcState *s, int a)
{
if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
return a;
@ -566,7 +566,7 @@ static inline int rtc_to_bcd(RTCState *s, int a)
}
}
static inline int rtc_from_bcd(RTCState *s, int a)
static inline int rtc_from_bcd(MC146818RtcState *s, int a)
{
if ((a & 0xc0) == 0xc0) {
return -1;
@ -578,7 +578,7 @@ static inline int rtc_from_bcd(RTCState *s, int a)
}
}
static void rtc_get_time(RTCState *s, struct tm *tm)
static void rtc_get_time(MC146818RtcState *s, struct tm *tm)
{
tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
@ -597,7 +597,7 @@ static void rtc_get_time(RTCState *s, struct tm *tm)
rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900;
}
static void rtc_set_time(RTCState *s)
static void rtc_set_time(MC146818RtcState *s)
{
struct tm tm;
g_autofree const char *qom_path = object_get_canonical_path(OBJECT(s));
@ -609,7 +609,7 @@ static void rtc_set_time(RTCState *s)
qapi_event_send_rtc_change(qemu_timedate_diff(&tm), qom_path);
}
static void rtc_set_cmos(RTCState *s, const struct tm *tm)
static void rtc_set_cmos(MC146818RtcState *s, const struct tm *tm)
{
int year;
@ -633,7 +633,7 @@ static void rtc_set_cmos(RTCState *s, const struct tm *tm)
s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100);
}
static void rtc_update_time(RTCState *s)
static void rtc_update_time(MC146818RtcState *s)
{
struct tm ret;
time_t guest_sec;
@ -649,7 +649,7 @@ static void rtc_update_time(RTCState *s)
}
}
static int update_in_progress(RTCState *s)
static int update_in_progress(MC146818RtcState *s)
{
int64_t guest_nsec;
@ -678,7 +678,7 @@ static int update_in_progress(RTCState *s)
static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
unsigned size)
{
RTCState *s = opaque;
MC146818RtcState *s = opaque;
int ret;
if ((addr & 1) == 0) {
return 0xff;
@ -739,23 +739,21 @@ static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
}
}
void rtc_set_memory(ISADevice *dev, int addr, int val)
void mc146818rtc_set_cmos_data(MC146818RtcState *s, int addr, int val)
{
RTCState *s = MC146818_RTC(dev);
if (addr >= 0 && addr <= 127)
s->cmos_data[addr] = val;
}
int rtc_get_memory(ISADevice *dev, int addr)
int mc146818rtc_get_cmos_data(MC146818RtcState *s, int addr)
{
RTCState *s = MC146818_RTC(dev);
assert(addr >= 0 && addr <= 127);
return s->cmos_data[addr];
}
static void rtc_set_date_from_host(ISADevice *dev)
{
RTCState *s = MC146818_RTC(dev);
MC146818RtcState *s = MC146818_RTC(dev);
struct tm tm;
qemu_get_timedate(&tm, 0);
@ -770,7 +768,7 @@ static void rtc_set_date_from_host(ISADevice *dev)
static int rtc_pre_save(void *opaque)
{
RTCState *s = opaque;
MC146818RtcState *s = opaque;
rtc_update_time(s);
@ -779,7 +777,7 @@ static int rtc_pre_save(void *opaque)
static int rtc_post_load(void *opaque, int version_id)
{
RTCState *s = opaque;
MC146818RtcState *s = opaque;
if (version_id <= 2 || rtc_clock == QEMU_CLOCK_REALTIME) {
rtc_set_time(s);
@ -810,7 +808,7 @@ static int rtc_post_load(void *opaque, int version_id)
static bool rtc_irq_reinject_on_ack_count_needed(void *opaque)
{
RTCState *s = (RTCState *)opaque;
MC146818RtcState *s = (MC146818RtcState *)opaque;
return s->irq_reinject_on_ack_count != 0;
}
@ -820,7 +818,7 @@ static const VMStateDescription vmstate_rtc_irq_reinject_on_ack_count = {
.minimum_version_id = 1,
.needed = rtc_irq_reinject_on_ack_count_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT16(irq_reinject_on_ack_count, RTCState),
VMSTATE_UINT16(irq_reinject_on_ack_count, MC146818RtcState),
VMSTATE_END_OF_LIST()
}
};
@ -832,19 +830,19 @@ static const VMStateDescription vmstate_rtc = {
.pre_save = rtc_pre_save,
.post_load = rtc_post_load,
.fields = (VMStateField[]) {
VMSTATE_BUFFER(cmos_data, RTCState),
VMSTATE_UINT8(cmos_index, RTCState),
VMSTATE_BUFFER(cmos_data, MC146818RtcState),
VMSTATE_UINT8(cmos_index, MC146818RtcState),
VMSTATE_UNUSED(7*4),
VMSTATE_TIMER_PTR(periodic_timer, RTCState),
VMSTATE_INT64(next_periodic_time, RTCState),
VMSTATE_TIMER_PTR(periodic_timer, MC146818RtcState),
VMSTATE_INT64(next_periodic_time, MC146818RtcState),
VMSTATE_UNUSED(3*8),
VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
VMSTATE_UINT32_V(period, RTCState, 2),
VMSTATE_UINT64_V(base_rtc, RTCState, 3),
VMSTATE_UINT64_V(last_update, RTCState, 3),
VMSTATE_INT64_V(offset, RTCState, 3),
VMSTATE_TIMER_PTR_V(update_timer, RTCState, 3),
VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
VMSTATE_UINT32_V(irq_coalesced, MC146818RtcState, 2),
VMSTATE_UINT32_V(period, MC146818RtcState, 2),
VMSTATE_UINT64_V(base_rtc, MC146818RtcState, 3),
VMSTATE_UINT64_V(last_update, MC146818RtcState, 3),
VMSTATE_INT64_V(offset, MC146818RtcState, 3),
VMSTATE_TIMER_PTR_V(update_timer, MC146818RtcState, 3),
VMSTATE_UINT64_V(next_alarm_time, MC146818RtcState, 3),
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription*[]) {
@ -857,8 +855,9 @@ static const VMStateDescription vmstate_rtc = {
BIOS will read it and start S3 resume at POST Entry */
static void rtc_notify_suspend(Notifier *notifier, void *data)
{
RTCState *s = container_of(notifier, RTCState, suspend_notifier);
rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE);
MC146818RtcState *s = container_of(notifier, MC146818RtcState,
suspend_notifier);
mc146818rtc_set_cmos_data(s, 0xF, 0xFE);
}
static const MemoryRegionOps cmos_ops = {
@ -873,7 +872,7 @@ static const MemoryRegionOps cmos_ops = {
static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp)
{
RTCState *s = MC146818_RTC(obj);
MC146818RtcState *s = MC146818_RTC(obj);
rtc_update_time(s);
rtc_get_time(s, current_tm);
@ -882,7 +881,7 @@ static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp)
static void rtc_realizefn(DeviceState *dev, Error **errp)
{
ISADevice *isadev = ISA_DEVICE(dev);
RTCState *s = MC146818_RTC(dev);
MC146818RtcState *s = MC146818_RTC(dev);
s->cmos_data[RTC_REG_A] = 0x26;
s->cmos_data[RTC_REG_B] = 0x02;
@ -945,11 +944,12 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
QLIST_INSERT_HEAD(&rtc_devices, s, link);
}
ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
MC146818RtcState *mc146818_rtc_init(ISABus *bus, int base_year,
qemu_irq intercept_irq)
{
DeviceState *dev;
ISADevice *isadev;
RTCState *s;
MC146818RtcState *s;
isadev = isa_new(TYPE_MC146818_RTC);
dev = DEVICE(isadev);
@ -965,21 +965,21 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(isadev),
"date");
return isadev;
return s;
}
static Property mc146818rtc_properties[] = {
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
DEFINE_PROP_UINT16("iobase", RTCState, io_base, RTC_ISA_BASE),
DEFINE_PROP_UINT8("irq", RTCState, isairq, RTC_ISA_IRQ),
DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
DEFINE_PROP_INT32("base_year", MC146818RtcState, base_year, 1980),
DEFINE_PROP_UINT16("iobase", MC146818RtcState, io_base, RTC_ISA_BASE),
DEFINE_PROP_UINT8("irq", MC146818RtcState, isairq, RTC_ISA_IRQ),
DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", MC146818RtcState,
lost_tick_policy, LOST_TICK_POLICY_DISCARD),
DEFINE_PROP_END_OF_LIST(),
};
static void rtc_reset_enter(Object *obj, ResetType type)
{
RTCState *s = MC146818_RTC(obj);
MC146818RtcState *s = MC146818_RTC(obj);
/* Reason: VM do suspend self will set 0xfe
* Reset any values other than 0xfe(Guest suspend case) */
@ -1000,14 +1000,14 @@ static void rtc_reset_enter(Object *obj, ResetType type)
static void rtc_reset_hold(Object *obj)
{
RTCState *s = MC146818_RTC(obj);
MC146818RtcState *s = MC146818_RTC(obj);
qemu_irq_lower(s->irq);
}
static void rtc_build_aml(AcpiDevAmlIf *adev, Aml *scope)
{
RTCState *s = MC146818_RTC(adev);
MC146818RtcState *s = MC146818_RTC(adev);
Aml *dev;
Aml *crs;
@ -1045,7 +1045,7 @@ static void rtc_class_initfn(ObjectClass *klass, void *data)
static const TypeInfo mc146818rtc_info = {
.name = TYPE_MC146818_RTC,
.parent = TYPE_ISA_DEVICE,
.instance_size = sizeof(RTCState),
.instance_size = sizeof(MC146818RtcState),
.class_init = rtc_class_initfn,
.interfaces = (InterfaceInfo[]) {
{ TYPE_ACPI_DEV_AML_IF },

4
hw/sh4/r2d.c
View file

@ -38,7 +38,7 @@
#include "hw/qdev-properties.h"
#include "net/net.h"
#include "sh7750_regs.h"
#include "hw/ide.h"
#include "hw/ide/mmio.h"
#include "hw/irq.h"
#include "hw/loader.h"
#include "hw/usb.h"
@ -274,7 +274,7 @@ static void r2d_init(MachineState *machine)
dev = qdev_new("sysbus-sm501");
busdev = SYS_BUS_DEVICE(dev);
qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE);
qdev_prop_set_uint32(dev, "base", 0x10000000);
qdev_prop_set_uint64(dev, "dma-offset", 0x10000000);
qdev_prop_set_chr(dev, "chardev", serial_hd(2));
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10000000);

13
hw/sparc64/sun4u.c
View file

@ -28,6 +28,7 @@
#include "qapi/error.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
@ -84,7 +85,8 @@ struct EbusState {
PCIDevice parent_obj;
ISABus *isa_bus;
qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
qemu_irq *isa_irqs_in;
qemu_irq isa_irqs_out[ISA_NUM_IRQS];
uint64_t console_serial_base;
MemoryRegion bar0;
MemoryRegion bar1;
@ -287,7 +289,7 @@ static const TypeInfo power_info = {
static void ebus_isa_irq_handler(void *opaque, int n, int level)
{
EbusState *s = EBUS(opaque);
qemu_irq irq = s->isa_bus_irqs[n];
qemu_irq irq = s->isa_irqs_out[n];
/* Pass ISA bus IRQs onto their gpio equivalent */
trace_ebus_isa_irq_handler(n, level);
@ -303,7 +305,6 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp)
ISADevice *isa_dev;
SysBusDevice *sbd;
DeviceState *dev;
qemu_irq *isa_irq;
DriveInfo *fd[MAX_FD];
int i;
@ -315,9 +316,9 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp)
}
/* ISA bus */
isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
isa_bus_irqs(s->isa_bus, isa_irq);
qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
s->isa_irqs_in = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
isa_bus_register_input_irqs(s->isa_bus, s->isa_irqs_in);
qdev_init_gpio_out_named(DEVICE(s), s->isa_irqs_out, "isa-irq",
ISA_NUM_IRQS);
/* Serial ports */

1
hw/timer/hpet.c
View file

@ -30,6 +30,7 @@
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/timer.h"
#include "hw/qdev-properties.h"
#include "hw/timer/hpet.h"
#include "hw/sysbus.h"
#include "hw/rtc/mc146818rtc.h"

7
hw/usb/dev-smartcard-reader.c
View file

@ -278,7 +278,9 @@ typedef struct BulkIn {
struct CCIDBus {
BusState qbus;
};
typedef struct CCIDBus CCIDBus;
#define TYPE_CCID_BUS "ccid-bus"
OBJECT_DECLARE_SIMPLE_TYPE(CCIDBus, CCID_BUS)
/*
* powered - defaults to true, changed by PowerOn/PowerOff messages
@ -1174,9 +1176,6 @@ static Property ccid_props[] = {
DEFINE_PROP_END_OF_LIST(),
};
#define TYPE_CCID_BUS "ccid-bus"
OBJECT_DECLARE_SIMPLE_TYPE(CCIDBus, CCID_BUS)
static const TypeInfo ccid_bus_info = {
.name = TYPE_CCID_BUS,
.parent = TYPE_BUS,

436
hw/usb/hcd-ohci.c
View file

@ -23,7 +23,7 @@
* o Disable timers when nothing needs to be done, or remove timer usage
* all together.
* o BIOS work to boot from USB storage
*/
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
@ -39,7 +39,7 @@
#include "hcd-ohci.h"
/* This causes frames to occur 1000x slower */
//#define OHCI_TIME_WARP 1
/*#define OHCI_TIME_WARP 1*/
#define ED_LINK_LIMIT 32
@ -58,48 +58,48 @@ struct ohci_hcca {
#define ED_WBACK_OFFSET offsetof(struct ohci_ed, head)
#define ED_WBACK_SIZE 4
/* Bitfields for the first word of an Endpoint Desciptor. */
/* Bitfields for the first word of an Endpoint Descriptor. */
#define OHCI_ED_FA_SHIFT 0
#define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
#define OHCI_ED_FA_MASK (0x7f << OHCI_ED_FA_SHIFT)
#define OHCI_ED_EN_SHIFT 7
#define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
#define OHCI_ED_EN_MASK (0xf << OHCI_ED_EN_SHIFT)
#define OHCI_ED_D_SHIFT 11
#define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
#define OHCI_ED_S (1<<13)
#define OHCI_ED_K (1<<14)
#define OHCI_ED_F (1<<15)
#define OHCI_ED_D_MASK (3 << OHCI_ED_D_SHIFT)
#define OHCI_ED_S (1 << 13)
#define OHCI_ED_K (1 << 14)
#define OHCI_ED_F (1 << 15)
#define OHCI_ED_MPS_SHIFT 16
#define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
#define OHCI_ED_MPS_MASK (0x7ff << OHCI_ED_MPS_SHIFT)
/* Flags in the head field of an Endpoint Desciptor. */
/* Flags in the head field of an Endpoint Descriptor. */
#define OHCI_ED_H 1
#define OHCI_ED_C 2
/* Bitfields for the first word of a Transfer Desciptor. */
#define OHCI_TD_R (1<<18)
/* Bitfields for the first word of a Transfer Descriptor. */
#define OHCI_TD_R (1 << 18)
#define OHCI_TD_DP_SHIFT 19
#define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
#define OHCI_TD_DP_MASK (3 << OHCI_TD_DP_SHIFT)
#define OHCI_TD_DI_SHIFT 21
#define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
#define OHCI_TD_T0 (1<<24)
#define OHCI_TD_T1 (1<<25)
#define OHCI_TD_DI_MASK (7 << OHCI_TD_DI_SHIFT)
#define OHCI_TD_T0 (1 << 24)
#define OHCI_TD_T1 (1 << 25)
#define OHCI_TD_EC_SHIFT 26
#define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
#define OHCI_TD_EC_MASK (3 << OHCI_TD_EC_SHIFT)
#define OHCI_TD_CC_SHIFT 28
#define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
#define OHCI_TD_CC_MASK (0xf << OHCI_TD_CC_SHIFT)
/* Bitfields for the first word of an Isochronous Transfer Desciptor. */
/* CC & DI - same as in the General Transfer Desciptor */
/* Bitfields for the first word of an Isochronous Transfer Descriptor. */
/* CC & DI - same as in the General Transfer Descriptor */
#define OHCI_TD_SF_SHIFT 0
#define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
#define OHCI_TD_SF_MASK (0xffff << OHCI_TD_SF_SHIFT)
#define OHCI_TD_FC_SHIFT 24
#define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
#define OHCI_TD_FC_MASK (7 << OHCI_TD_FC_SHIFT)
/* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
/* Isochronous Transfer Descriptor - Offset / PacketStatusWord */
#define OHCI_TD_PSW_CC_SHIFT 12
#define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
#define OHCI_TD_PSW_CC_MASK (0xf << OHCI_TD_PSW_CC_SHIFT)
#define OHCI_TD_PSW_SIZE_SHIFT 0
#define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
#define OHCI_TD_PSW_SIZE_MASK (0xfff << OHCI_TD_PSW_SIZE_SHIFT)
#define OHCI_PAGE_MASK 0xfffff000
#define OHCI_OFFSET_MASK 0xfff
@ -112,7 +112,7 @@ struct ohci_hcca {
#define OHCI_SET_BM(val, field, newval) do { \
val &= ~OHCI_##field##_MASK; \
val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
} while(0)
} while (0)
/* endpoint descriptor */
struct ohci_ed {
@ -142,35 +142,35 @@ struct ohci_iso_td {
#define USB_HZ 12000000
/* OHCI Local stuff */
#define OHCI_CTL_CBSR ((1<<0)|(1<<1))
#define OHCI_CTL_PLE (1<<2)
#define OHCI_CTL_IE (1<<3)
#define OHCI_CTL_CLE (1<<4)
#define OHCI_CTL_BLE (1<<5)
#define OHCI_CTL_HCFS ((1<<6)|(1<<7))
#define OHCI_CTL_CBSR ((1 << 0) | (1 << 1))
#define OHCI_CTL_PLE (1 << 2)
#define OHCI_CTL_IE (1 << 3)
#define OHCI_CTL_CLE (1 << 4)
#define OHCI_CTL_BLE (1 << 5)
#define OHCI_CTL_HCFS ((1 << 6) | (1 << 7))
#define OHCI_USB_RESET 0x00
#define OHCI_USB_RESUME 0x40
#define OHCI_USB_OPERATIONAL 0x80
#define OHCI_USB_SUSPEND 0xc0
#define OHCI_CTL_IR (1<<8)
#define OHCI_CTL_RWC (1<<9)
#define OHCI_CTL_RWE (1<<10)
#define OHCI_CTL_IR (1 << 8)
#define OHCI_CTL_RWC (1 << 9)
#define OHCI_CTL_RWE (1 << 10)
#define OHCI_STATUS_HCR (1<<0)
#define OHCI_STATUS_CLF (1<<1)
#define OHCI_STATUS_BLF (1<<2)
#define OHCI_STATUS_OCR (1<<3)
#define OHCI_STATUS_SOC ((1<<6)|(1<<7))
#define OHCI_STATUS_HCR (1 << 0)
#define OHCI_STATUS_CLF (1 << 1)
#define OHCI_STATUS_BLF (1 << 2)
#define OHCI_STATUS_OCR (1 << 3)
#define OHCI_STATUS_SOC ((1 << 6) | (1 << 7))
#define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */
#define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */
#define OHCI_INTR_SF (1U<<2) /* Start of frame */
#define OHCI_INTR_RD (1U<<3) /* Resume detect */
#define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */
#define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */
#define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */
#define OHCI_INTR_OC (1U<<30) /* Ownership change */
#define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */
#define OHCI_INTR_SO (1U << 0) /* Scheduling overrun */
#define OHCI_INTR_WD (1U << 1) /* HcDoneHead writeback */
#define OHCI_INTR_SF (1U << 2) /* Start of frame */
#define OHCI_INTR_RD (1U << 3) /* Resume detect */
#define OHCI_INTR_UE (1U << 4) /* Unrecoverable error */
#define OHCI_INTR_FNO (1U << 5) /* Frame number overflow */
#define OHCI_INTR_RHSC (1U << 6) /* Root hub status change */
#define OHCI_INTR_OC (1U << 30) /* Ownership change */
#define OHCI_INTR_MIE (1U << 31) /* Master Interrupt Enable */
#define OHCI_HCCA_SIZE 0x100
#define OHCI_HCCA_MASK 0xffffff00
@ -181,40 +181,40 @@ struct ohci_iso_td {
#define OHCI_FMI_FSMPS 0xffff0000
#define OHCI_FMI_FIT 0x80000000
#define OHCI_FR_RT (1U<<31)
#define OHCI_FR_RT (1U << 31)
#define OHCI_LS_THRESH 0x628
#define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
#define OHCI_RHA_PSM (1<<8)
#define OHCI_RHA_NPS (1<<9)
#define OHCI_RHA_DT (1<<10)
#define OHCI_RHA_OCPM (1<<11)
#define OHCI_RHA_NOCP (1<<12)
#define OHCI_RHA_PSM (1 << 8)
#define OHCI_RHA_NPS (1 << 9)
#define OHCI_RHA_DT (1 << 10)
#define OHCI_RHA_OCPM (1 << 11)
#define OHCI_RHA_NOCP (1 << 12)
#define OHCI_RHA_POTPGT_MASK 0xff000000
#define OHCI_RHS_LPS (1U<<0)
#define OHCI_RHS_OCI (1U<<1)
#define OHCI_RHS_DRWE (1U<<15)
#define OHCI_RHS_LPSC (1U<<16)
#define OHCI_RHS_OCIC (1U<<17)
#define OHCI_RHS_CRWE (1U<<31)
#define OHCI_PORT_CCS (1<<0)
#define OHCI_PORT_PES (1<<1)
#define OHCI_PORT_PSS (1<<2)
#define OHCI_PORT_POCI (1<<3)
#define OHCI_PORT_PRS (1<<4)
#define OHCI_PORT_PPS (1<<8)
#define OHCI_PORT_LSDA (1<<9)
#define OHCI_PORT_CSC (1<<16)
#define OHCI_PORT_PESC (1<<17)
#define OHCI_PORT_PSSC (1<<18)
#define OHCI_PORT_OCIC (1<<19)
#define OHCI_PORT_PRSC (1<<20)
#define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
|OHCI_PORT_OCIC|OHCI_PORT_PRSC)
#define OHCI_RHS_LPS (1U << 0)
#define OHCI_RHS_OCI (1U << 1)
#define OHCI_RHS_DRWE (1U << 15)
#define OHCI_RHS_LPSC (1U << 16)
#define OHCI_RHS_OCIC (1U << 17)
#define OHCI_RHS_CRWE (1U << 31)
#define OHCI_PORT_CCS (1 << 0)
#define OHCI_PORT_PES (1 << 1)
#define OHCI_PORT_PSS (1 << 2)
#define OHCI_PORT_POCI (1 << 3)
#define OHCI_PORT_PRS (1 << 4)
#define OHCI_PORT_PPS (1 << 8)
#define OHCI_PORT_LSDA (1 << 9)
#define OHCI_PORT_CSC (1 << 16)
#define OHCI_PORT_PESC (1 << 17)
#define OHCI_PORT_PSSC (1 << 18)
#define OHCI_PORT_OCIC (1 << 19)
#define OHCI_PORT_PRSC (1 << 20)
#define OHCI_PORT_WTC (OHCI_PORT_CSC | OHCI_PORT_PESC | \
OHCI_PORT_PSSC | OHCI_PORT_OCIC | \
OHCI_PORT_PRSC)
#define OHCI_TD_DIR_SETUP 0x0
#define OHCI_TD_DIR_OUT 0x1
#define OHCI_TD_DIR_IN 0x2
@ -235,6 +235,24 @@ struct ohci_iso_td {
#define OHCI_HRESET_FSBIR (1 << 0)
static const char *ohci_reg_names[] = {
"HcRevision", "HcControl", "HcCommandStatus", "HcInterruptStatus",
"HcInterruptEnable", "HcInterruptDisable", "HcHCCA", "HcPeriodCurrentED",
"HcControlHeadED", "HcControlCurrentED", "HcBulkHeadED", "HcBulkCurrentED",
"HcDoneHead", "HcFmInterval", "HcFmRemaining", "HcFmNumber",
"HcPeriodicStart", "HcLSThreshold", "HcRhDescriptorA", "HcRhDescriptorB",
"HcRhStatus"
};
static const char *ohci_reg_name(hwaddr addr)
{
if (addr >> 2 < ARRAY_SIZE(ohci_reg_names)) {
return ohci_reg_names[addr >> 2];
} else {
return "<unknown>";
}
}
static void ohci_die(OHCIState *ohci)
{
ohci->ohci_die(ohci);
@ -335,8 +353,8 @@ static void ohci_soft_reset(OHCIState *ohci)
ohci->per_cur = 0;
ohci->done = 0;
ohci->done_count = 7;
/* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
/*
* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
* I took the value linux sets ...
*/
ohci->fsmps = 0x2778;
@ -460,10 +478,10 @@ static inline int ohci_read_hcca(OHCIState *ohci,
static inline int ohci_put_ed(OHCIState *ohci,
dma_addr_t addr, struct ohci_ed *ed)
{
/* ed->tail is under control of the HCD.
/*
* ed->tail is under control of the HCD.
* Since just ed->head is changed by HC, just write back this
*/
return put_dwords(ohci, addr + ED_WBACK_OFFSET,
(uint32_t *)((char *)ed + ED_WBACK_OFFSET),
ED_WBACK_SIZE >> 2);
@ -499,9 +517,9 @@ static int ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
ptr = td->cbp;
n = 0x1000 - (ptr & 0xfff);
if (n > len)
if (n > len) {
n = len;
}
if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
n, dir, MEMTXATTRS_UNSPECIFIED)) {
return -1;
@ -527,9 +545,9 @@ static int ohci_copy_iso_td(OHCIState *ohci,
ptr = start_addr;
n = 0x1000 - (ptr & 0xfff);
if (n > len)
if (n > len) {
n = len;
}
if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
n, dir, MEMTXATTRS_UNSPECIFIED)) {
return -1;
@ -584,7 +602,7 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed)
starting_frame = OHCI_BM(iso_td.flags, TD_SF);
frame_count = OHCI_BM(iso_td.flags, TD_FC);
relative_frame_number = USUB(ohci->frame_number, starting_frame);
relative_frame_number = USUB(ohci->frame_number, starting_frame);
trace_usb_ohci_iso_td_head(
ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
@ -601,8 +619,10 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed)
trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number);
return 1;
} else if (relative_frame_number > frame_count) {
/* ISO TD expired - retire the TD to the Done Queue and continue with
the next ISO TD of the same ED */
/*
* ISO TD expired - retire the TD to the Done Queue and continue with
* the next ISO TD of the same ED
*/
trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number,
frame_count);
if (OHCI_CC_DATAOVERRUN == OHCI_BM(iso_td.flags, TD_CC)) {
@ -615,8 +635,9 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed)
iso_td.next = ohci->done;
ohci->done = addr;
i = OHCI_BM(iso_td.flags, TD_DI);
if (i < ohci->done_count)
if (i < ohci->done_count) {
ohci->done_count = i;
}
if (ohci_put_iso_td(ohci, addr, &iso_td)) {
ohci_die(ohci);
return 1;
@ -655,8 +676,8 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed)
next_offset = iso_td.be;
}
if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
((relative_frame_number < frame_count) &&
if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
((relative_frame_number < frame_count) &&
!(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset, next_offset);
return 1;
@ -801,8 +822,9 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed)
iso_td.next = ohci->done;
ohci->done = addr;
i = OHCI_BM(iso_td.flags, TD_DI);
if (i < ohci->done_count)
if (i < ohci->done_count) {
ohci->done_count = i;
}
}
if (ohci_put_iso_td(ohci, addr, &iso_td)) {
ohci_die(ohci);
@ -845,9 +867,10 @@ static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len)
}
}
/* Service a transport descriptor.
Returns nonzero to terminate processing of this endpoint. */
/*
* Service a transport descriptor.
* Returns nonzero to terminate processing of this endpoint.
*/
static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
{
int dir;
@ -869,7 +892,7 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
return 1;
}
/* See if this TD has already been submitted to the device. */
/* See if this TD has already been submitted to the device. */
completion = (addr == ohci->async_td);
if (completion && !ohci->async_complete) {
trace_usb_ohci_td_skip_async();
@ -885,7 +908,7 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
switch (dir) {
case OHCI_TD_DIR_OUT:
case OHCI_TD_DIR_IN:
/* Same value. */
/* Same value. */
break;
default:
dir = OHCI_BM(td.flags, TD_DP);
@ -956,11 +979,12 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
}
ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN));
if (ohci->async_td) {
/* ??? The hardware should allow one active packet per
endpoint. We only allow one active packet per controller.
This should be sufficient as long as devices respond in a
timely manner.
*/
/*
* ??? The hardware should allow one active packet per
* endpoint. We only allow one active packet per controller.
* This should be sufficient as long as devices respond in a
* timely manner.
*/
trace_usb_ohci_td_too_many_pending(ep->nr);
return 1;
}
@ -996,7 +1020,7 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
/* Writeback */
if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
/* Transmission succeeded. */
/* Transmission succeeded. */
if (ret == len) {
td.cbp = 0;
} else {
@ -1018,8 +1042,9 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
/* Setting ED_C is part of the TD retirement process */
ed->head &= ~OHCI_ED_C;
if (td.flags & OHCI_TD_T0)
if (td.flags & OHCI_TD_T0) {
ed->head |= OHCI_ED_C;
}
} else {
if (ret >= 0) {
trace_usb_ohci_td_underrun();
@ -1048,8 +1073,10 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
OHCI_SET_BM(td.flags, TD_EC, 3);
break;
}
/* An error occurred so we have to clear the interrupt counter. See
* spec at 6.4.4 on page 104 */
/*
* An error occurred so we have to clear the interrupt counter.
* See spec at 6.4.4 on page 104
*/
ohci->done_count = 0;
}
ed->head |= OHCI_ED_H;
@ -1061,8 +1088,9 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
td.next = ohci->done;
ohci->done = addr;
i = OHCI_BM(td.flags, TD_DI);
if (i < ohci->done_count)
if (i < ohci->done_count) {
ohci->done_count = i;
}
exit_no_retire:
if (ohci_put_td(ohci, addr, &td)) {
ohci_die(ohci);
@ -1071,7 +1099,7 @@ exit_no_retire:
return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
}
/* Service an endpoint list. Returns nonzero if active TD were found. */
/* Service an endpoint list. Returns nonzero if active TD were found. */
static int ohci_service_ed_list(OHCIState *ohci, uint32_t head)
{
struct ohci_ed ed;
@ -1081,9 +1109,9 @@ static int ohci_service_ed_list(OHCIState *ohci, uint32_t head)
uint32_t link_cnt = 0;
active = 0;
if (head == 0)
if (head == 0) {
return 0;
}
for (cur = head; cur && link_cnt++ < ED_LINK_LIMIT; cur = next_ed) {
if (ohci_read_ed(ohci, cur, &ed)) {
trace_usb_ohci_ed_read_error(cur);
@ -1095,7 +1123,7 @@ static int ohci_service_ed_list(OHCIState *ohci, uint32_t head)
if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
uint32_t addr;
/* Cancel pending packets for ED that have been paused. */
/* Cancel pending packets for ED that have been paused. */
addr = ed.head & OHCI_DPTR_MASK;
if (ohci->async_td && addr == ohci->async_td) {
usb_cancel_packet(&ohci->usb_packet);
@ -1112,15 +1140,16 @@ static int ohci_service_ed_list(OHCIState *ohci, uint32_t head)
ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
trace_usb_ohci_ed_pkt_flags(
OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S) != 0,
(ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
OHCI_BM(ed.flags, ED_MPS));
active = 1;
if ((ed.flags & OHCI_ED_F) == 0) {
if (ohci_service_td(ohci, &ed))
if (ohci_service_td(ohci, &ed)) {
break;
}
} else {
/* Handle isochronous endpoints */
if (ohci_service_iso_td(ohci, &ed)) {
@ -1151,7 +1180,7 @@ static void ohci_sof(OHCIState *ohci)
ohci_set_interrupt(ohci, OHCI_INTR_SF);
}
/* Process Control and Bulk lists. */
/* Process Control and Bulk lists. */
static void ohci_process_lists(OHCIState *ohci)
{
if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
@ -1192,7 +1221,7 @@ static void ohci_frame_boundary(void *opaque)
ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]));
}
/* Cancel all pending packets if either of the lists has been disabled. */
/* Cancel all pending packets if either of the lists has been disabled. */
if (ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
ohci_stop_endpoints(ohci);
}
@ -1212,19 +1241,21 @@ static void ohci_frame_boundary(void *opaque)
hcca.frame = cpu_to_le16(ohci->frame_number);
if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
if (!ohci->done)
if (!ohci->done) {
abort();
if (ohci->intr & ohci->intr_status)
}
if (ohci->intr & ohci->intr_status) {
ohci->done |= 1;
}
hcca.done = cpu_to_le32(ohci->done);
ohci->done = 0;
ohci->done_count = 7;
ohci_set_interrupt(ohci, OHCI_INTR_WD);
}
if (ohci->done_count != 7 && ohci->done_count != 0)
if (ohci->done_count != 7 && ohci->done_count != 0) {
ohci->done_count--;
}
/* Do SOF stuff here */
ohci_sof(ohci);
@ -1234,18 +1265,17 @@ static void ohci_frame_boundary(void *opaque)
}
}
/* Start sending SOF tokens across the USB bus, lists are processed in
/*
* Start sending SOF tokens across the USB bus, lists are processed in
* next frame
*/
static int ohci_bus_start(OHCIState *ohci)
{
trace_usb_ohci_start(ohci->name);
/* Delay the first SOF event by one frame time as
* linux driver is not ready to receive it and
* can meet some race conditions
/*
* Delay the first SOF event by one frame time as linux driver is
* not ready to receive it and can meet some race conditions
*/
ohci->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
ohci_eof_timer(ohci);
@ -1259,39 +1289,7 @@ void ohci_bus_stop(OHCIState *ohci)
timer_del(ohci->eof_timer);
}
/* Sets a flag in a port status register but only set it if the port is
* connected, if not set ConnectStatusChange flag. If flag is enabled
* return 1.
*/
static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
{
int ret = 1;
/* writing a 0 has no effect */
if (val == 0)
return 0;
/* If CurrentConnectStatus is cleared we set
* ConnectStatusChange
*/
if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
if (ohci->rhstatus & OHCI_RHS_DRWE) {
/* TODO: CSC is a wakeup event */
}
return 0;
}
if (ohci->rhport[i].ctrl & val)
ret = 0;
/* set the bit */
ohci->rhport[i].ctrl |= val;
return ret;
}
/* Set the frame interval - frame interval toggle is manipulated by the hcd only */
/* Frame interval toggle is manipulated by the hcd only */
static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
{
val &= OHCI_FMI_FI;
@ -1308,10 +1306,8 @@ static void ohci_port_power(OHCIState *ohci, int i, int p)
if (p) {
ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
} else {
ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
OHCI_PORT_CCS|
OHCI_PORT_PSS|
OHCI_PORT_PRS);
ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS | OHCI_PORT_CCS |
OHCI_PORT_PSS | OHCI_PORT_PRS);
}
}
@ -1326,9 +1322,9 @@ static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
new_state = ohci->ctl & OHCI_CTL_HCFS;
/* no state change */
if (old_state == new_state)
if (old_state == new_state) {
return;
}
trace_usb_ohci_set_ctl(ohci->name, new_state);
switch (new_state) {
case OHCI_USB_OPERATIONAL:
@ -1354,21 +1350,19 @@ static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
uint16_t fr;
int64_t tks;
if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
return (ohci->frt << 31);
/* Being in USB operational state guarnatees sof_time was
* set already.
*/
if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL) {
return ohci->frt << 31;
}
/* Being in USB operational state guarnatees sof_time was set already. */
tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time;
if (tks < 0) {
tks = 0;
}
/* avoid muldiv if possible */
if (tks >= usb_frame_time)
return (ohci->frt << 31);
if (tks >= usb_frame_time) {
return ohci->frt << 31;
}
tks = tks / usb_bit_time;
fr = (uint16_t)(ohci->fi - tks);
@ -1384,33 +1378,66 @@ static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
old_state = ohci->rhstatus;
/* write 1 to clear OCIC */
if (val & OHCI_RHS_OCIC)
if (val & OHCI_RHS_OCIC) {
ohci->rhstatus &= ~OHCI_RHS_OCIC;
}
if (val & OHCI_RHS_LPS) {
int i;
for (i = 0; i < ohci->num_ports; i++)
for (i = 0; i < ohci->num_ports; i++) {
ohci_port_power(ohci, i, 0);
}
trace_usb_ohci_hub_power_down();
}
if (val & OHCI_RHS_LPSC) {
int i;
for (i = 0; i < ohci->num_ports; i++)
for (i = 0; i < ohci->num_ports; i++) {
ohci_port_power(ohci, i, 1);
}
trace_usb_ohci_hub_power_up();
}
if (val & OHCI_RHS_DRWE)
if (val & OHCI_RHS_DRWE) {
ohci->rhstatus |= OHCI_RHS_DRWE;
if (val & OHCI_RHS_CRWE)
}
if (val & OHCI_RHS_CRWE) {
ohci->rhstatus &= ~OHCI_RHS_DRWE;
if (old_state != ohci->rhstatus)
}
if (old_state != ohci->rhstatus) {
ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
}
}
/*
* Sets a flag in a port status reg but only set it if the port is connected.
* If not set ConnectStatusChange flag. If flag is enabled return 1.
*/
static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
{
int ret = 1;
/* writing a 0 has no effect */
if (val == 0) {
return 0;
}
/* If CurrentConnectStatus is cleared we set ConnectStatusChange */
if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
if (ohci->rhstatus & OHCI_RHS_DRWE) {
/* TODO: CSC is a wakeup event */
}
return 0;
}
if (ohci->rhport[i].ctrl & val) {
ret = 0;
}
/* set the bit */
ohci->rhport[i].ctrl |= val;
return ret;
}
/* Set root hub port status */
@ -1423,12 +1450,12 @@ static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
old_state = port->ctrl;
/* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
if (val & OHCI_PORT_WTC)
if (val & OHCI_PORT_WTC) {
port->ctrl &= ~(val & OHCI_PORT_WTC);
if (val & OHCI_PORT_CCS)
}
if (val & OHCI_PORT_CCS) {
port->ctrl &= ~OHCI_PORT_PES;
}
ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
@ -1439,20 +1466,20 @@ static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
trace_usb_ohci_port_reset(portnum);
usb_device_reset(port->port.dev);
port->ctrl &= ~OHCI_PORT_PRS;
/* ??? Should this also set OHCI_PORT_PESC. */
/* ??? Should this also set OHCI_PORT_PESC. */
port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
}
/* Invert order here to ensure in ambiguous case, device is
* powered up...
*/
if (val & OHCI_PORT_LSDA)
/* Invert order here to ensure in ambiguous case, device is powered up. */
if (val & OHCI_PORT_LSDA) {
ohci_port_power(ohci, portnum, 0);
if (val & OHCI_PORT_PPS)
}
if (val & OHCI_PORT_PPS) {
ohci_port_power(ohci, portnum, 1);
if (old_state != port->ctrl)
}
if (old_state != port->ctrl) {
ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
}
}
static uint64_t ohci_mem_read(void *opaque,
@ -1469,6 +1496,8 @@ static uint64_t ohci_mem_read(void *opaque,
} else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
/* HcRhPortStatus */
retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
trace_usb_ohci_mem_port_read(size, "HcRhPortStatus", (addr - 0x50) >> 2,
addr, addr >> 2, retval);
} else {
switch (addr >> 2) {
case 0: /* HcRevision */
@ -1573,6 +1602,10 @@ static uint64_t ohci_mem_read(void *opaque,
trace_usb_ohci_mem_read_bad_offset(addr);
retval = 0xffffffff;
}
if (addr != 0xc || retval) {
trace_usb_ohci_mem_read(size, ohci_reg_name(addr), addr, addr >> 2,
retval);
}
}
return retval;
@ -1593,10 +1626,13 @@ static void ohci_mem_write(void *opaque,
if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
/* HcRhPortStatus */
trace_usb_ohci_mem_port_write(size, "HcRhPortStatus",
(addr - 0x50) >> 2, addr, addr >> 2, val);
ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
return;
}
trace_usb_ohci_mem_write(size, ohci_reg_name(addr), addr, addr >> 2, val);
switch (addr >> 2) {
case 1: /* HcControl */
ohci_set_ctl(ohci, val);
@ -1609,8 +1645,9 @@ static void ohci_mem_write(void *opaque,
/* Bits written as '0' remain unchanged in the register */
ohci->status |= val;
if (ohci->status & OHCI_STATUS_HCR)
if (ohci->status & OHCI_STATUS_HCR) {
ohci_soft_reset(ohci);
}
break;
case 3: /* HcInterruptStatus */
@ -1688,8 +1725,9 @@ static void ohci_mem_write(void *opaque,
case 25: /* HcHReset */
ohci->hreset = val & ~OHCI_HRESET_FSBIR;
if (val & OHCI_HRESET_FSBIR)
if (val & OHCI_HRESET_FSBIR) {
ohci_hard_reset(ohci);
}
break;
case 26: /* HcHInterruptEnable */
@ -1827,7 +1865,7 @@ static USBBusOps ohci_bus_ops = {
void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports,
dma_addr_t localmem_base, char *masterbus,
uint32_t firstport, AddressSpace *as,
void (*ohci_die_fn)(struct OHCIState *), Error **errp)
void (*ohci_die_fn)(OHCIState *), Error **errp)
{
Error *err = NULL;
int i;
@ -1859,7 +1897,7 @@ void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports,
ohci->num_ports = num_ports;
if (masterbus) {
USBPort *ports[OHCI_MAX_PORTS];
for(i = 0; i < num_ports; i++) {
for (i = 0; i < num_ports; i++) {
ports[i] = &ohci->rhport[i].port;
}
usb_register_companion(masterbus, ports, num_ports,
@ -1892,7 +1930,7 @@ void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports,
ohci_frame_boundary, ohci);
}
/**
/*
* A typical OHCI will stop operating and set itself into error state
* (which can be queried by MMIO) to signal that it got an error.
*/

11
hw/usb/hcd-ohci.h
View file

@ -21,6 +21,7 @@
#ifndef HCD_OHCI_H
#define HCD_OHCI_H
#include "hw/sysbus.h"
#include "sysemu/dma.h"
#include "hw/usb.h"
#include "qom/object.h"
@ -33,7 +34,9 @@ typedef struct OHCIPort {
uint32_t ctrl;
} OHCIPort;
typedef struct OHCIState {
typedef struct OHCIState OHCIState;
struct OHCIState {
USBBus bus;
qemu_irq irq;
MemoryRegion mem;
@ -89,8 +92,8 @@ typedef struct OHCIState {
uint32_t async_td;
bool async_complete;
void (*ohci_die)(struct OHCIState *ohci);
} OHCIState;
void (*ohci_die)(OHCIState *ohci);
};
#define TYPE_SYSBUS_OHCI "sysbus-ohci"
OBJECT_DECLARE_SIMPLE_TYPE(OHCISysBusState, SYSBUS_OHCI)
@ -112,7 +115,7 @@ extern const VMStateDescription vmstate_ohci_state;
void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports,
dma_addr_t localmem_base, char *masterbus,
uint32_t firstport, AddressSpace *as,
void (*ohci_die_fn)(struct OHCIState *), Error **errp);
void (*ohci_die_fn)(OHCIState *), Error **errp);
void ohci_bus_stop(OHCIState *ohci);
void ohci_stop_endpoints(OHCIState *ohci);
void ohci_hard_reset(OHCIState *ohci);

7
hw/usb/hcd-uhci.c
View file

@ -60,9 +60,7 @@ enum {
TD_RESULT_ASYNC_CONT,
};
typedef struct UHCIState UHCIState;
typedef struct UHCIAsync UHCIAsync;
typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass;
struct UHCIPCIDeviceClass {
PCIDeviceClass parent_class;
@ -1161,8 +1159,7 @@ static USBBusOps uhci_bus_ops = {
void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
{
Error *err = NULL;
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class);
UHCIPCIDeviceClass *u = UHCI_GET_CLASS(dev);
UHCIState *s = UHCI(dev);
uint8_t *pci_conf = s->dev.config;
int i;
@ -1269,7 +1266,7 @@ void uhci_data_class_init(ObjectClass *klass, void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class);
UHCIPCIDeviceClass *u = UHCI_CLASS(klass);
UHCIInfo *info = data;
k->realize = info->realize ? info->realize : usb_uhci_common_realize;

2
hw/usb/hcd-uhci.h
View file

@ -75,7 +75,7 @@ typedef struct UHCIState {
} UHCIState;
#define TYPE_UHCI "pci-uhci-usb"
DECLARE_INSTANCE_CHECKER(UHCIState, UHCI, TYPE_UHCI)
OBJECT_DECLARE_TYPE(UHCIState, UHCIPCIDeviceClass, UHCI)
typedef struct UHCIInfo {
const char *name;

8
hw/usb/hcd-xhci-nec.c
View file

@ -27,14 +27,16 @@
#include "hcd-xhci-pci.h"
typedef struct XHCINecState {
OBJECT_DECLARE_SIMPLE_TYPE(XHCINecState, NEC_XHCI)
struct XHCINecState {
/*< private >*/
XHCIPciState parent_obj;
/*< public >*/
uint32_t flags;
uint32_t intrs;
uint32_t slots;
} XHCINecState;
};
static Property nec_xhci_properties[] = {
DEFINE_PROP_ON_OFF_AUTO("msi", XHCIPciState, msi, ON_OFF_AUTO_AUTO),
@ -51,7 +53,7 @@ static Property nec_xhci_properties[] = {
static void nec_xhci_instance_init(Object *obj)
{
XHCIPciState *pci = XHCI_PCI(obj);
XHCINecState *nec = container_of(pci, XHCINecState, parent_obj);
XHCINecState *nec = NEC_XHCI(obj);
pci->xhci.flags = nec->flags;
pci->xhci.numintrs = nec->intrs;

4
hw/usb/trace-events
View file

@ -57,8 +57,12 @@ usb_ohci_ed_read_error(uint32_t addr) "ED read error at 0x%x"
usb_ohci_ed_pkt(uint32_t cur, int h, int c, uint32_t head, uint32_t tail, uint32_t next) "ED @ 0x%.8x h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x"
usb_ohci_ed_pkt_flags(uint32_t fa, uint32_t en, uint32_t d, int s, int k, int f, uint32_t mps) "fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u"
usb_ohci_hcca_read_error(uint32_t addr) "HCCA read error at 0x%x"
usb_ohci_mem_read(uint32_t size, const char *name, uint32_t addr, uint32_t offs, uint32_t val) "%d %s 0x%x %d -> 0x%x"
usb_ohci_mem_port_read(uint32_t size, const char *name, uint32_t port, uint32_t addr, uint32_t offs, uint32_t val) "%d %s[%d] 0x%x %d -> 0x%x"
usb_ohci_mem_read_unaligned(uint32_t addr) "at 0x%x"
usb_ohci_mem_read_bad_offset(uint32_t addr) "0x%x"
usb_ohci_mem_write(uint32_t size, const char *name, uint32_t addr, uint32_t offs, uint32_t val) "%d %s 0x%x %d <- 0x%x"
usb_ohci_mem_port_write(uint32_t size, const char *name, uint32_t port, uint32_t addr, uint32_t offs, uint32_t val) "%d %s[%d] 0x%x %d <- 0x%x"
usb_ohci_mem_write_unaligned(uint32_t addr) "at 0x%x"
usb_ohci_mem_write_bad_offset(uint32_t addr) "0x%x"
usb_ohci_process_lists(uint32_t head, uint32_t cur) "head 0x%x, cur 0x%x"

16
hw/usb/u2f.h
View file

@ -31,22 +31,16 @@
#define U2FHID_PACKET_SIZE 64
#define U2FHID_PENDING_IN_NUM 32
typedef struct U2FKeyState U2FKeyState;
typedef struct U2FKeyInfo U2FKeyInfo;
#define TYPE_U2F_KEY "u2f-key"
#define U2F_KEY(obj) \
OBJECT_CHECK(U2FKeyState, (obj), TYPE_U2F_KEY)
#define U2F_KEY_CLASS(klass) \
OBJECT_CLASS_CHECK(U2FKeyClass, (klass), TYPE_U2F_KEY)
#define U2F_KEY_GET_CLASS(obj) \
OBJECT_GET_CLASS(U2FKeyClass, (obj), TYPE_U2F_KEY)
OBJECT_DECLARE_TYPE(U2FKeyState, U2FKeyClass, U2F_KEY)
/*
* Callbacks to be used by the U2F key base device (i.e. hw/u2f.c)
* to interact with its variants (i.e. hw/u2f-*.c)
*/
typedef struct U2FKeyClass {
struct U2FKeyClass {
/*< private >*/
USBDeviceClass parent_class;
@ -55,12 +49,12 @@ typedef struct U2FKeyClass {
const uint8_t packet[U2FHID_PACKET_SIZE]);
void (*realize)(U2FKeyState *key, Error **errp);
void (*unrealize)(U2FKeyState *key);
} U2FKeyClass;
};
/*
* State of the U2F key base device (i.e. hw/u2f.c)
*/
typedef struct U2FKeyState {
struct U2FKeyState {
USBDevice dev;
USBEndpoint *ep;
uint8_t idle;
@ -70,7 +64,7 @@ typedef struct U2FKeyState {
uint8_t pending_in_start;
uint8_t pending_in_end;
uint8_t pending_in_num;
} U2FKeyState;
};
/*
* API to be used by the U2F key device variants (i.e. hw/u2f-*.c)

1
include/exec/gen-icount.h
View file

@ -2,7 +2,6 @@
#define GEN_ICOUNT_H
#include "exec/exec-all.h"
#include "qemu/timer.h"
/* Helpers for instruction counting code generation. */

80
include/exec/replay-core.h Normal file
View file

@ -0,0 +1,80 @@
/*
* QEMU replay core API
*
* Copyright (c) 2010-2015 Institute for System Programming
* of the Russian Academy of Sciences.
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef EXEC_REPLAY_H
#define EXEC_REPLAY_H
#include "qapi/qapi-types-replay.h"
extern ReplayMode replay_mode;
/* Replay process control functions */
/* Enables recording or saving event log with specified parameters */
void replay_configure(struct QemuOpts *opts);
/* Initializes timers used for snapshotting and enables events recording */
void replay_start(void);
/* Closes replay log file and frees other resources. */
void replay_finish(void);
/* Adds replay blocker with the specified error description */
void replay_add_blocker(const char *feature);
/* Returns name of the replay log file */
const char *replay_get_filename(void);
/*
* Start making one step in backward direction.
* Used by gdbstub for backwards debugging.
* Returns true on success.
*/
bool replay_reverse_step(void);
/*
* Start searching the last breakpoint/watchpoint.
* Used by gdbstub for backwards debugging.
* Returns true if the process successfully started.
*/
bool replay_reverse_continue(void);
/*
* Returns true if replay module is processing
* reverse_continue or reverse_step request
*/
bool replay_running_debug(void);
/* Called in reverse debugging mode to collect breakpoint information */
void replay_breakpoint(void);
/* Called when gdb is attached to gdbstub */
void replay_gdb_attached(void);
/* Interrupts and exceptions */
/* Called by exception handler to write or read exception processing events */
bool replay_exception(void);
/*
* Used to determine that exception is pending.
* Does not proceed to the next event in the log.
*/
bool replay_has_exception(void);
/*
* Called by interrupt handlers to write or read interrupt processing events.
* Returns true if interrupt should be processed.
*/
bool replay_interrupt(void);
/*
* Tries to read interrupt event from the file.
* Returns true, when interrupt request is pending.
*/
bool replay_has_interrupt(void);
/* Processing data from random generators */
/* Saves the values from the random number generator */
void replay_save_random(int ret, void *buf, size_t len);
/* Loads the saved values for the random number generator */
int replay_read_random(void *buf, size_t len);
#endif

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