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https://gitlab.com/qemu-project/qemu
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intc: make HMP 'info irq' and 'info pic' commands use InterruptStatsProvider interface
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <1474921408-24710-6-git-send-email-hpoussin@reactos.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
7c468ec54c
commit
61b97833b3
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@ -179,13 +179,7 @@ ETEXI
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.args_type = "",
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.params = "",
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.help = "show the interrupts statistics (if available)",
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#ifdef TARGET_SPARC
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.cmd = sun4m_hmp_info_irq,
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#elif defined(TARGET_LM32)
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.cmd = lm32_hmp_info_irq,
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#else
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.cmd = hmp_info_irq,
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#endif
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},
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STEXI
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@ -199,13 +193,7 @@ ETEXI
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.args_type = "",
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.params = "",
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.help = "show i8259 (PIC) state",
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#ifdef TARGET_SPARC
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.cmd = sun4m_hmp_info_pic,
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#elif defined(TARGET_LM32)
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.cmd = lm32_hmp_info_pic,
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#else
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.cmd = hmp_info_pic,
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#endif
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},
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#endif
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65
hmp.c
65
hmp.c
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@ -36,6 +36,7 @@
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#include "qemu-io.h"
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#include "qemu/cutils.h"
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#include "qemu/error-report.h"
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#include "hw/intc/intc.h"
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#ifdef CONFIG_SPICE
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#include <spice/enums.h>
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@ -787,6 +788,70 @@ static void hmp_info_pci_device(Monitor *mon, const PciDeviceInfo *dev)
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}
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}
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static int hmp_info_irq_foreach(Object *obj, void *opaque)
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{
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InterruptStatsProvider *intc;
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InterruptStatsProviderClass *k;
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Monitor *mon = opaque;
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if (object_dynamic_cast(obj, TYPE_INTERRUPT_STATS_PROVIDER)) {
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intc = INTERRUPT_STATS_PROVIDER(obj);
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k = INTERRUPT_STATS_PROVIDER_GET_CLASS(obj);
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uint64_t *irq_counts;
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unsigned int nb_irqs, i;
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if (k->get_statistics &&
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k->get_statistics(intc, &irq_counts, &nb_irqs)) {
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if (nb_irqs > 0) {
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monitor_printf(mon, "IRQ statistics for %s:\n",
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object_get_typename(obj));
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for (i = 0; i < nb_irqs; i++) {
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if (irq_counts[i] > 0) {
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monitor_printf(mon, "%2d: %" PRId64 "\n", i,
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irq_counts[i]);
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}
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}
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}
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} else {
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monitor_printf(mon, "IRQ statistics not available for %s.\n",
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object_get_typename(obj));
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}
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}
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return 0;
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}
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void hmp_info_irq(Monitor *mon, const QDict *qdict)
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{
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object_child_foreach_recursive(object_get_root(),
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hmp_info_irq_foreach, mon);
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}
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static int hmp_info_pic_foreach(Object *obj, void *opaque)
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{
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InterruptStatsProvider *intc;
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InterruptStatsProviderClass *k;
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Monitor *mon = opaque;
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if (object_dynamic_cast(obj, TYPE_INTERRUPT_STATS_PROVIDER)) {
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intc = INTERRUPT_STATS_PROVIDER(obj);
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k = INTERRUPT_STATS_PROVIDER_GET_CLASS(obj);
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if (k->print_info) {
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k->print_info(intc, mon);
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} else {
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monitor_printf(mon, "Interrupt controller information not available for %s.\n",
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object_get_typename(obj));
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}
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}
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return 0;
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}
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void hmp_info_pic(Monitor *mon, const QDict *qdict)
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{
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object_child_foreach_recursive(object_get_root(),
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hmp_info_pic_foreach, mon);
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}
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void hmp_info_pci(Monitor *mon, const QDict *qdict)
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{
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PciInfoList *info_list, *info;
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2
hmp.h
2
hmp.h
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@ -36,6 +36,8 @@ void hmp_info_blockstats(Monitor *mon, const QDict *qdict);
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void hmp_info_vnc(Monitor *mon, const QDict *qdict);
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void hmp_info_spice(Monitor *mon, const QDict *qdict);
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void hmp_info_balloon(Monitor *mon, const QDict *qdict);
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void hmp_info_irq(Monitor *mon, const QDict *qdict);
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void hmp_info_pic(Monitor *mon, const QDict *qdict);
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void hmp_info_pci(Monitor *mon, const QDict *qdict);
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void hmp_info_block_jobs(Monitor *mon, const QDict *qdict);
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void hmp_info_tpm(Monitor *mon, const QDict *qdict);
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@ -461,42 +461,6 @@ static void pic_realize(DeviceState *dev, Error **errp)
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pc->parent_realize(dev, errp);
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}
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void hmp_info_pic(Monitor *mon, const QDict *qdict)
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{
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int i;
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PICCommonState *s;
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if (!isa_pic) {
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return;
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}
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for (i = 0; i < 2; i++) {
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s = i == 0 ? PIC_COMMON(isa_pic) : slave_pic;
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monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
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"irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
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i, s->irr, s->imr, s->isr, s->priority_add,
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s->irq_base, s->read_reg_select, s->elcr,
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s->special_fully_nested_mode);
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}
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}
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void hmp_info_irq(Monitor *mon, const QDict *qdict)
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{
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#ifndef DEBUG_IRQ_COUNT
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monitor_printf(mon, "irq statistic code not compiled.\n");
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#else
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int i;
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int64_t count;
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monitor_printf(mon, "IRQ statistics:\n");
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for (i = 0; i < 16; i++) {
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count = irq_count[i];
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if (count > 0) {
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monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
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}
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}
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#endif
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}
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qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
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{
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qemu_irq *irq_set;
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@ -43,35 +43,6 @@ struct LM32PicState {
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};
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typedef struct LM32PicState LM32PicState;
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static LM32PicState *pic;
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void lm32_hmp_info_pic(Monitor *mon, const QDict *qdict)
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{
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if (pic == NULL) {
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return;
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}
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monitor_printf(mon, "lm32-pic: im=%08x ip=%08x irq_state=%08x\n",
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pic->im, pic->ip, pic->irq_state);
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}
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void lm32_hmp_info_irq(Monitor *mon, const QDict *qdict)
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{
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int i;
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uint32_t count;
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if (pic == NULL) {
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return;
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}
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monitor_printf(mon, "IRQ statistics:\n");
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for (i = 0; i < 32; i++) {
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count = pic->stats_irq_count[i];
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if (count > 0) {
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monitor_printf(mon, "%2d: %u\n", i, count);
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}
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}
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}
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static void update_irq(LM32PicState *s)
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{
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s->ip |= s->irq_state;
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@ -177,8 +148,6 @@ static void lm32_pic_init(Object *obj)
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qdev_init_gpio_in(dev, irq_handler, 32);
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sysbus_init_irq(sbd, &s->parent_irq);
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pic = s;
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}
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static const VMStateDescription vmstate_lm32_pic = {
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@ -211,38 +211,6 @@ static const MemoryRegionOps slavio_intctlm_mem_ops = {
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},
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};
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void slavio_pic_info(Monitor *mon, DeviceState *dev)
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{
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SLAVIO_INTCTLState *s = SLAVIO_INTCTL(dev);
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int i;
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for (i = 0; i < MAX_CPUS; i++) {
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monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
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s->slaves[i].intreg_pending);
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}
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monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
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s->intregm_pending, s->intregm_disabled);
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}
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void slavio_irq_info(Monitor *mon, DeviceState *dev)
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{
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#ifndef DEBUG_IRQ_COUNT
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monitor_printf(mon, "irq statistic code not compiled.\n");
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#else
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SLAVIO_INTCTLState *s = SLAVIO_INTCTL(dev);
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int i;
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int64_t count;
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s = SLAVIO_INTCTL(dev);
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monitor_printf(mon, "IRQ statistics:\n");
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for (i = 0; i < 32; i++) {
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count = s->irq_count[i];
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if (count > 0)
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monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
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}
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#endif
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}
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static const uint32_t intbit_to_level[] = {
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2, 3, 5, 7, 9, 11, 13, 2, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 13, 4, 10, 8, 9, 11, 0, 0, 0, 0, 15, 15, 15, 15, 0,
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@ -159,20 +159,6 @@ static void nvram_init(Nvram *nvram, uint8_t *macaddr,
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}
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}
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static DeviceState *slavio_intctl;
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void sun4m_hmp_info_pic(Monitor *mon, const QDict *qdict)
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{
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if (slavio_intctl)
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slavio_pic_info(mon, slavio_intctl);
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}
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void sun4m_hmp_info_irq(Monitor *mon, const QDict *qdict)
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{
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if (slavio_intctl)
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slavio_irq_info(mon, slavio_intctl);
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}
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void cpu_check_irqs(CPUSPARCState *env)
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{
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CPUState *cs;
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@ -873,6 +859,7 @@ static void dummy_fdc_tc(void *opaque, int irq, int level)
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static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
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MachineState *machine)
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{
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DeviceState *slavio_intctl;
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const char *cpu_model = machine->cpu_model;
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unsigned int i;
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void *iommu, *espdma, *ledma, *nvram;
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@ -181,8 +181,6 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
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qemu_irq *kvm_i8259_init(ISABus *bus);
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int pic_read_irq(DeviceState *d);
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int pic_get_output(DeviceState *d);
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void hmp_info_pic(Monitor *mon, const QDict *qdict);
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void hmp_info_irq(Monitor *mon, const QDict *qdict);
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/* ioapic.c */
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@ -8,7 +8,4 @@ uint32_t lm32_pic_get_im(DeviceState *d);
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void lm32_pic_set_ip(DeviceState *d, uint32_t ip);
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void lm32_pic_set_im(DeviceState *d, uint32_t im);
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void lm32_hmp_info_pic(Monitor *mon, const QDict *qdict);
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void lm32_hmp_info_irq(Monitor *mon, const QDict *qdict);
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#endif /* QEMU_HW_LM32_PIC_H */
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@ -24,14 +24,6 @@ static inline void sparc_iommu_memory_write(void *opaque,
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sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
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}
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/* slavio_intctl.c */
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void slavio_pic_info(Monitor *mon, DeviceState *dev);
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void slavio_irq_info(Monitor *mon, DeviceState *dev);
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/* sun4m.c */
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void sun4m_hmp_info_pic(Monitor *mon, const QDict *qdict);
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void sun4m_hmp_info_irq(Monitor *mon, const QDict *qdict);
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/* sparc32_dma.c */
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#include "hw/sparc/sparc32_dma.h"
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