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ioh3420: support aer
Add aer support. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
parent
d33d9156fd
commit
61620c2fff
80
hw/ioh3420.c
80
hw/ioh3420.c
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@ -36,25 +36,59 @@
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#define IOH_EP_EXP_OFFSET 0x90
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#define IOH_EP_AER_OFFSET 0x100
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/*
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* If two MSI vector are allocated, Advanced Error Interrupt Message Number
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* is 1. otherwise 0.
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* 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number.
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*/
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static uint8_t ioh3420_aer_vector(const PCIDevice *d)
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{
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switch (msi_nr_vectors_allocated(d)) {
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case 1:
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return 0;
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case 2:
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return 1;
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case 4:
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case 8:
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case 16:
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case 32:
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default:
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break;
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}
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abort();
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return 0;
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}
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static void ioh3420_aer_vector_update(PCIDevice *d)
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{
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pcie_aer_root_set_vector(d, ioh3420_aer_vector(d));
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}
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static void ioh3420_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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uint32_t root_cmd =
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pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
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pci_bridge_write_config(d, address, val, len);
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msi_write_config(d, address, val, len);
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ioh3420_aer_vector_update(d);
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pcie_cap_slot_write_config(d, address, val, len);
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/* TODO: AER */
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pcie_aer_write_config(d, address, val, len);
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pcie_aer_root_write_config(d, address, val, len, root_cmd);
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}
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static void ioh3420_reset(DeviceState *qdev)
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{
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PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
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msi_reset(d);
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ioh3420_aer_vector_update(d);
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pcie_cap_root_reset(d);
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pcie_cap_deverr_reset(d);
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pcie_cap_slot_reset(d);
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pcie_aer_root_reset(d);
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pci_bridge_reset(qdev);
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pci_bridge_disable_base_limit(d);
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/* TODO: AER */
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}
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static int ioh3420_initfn(PCIDevice *d)
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@ -63,6 +97,7 @@ static int ioh3420_initfn(PCIDevice *d)
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PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
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PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
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int rc;
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int tmp;
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rc = pci_bridge_initfn(d);
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if (rc < 0) {
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@ -78,35 +113,57 @@ static int ioh3420_initfn(PCIDevice *d)
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rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
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IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
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if (rc < 0) {
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return rc;
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goto err_bridge;
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}
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rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
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IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
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IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
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if (rc < 0) {
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return rc;
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goto err_bridge;
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}
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rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port);
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if (rc < 0) {
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return rc;
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goto err_msi;
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}
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pcie_cap_deverr_init(d);
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pcie_cap_slot_init(d, s->slot);
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pcie_chassis_create(s->chassis);
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rc = pcie_chassis_add_slot(s);
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if (rc < 0) {
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goto err_pcie_cap;
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return rc;
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}
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pcie_cap_root_init(d);
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/* TODO: AER */
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rc = pcie_aer_init(d, IOH_EP_AER_OFFSET);
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if (rc < 0) {
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goto err;
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}
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pcie_aer_root_init(d);
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ioh3420_aer_vector_update(d);
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return 0;
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err:
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pcie_chassis_del_slot(s);
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err_pcie_cap:
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pcie_cap_exit(d);
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err_msi:
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msi_uninit(d);
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err_bridge:
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tmp = pci_bridge_exitfn(d);
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assert(!tmp);
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return rc;
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}
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static int ioh3420_exitfn(PCIDevice *d)
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{
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/* TODO: AER */
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msi_uninit(d);
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PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
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PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
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PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
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pcie_aer_exit(d);
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pcie_chassis_del_slot(s);
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pcie_cap_exit(d);
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msi_uninit(d);
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return pci_bridge_exitfn(d);
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}
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@ -142,7 +199,8 @@ static const VMStateDescription vmstate_ioh3420 = {
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.post_load = pcie_cap_slot_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
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/* TODO: AER */
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VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
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vmstate_pcie_aer_log, PCIEAERLog),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -164,7 +222,9 @@ static PCIDeviceInfo ioh3420_info = {
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DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
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DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
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DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
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/* TODO: AER */
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DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
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port.br.dev.exp.aer_log.log_max,
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PCIE_AER_LOG_MAX_DEFAULT),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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