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tcg: Add gvec expanders for variable shift
The gvec expanders perform a modulo on the shift count. If the target requires alternate behaviour, then it cannot use the generic gvec expanders anyway, and will have to have its own custom code. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
37ee55a081
commit
5ee5c14cac
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@ -725,6 +725,150 @@ void HELPER(gvec_sar64i)(void *d, void *a, uint32_t desc)
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_shl8v)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
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uint8_t sh = *(uint8_t *)(b + i) & 7;
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*(uint8_t *)(d + i) = *(uint8_t *)(a + i) << sh;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_shl16v)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
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uint8_t sh = *(uint16_t *)(b + i) & 15;
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*(uint16_t *)(d + i) = *(uint16_t *)(a + i) << sh;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_shl32v)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
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uint8_t sh = *(uint32_t *)(b + i) & 31;
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*(uint32_t *)(d + i) = *(uint32_t *)(a + i) << sh;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_shl64v)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
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uint8_t sh = *(uint64_t *)(b + i) & 63;
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*(uint64_t *)(d + i) = *(uint64_t *)(a + i) << sh;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_shr8v)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
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uint8_t sh = *(uint8_t *)(b + i) & 7;
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*(uint8_t *)(d + i) = *(uint8_t *)(a + i) >> sh;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_shr16v)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
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uint8_t sh = *(uint16_t *)(b + i) & 15;
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*(uint16_t *)(d + i) = *(uint16_t *)(a + i) >> sh;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_shr32v)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
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uint8_t sh = *(uint32_t *)(b + i) & 31;
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*(uint32_t *)(d + i) = *(uint32_t *)(a + i) >> sh;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_shr64v)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
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uint8_t sh = *(uint64_t *)(b + i) & 63;
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*(uint64_t *)(d + i) = *(uint64_t *)(a + i) >> sh;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_sar8v)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(vec8)) {
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uint8_t sh = *(uint8_t *)(b + i) & 7;
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*(int8_t *)(d + i) = *(int8_t *)(a + i) >> sh;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_sar16v)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(int16_t)) {
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uint8_t sh = *(uint16_t *)(b + i) & 15;
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*(int16_t *)(d + i) = *(int16_t *)(a + i) >> sh;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_sar32v)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(vec32)) {
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uint8_t sh = *(uint32_t *)(b + i) & 31;
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*(int32_t *)(d + i) = *(int32_t *)(a + i) >> sh;
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}
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clear_high(d, oprsz, desc);
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}
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void HELPER(gvec_sar64v)(void *d, void *a, void *b, uint32_t desc)
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{
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intptr_t oprsz = simd_oprsz(desc);
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intptr_t i;
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for (i = 0; i < oprsz; i += sizeof(vec64)) {
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uint8_t sh = *(uint64_t *)(b + i) & 63;
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*(int64_t *)(d + i) = *(int64_t *)(a + i) >> sh;
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}
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clear_high(d, oprsz, desc);
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}
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/* If vectors are enabled, the compiler fills in -1 for true.
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Otherwise, we must take care of this by hand. */
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#ifdef CONFIG_VECTOR16
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@ -254,6 +254,21 @@ DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_shl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_shl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_shl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_shl64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_shr8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_shr16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_shr32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_shr64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_sar8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_sar16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_sar32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_sar64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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@ -2555,6 +2555,201 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
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}
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}
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/*
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* Expand D = A << (B % element bits)
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*
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* Unlike scalar shifts, where it is easy for the target front end
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* to include the modulo as part of the expansion. If the target
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* naturally includes the modulo as part of the operation, great!
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* If the target has some other behaviour from out-of-range shifts,
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* then it could not use this function anyway, and would need to
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* do it's own expansion with custom functions.
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*/
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static void tcg_gen_shlv_mod_vec(unsigned vece, TCGv_vec d,
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TCGv_vec a, TCGv_vec b)
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{
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TCGv_vec t = tcg_temp_new_vec_matching(d);
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tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
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tcg_gen_and_vec(vece, t, t, b);
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tcg_gen_shlv_vec(vece, d, a, t);
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tcg_temp_free_vec(t);
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}
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static void tcg_gen_shl_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
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{
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TCGv_i32 t = tcg_temp_new_i32();
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tcg_gen_andi_i32(t, b, 31);
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tcg_gen_shl_i32(d, a, t);
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tcg_temp_free_i32(t);
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}
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static void tcg_gen_shl_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
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{
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TCGv_i64 t = tcg_temp_new_i64();
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tcg_gen_andi_i64(t, b, 63);
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tcg_gen_shl_i64(d, a, t);
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tcg_temp_free_i64(t);
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}
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void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs,
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uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
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{
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static const TCGOpcode vecop_list[] = { INDEX_op_shlv_vec, 0 };
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static const GVecGen3 g[4] = {
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{ .fniv = tcg_gen_shlv_mod_vec,
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.fno = gen_helper_gvec_shl8v,
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.opt_opc = vecop_list,
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.vece = MO_8 },
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{ .fniv = tcg_gen_shlv_mod_vec,
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.fno = gen_helper_gvec_shl16v,
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.opt_opc = vecop_list,
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.vece = MO_16 },
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{ .fni4 = tcg_gen_shl_mod_i32,
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.fniv = tcg_gen_shlv_mod_vec,
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.fno = gen_helper_gvec_shl32v,
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.opt_opc = vecop_list,
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.vece = MO_32 },
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{ .fni8 = tcg_gen_shl_mod_i64,
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.fniv = tcg_gen_shlv_mod_vec,
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.fno = gen_helper_gvec_shl64v,
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.opt_opc = vecop_list,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.vece = MO_64 },
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};
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tcg_debug_assert(vece <= MO_64);
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tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
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}
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/*
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* Similarly for logical right shifts.
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*/
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static void tcg_gen_shrv_mod_vec(unsigned vece, TCGv_vec d,
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TCGv_vec a, TCGv_vec b)
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{
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TCGv_vec t = tcg_temp_new_vec_matching(d);
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tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
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tcg_gen_and_vec(vece, t, t, b);
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tcg_gen_shrv_vec(vece, d, a, t);
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tcg_temp_free_vec(t);
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}
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static void tcg_gen_shr_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
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{
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TCGv_i32 t = tcg_temp_new_i32();
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tcg_gen_andi_i32(t, b, 31);
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tcg_gen_shr_i32(d, a, t);
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tcg_temp_free_i32(t);
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}
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static void tcg_gen_shr_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
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{
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TCGv_i64 t = tcg_temp_new_i64();
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tcg_gen_andi_i64(t, b, 63);
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tcg_gen_shr_i64(d, a, t);
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tcg_temp_free_i64(t);
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}
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void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,
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uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
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{
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static const TCGOpcode vecop_list[] = { INDEX_op_shrv_vec, 0 };
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static const GVecGen3 g[4] = {
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{ .fniv = tcg_gen_shrv_mod_vec,
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.fno = gen_helper_gvec_shr8v,
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.opt_opc = vecop_list,
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.vece = MO_8 },
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{ .fniv = tcg_gen_shrv_mod_vec,
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.fno = gen_helper_gvec_shr16v,
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.opt_opc = vecop_list,
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.vece = MO_16 },
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{ .fni4 = tcg_gen_shr_mod_i32,
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.fniv = tcg_gen_shrv_mod_vec,
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.fno = gen_helper_gvec_shr32v,
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.opt_opc = vecop_list,
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.vece = MO_32 },
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{ .fni8 = tcg_gen_shr_mod_i64,
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.fniv = tcg_gen_shrv_mod_vec,
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.fno = gen_helper_gvec_shr64v,
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.opt_opc = vecop_list,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.vece = MO_64 },
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};
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tcg_debug_assert(vece <= MO_64);
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tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
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}
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/*
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* Similarly for arithmetic right shifts.
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*/
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static void tcg_gen_sarv_mod_vec(unsigned vece, TCGv_vec d,
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TCGv_vec a, TCGv_vec b)
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{
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TCGv_vec t = tcg_temp_new_vec_matching(d);
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tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
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tcg_gen_and_vec(vece, t, t, b);
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tcg_gen_sarv_vec(vece, d, a, t);
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tcg_temp_free_vec(t);
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}
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static void tcg_gen_sar_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
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{
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TCGv_i32 t = tcg_temp_new_i32();
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tcg_gen_andi_i32(t, b, 31);
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tcg_gen_sar_i32(d, a, t);
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tcg_temp_free_i32(t);
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}
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static void tcg_gen_sar_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
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{
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TCGv_i64 t = tcg_temp_new_i64();
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tcg_gen_andi_i64(t, b, 63);
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tcg_gen_sar_i64(d, a, t);
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tcg_temp_free_i64(t);
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}
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void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,
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uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
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{
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static const TCGOpcode vecop_list[] = { INDEX_op_sarv_vec, 0 };
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static const GVecGen3 g[4] = {
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{ .fniv = tcg_gen_sarv_mod_vec,
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.fno = gen_helper_gvec_sar8v,
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.opt_opc = vecop_list,
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.vece = MO_8 },
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{ .fniv = tcg_gen_sarv_mod_vec,
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.fno = gen_helper_gvec_sar16v,
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.opt_opc = vecop_list,
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.vece = MO_16 },
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{ .fni4 = tcg_gen_sar_mod_i32,
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.fniv = tcg_gen_sarv_mod_vec,
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.fno = gen_helper_gvec_sar32v,
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.opt_opc = vecop_list,
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.vece = MO_32 },
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{ .fni8 = tcg_gen_sar_mod_i64,
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.fniv = tcg_gen_sarv_mod_vec,
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.fno = gen_helper_gvec_sar64v,
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.opt_opc = vecop_list,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.vece = MO_64 },
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};
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tcg_debug_assert(vece <= MO_64);
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tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
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}
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/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
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static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
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uint32_t oprsz, TCGCond cond)
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|
@ -318,6 +318,17 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
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void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
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||||
int64_t shift, uint32_t oprsz, uint32_t maxsz);
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||||
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/*
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* Perform vector shift by vector element, modulo the element size.
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* E.g. D[i] = A[i] << (B[i] % (8 << vece)).
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*/
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void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs,
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||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
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||||
void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,
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||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
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||||
void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
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||||
|
||||
void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
|
||||
uint32_t aofs, uint32_t bofs,
|
||||
uint32_t oprsz, uint32_t maxsz);
|
||||
|
|
|
@ -583,3 +583,18 @@ void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
|||
{
|
||||
do_op3(vece, r, a, b, INDEX_op_umax_vec);
|
||||
}
|
||||
|
||||
void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
do_op3(vece, r, a, b, INDEX_op_shlv_vec);
|
||||
}
|
||||
|
||||
void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
do_op3(vece, r, a, b, INDEX_op_shrv_vec);
|
||||
}
|
||||
|
||||
void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
do_op3(vece, r, a, b, INDEX_op_sarv_vec);
|
||||
}
|
||||
|
|
|
@ -986,6 +986,10 @@ void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
|
|||
void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
|
||||
void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
|
||||
|
||||
void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
|
||||
void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
|
||||
void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
|
||||
|
||||
void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
|
||||
TCGv_vec a, TCGv_vec b);
|
||||
|
||||
|
|
Loading…
Reference in a new issue