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https://gitlab.com/qemu-project/qemu
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exec: return MemoryRegion from address_space_translate
Only address_space_translate_for_iotlb needs to return the section. Every caller of address_space_translate now uses only section->mr, return it directly. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
acc9d80b26
commit
5c8a00ce18
150
exec.c
150
exec.c
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@ -262,11 +262,11 @@ address_space_translate_internal(AddressSpace *as, hwaddr addr, hwaddr *xlat,
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return section;
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}
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MemoryRegionSection *address_space_translate(AddressSpace *as, hwaddr addr,
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hwaddr *xlat, hwaddr *plen,
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bool is_write)
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MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
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hwaddr *xlat, hwaddr *plen,
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bool is_write)
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{
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return address_space_translate_internal(as, addr, xlat, plen, true);
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return address_space_translate_internal(as, addr, xlat, plen, true)->mr;
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}
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MemoryRegionSection *
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@ -1923,58 +1923,58 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
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uint8_t *ptr;
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uint64_t val;
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hwaddr addr1;
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MemoryRegionSection *section;
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MemoryRegion *mr;
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bool error = false;
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while (len > 0) {
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l = len;
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section = address_space_translate(as, addr, &addr1, &l, is_write);
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mr = address_space_translate(as, addr, &addr1, &l, is_write);
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if (is_write) {
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if (!memory_access_is_direct(section->mr, is_write)) {
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l = memory_access_size(section->mr, l, addr1);
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if (!memory_access_is_direct(mr, is_write)) {
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l = memory_access_size(mr, l, addr1);
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/* XXX: could force cpu_single_env to NULL to avoid
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potential bugs */
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if (l == 4) {
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/* 32 bit write access */
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val = ldl_p(buf);
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error |= io_mem_write(section->mr, addr1, val, 4);
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error |= io_mem_write(mr, addr1, val, 4);
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} else if (l == 2) {
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/* 16 bit write access */
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val = lduw_p(buf);
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error |= io_mem_write(section->mr, addr1, val, 2);
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error |= io_mem_write(mr, addr1, val, 2);
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} else {
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/* 8 bit write access */
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val = ldub_p(buf);
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error |= io_mem_write(section->mr, addr1, val, 1);
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error |= io_mem_write(mr, addr1, val, 1);
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}
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} else {
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addr1 += memory_region_get_ram_addr(section->mr);
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addr1 += memory_region_get_ram_addr(mr);
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/* RAM case */
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ptr = qemu_get_ram_ptr(addr1);
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memcpy(ptr, buf, l);
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invalidate_and_set_dirty(addr1, l);
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}
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} else {
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if (!memory_access_is_direct(section->mr, is_write)) {
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if (!memory_access_is_direct(mr, is_write)) {
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/* I/O case */
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l = memory_access_size(section->mr, l, addr1);
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l = memory_access_size(mr, l, addr1);
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if (l == 4) {
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/* 32 bit read access */
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error |= io_mem_read(section->mr, addr1, &val, 4);
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error |= io_mem_read(mr, addr1, &val, 4);
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stl_p(buf, val);
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} else if (l == 2) {
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/* 16 bit read access */
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error |= io_mem_read(section->mr, addr1, &val, 2);
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error |= io_mem_read(mr, addr1, &val, 2);
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stw_p(buf, val);
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} else {
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/* 8 bit read access */
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error |= io_mem_read(section->mr, addr1, &val, 1);
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error |= io_mem_read(mr, addr1, &val, 1);
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stb_p(buf, val);
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}
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} else {
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/* RAM case */
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ptr = qemu_get_ram_ptr(section->mr->ram_addr + addr1);
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ptr = qemu_get_ram_ptr(mr->ram_addr + addr1);
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memcpy(buf, ptr, l);
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}
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}
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@ -2011,18 +2011,18 @@ void cpu_physical_memory_write_rom(hwaddr addr,
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hwaddr l;
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uint8_t *ptr;
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hwaddr addr1;
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MemoryRegionSection *section;
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MemoryRegion *mr;
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while (len > 0) {
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l = len;
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section = address_space_translate(&address_space_memory,
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addr, &addr1, &l, true);
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mr = address_space_translate(&address_space_memory,
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addr, &addr1, &l, true);
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if (!(memory_region_is_ram(section->mr) ||
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memory_region_is_romd(section->mr))) {
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if (!(memory_region_is_ram(mr) ||
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memory_region_is_romd(mr))) {
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/* do nothing */
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} else {
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addr1 += memory_region_get_ram_addr(section->mr);
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addr1 += memory_region_get_ram_addr(mr);
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/* ROM/RAM case */
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ptr = qemu_get_ram_ptr(addr1);
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memcpy(ptr, buf, l);
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@ -2082,15 +2082,15 @@ static void cpu_notify_map_clients(void)
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bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write)
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{
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MemoryRegionSection *section;
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MemoryRegion *mr;
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hwaddr l, xlat;
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while (len > 0) {
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l = len;
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section = address_space_translate(as, addr, &xlat, &l, is_write);
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if (!memory_access_is_direct(section->mr, is_write)) {
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l = memory_access_size(section->mr, l, addr);
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if (!memory_region_access_valid(section->mr, xlat, l, is_write)) {
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mr = address_space_translate(as, addr, &xlat, &l, is_write);
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if (!memory_access_is_direct(mr, is_write)) {
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l = memory_access_size(mr, l, addr);
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if (!memory_region_access_valid(mr, xlat, l, is_write)) {
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return false;
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}
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}
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@ -2116,16 +2116,16 @@ void *address_space_map(AddressSpace *as,
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hwaddr len = *plen;
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hwaddr todo = 0;
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hwaddr l, xlat;
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MemoryRegionSection *section;
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MemoryRegion *mr;
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ram_addr_t raddr = RAM_ADDR_MAX;
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ram_addr_t rlen;
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void *ret;
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while (len > 0) {
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l = len;
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section = address_space_translate(as, addr, &xlat, &l, is_write);
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mr = address_space_translate(as, addr, &xlat, &l, is_write);
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if (!memory_access_is_direct(section->mr, is_write)) {
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if (!memory_access_is_direct(mr, is_write)) {
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if (todo || bounce.buffer) {
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break;
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}
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@ -2140,9 +2140,9 @@ void *address_space_map(AddressSpace *as,
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return bounce.buffer;
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}
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if (!todo) {
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raddr = memory_region_get_ram_addr(section->mr) + xlat;
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raddr = memory_region_get_ram_addr(mr) + xlat;
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} else {
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if (memory_region_get_ram_addr(section->mr) + xlat != raddr + todo) {
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if (memory_region_get_ram_addr(mr) + xlat != raddr + todo) {
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break;
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}
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}
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@ -2209,15 +2209,15 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegionSection *section;
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MemoryRegion *mr;
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hwaddr l = 4;
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hwaddr addr1;
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section = address_space_translate(&address_space_memory, addr, &addr1, &l,
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false);
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if (l < 4 || !memory_access_is_direct(section->mr, false)) {
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mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
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false);
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if (l < 4 || !memory_access_is_direct(mr, false)) {
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/* I/O case */
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io_mem_read(section->mr, addr1, &val, 4);
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io_mem_read(mr, addr1, &val, 4);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap32(val);
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@ -2229,7 +2229,7 @@ static inline uint32_t ldl_phys_internal(hwaddr addr,
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#endif
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} else {
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/* RAM case */
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ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section->mr)
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ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr)
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& TARGET_PAGE_MASK)
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+ addr1);
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switch (endian) {
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@ -2268,15 +2268,15 @@ static inline uint64_t ldq_phys_internal(hwaddr addr,
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegionSection *section;
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MemoryRegion *mr;
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hwaddr l = 8;
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hwaddr addr1;
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section = address_space_translate(&address_space_memory, addr, &addr1, &l,
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false);
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if (l < 8 || !memory_access_is_direct(section->mr, false)) {
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mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
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false);
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if (l < 8 || !memory_access_is_direct(mr, false)) {
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/* I/O case */
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io_mem_read(section->mr, addr1, &val, 8);
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io_mem_read(mr, addr1, &val, 8);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap64(val);
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@ -2288,7 +2288,7 @@ static inline uint64_t ldq_phys_internal(hwaddr addr,
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#endif
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} else {
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/* RAM case */
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ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section->mr)
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ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr)
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& TARGET_PAGE_MASK)
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+ addr1);
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switch (endian) {
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@ -2335,15 +2335,15 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegionSection *section;
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MemoryRegion *mr;
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hwaddr l = 2;
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hwaddr addr1;
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section = address_space_translate(&address_space_memory, addr, &addr1, &l,
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false);
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if (l < 2 || !memory_access_is_direct(section->mr, false)) {
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mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
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false);
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if (l < 2 || !memory_access_is_direct(mr, false)) {
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/* I/O case */
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io_mem_read(section->mr, addr1, &val, 2);
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io_mem_read(mr, addr1, &val, 2);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap16(val);
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@ -2355,7 +2355,7 @@ static inline uint32_t lduw_phys_internal(hwaddr addr,
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#endif
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} else {
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/* RAM case */
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ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(section->mr)
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ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr)
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& TARGET_PAGE_MASK)
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+ addr1);
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switch (endian) {
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@ -2394,16 +2394,16 @@ uint32_t lduw_be_phys(hwaddr addr)
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void stl_phys_notdirty(hwaddr addr, uint32_t val)
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{
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uint8_t *ptr;
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MemoryRegionSection *section;
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MemoryRegion *mr;
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hwaddr l = 4;
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hwaddr addr1;
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section = address_space_translate(&address_space_memory, addr, &addr1, &l,
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true);
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if (l < 4 || !memory_access_is_direct(section->mr, true)) {
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io_mem_write(section->mr, addr1, val, 4);
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mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
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true);
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if (l < 4 || !memory_access_is_direct(mr, true)) {
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io_mem_write(mr, addr1, val, 4);
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} else {
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addr1 += memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK;
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addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK;
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ptr = qemu_get_ram_ptr(addr1);
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stl_p(ptr, val);
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@ -2424,13 +2424,13 @@ static inline void stl_phys_internal(hwaddr addr, uint32_t val,
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enum device_endian endian)
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{
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uint8_t *ptr;
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MemoryRegionSection *section;
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MemoryRegion *mr;
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hwaddr l = 4;
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hwaddr addr1;
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section = address_space_translate(&address_space_memory, addr, &addr1, &l,
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true);
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if (l < 4 || !memory_access_is_direct(section->mr, true)) {
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mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
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true);
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if (l < 4 || !memory_access_is_direct(mr, true)) {
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap32(val);
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@ -2440,10 +2440,10 @@ static inline void stl_phys_internal(hwaddr addr, uint32_t val,
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val = bswap32(val);
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}
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#endif
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io_mem_write(section->mr, addr1, val, 4);
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io_mem_write(mr, addr1, val, 4);
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} else {
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/* RAM case */
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addr1 += memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK;
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addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK;
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ptr = qemu_get_ram_ptr(addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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@ -2487,13 +2487,13 @@ static inline void stw_phys_internal(hwaddr addr, uint32_t val,
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enum device_endian endian)
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{
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uint8_t *ptr;
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MemoryRegionSection *section;
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MemoryRegion *mr;
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hwaddr l = 2;
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hwaddr addr1;
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section = address_space_translate(&address_space_memory, addr, &addr1, &l,
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true);
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if (l < 2 || !memory_access_is_direct(section->mr, true)) {
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mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
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true);
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if (l < 2 || !memory_access_is_direct(mr, true)) {
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap16(val);
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@ -2503,10 +2503,10 @@ static inline void stw_phys_internal(hwaddr addr, uint32_t val,
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val = bswap16(val);
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}
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#endif
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io_mem_write(section->mr, addr1, val, 2);
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io_mem_write(mr, addr1, val, 2);
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} else {
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/* RAM case */
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addr1 += memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK;
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addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK;
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ptr = qemu_get_ram_ptr(addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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@ -2608,13 +2608,13 @@ bool virtio_is_big_endian(void)
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#ifndef CONFIG_USER_ONLY
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bool cpu_physical_memory_is_io(hwaddr phys_addr)
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{
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MemoryRegionSection *section;
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MemoryRegion*mr;
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hwaddr l = 1;
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section = address_space_translate(&address_space_memory,
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phys_addr, &phys_addr, &l, false);
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mr = address_space_translate(&address_space_memory,
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phys_addr, &phys_addr, &l, false);
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return !(memory_region_is_ram(section->mr) ||
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memory_region_is_romd(section->mr));
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return !(memory_region_is_ram(mr) ||
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memory_region_is_romd(mr));
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}
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#endif
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@ -859,7 +859,7 @@ bool address_space_write(AddressSpace *as, hwaddr addr,
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bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len);
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/* address_space_translate: translate an address range into an address space
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* into a MemoryRegionSection and an address range into that section
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* into a MemoryRegion and an address range into that section
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*
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* @as: #AddressSpace to be accessed
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* @addr: address within that address space
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@ -868,9 +868,9 @@ bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len);
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* @len: pointer to length
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* @is_write: indicates the transfer direction
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*/
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MemoryRegionSection *address_space_translate(AddressSpace *as, hwaddr addr,
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hwaddr *xlat, hwaddr *len,
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bool is_write);
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MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
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hwaddr *xlat, hwaddr *len,
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bool is_write);
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/* address_space_access_valid: check for validity of accessing an address
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* space range
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|
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@ -1355,15 +1355,15 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
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void tb_invalidate_phys_addr(hwaddr addr)
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{
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ram_addr_t ram_addr;
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MemoryRegionSection *section;
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MemoryRegion *mr;
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hwaddr l = 1;
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section = address_space_translate(&address_space_memory, addr, &addr, &l, false);
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if (!(memory_region_is_ram(section->mr)
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|| memory_region_is_romd(section->mr))) {
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mr = address_space_translate(&address_space_memory, addr, &addr, &l, false);
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||||
if (!(memory_region_is_ram(mr)
|
||||
|| memory_region_is_romd(mr))) {
|
||||
return;
|
||||
}
|
||||
ram_addr = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
|
||||
ram_addr = (memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK)
|
||||
+ addr;
|
||||
tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue