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tests/tcg/multiarch: Add sigbus.c
A mostly generic test for unaligned access raising SIGBUS. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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tests/tcg/multiarch/sigbus.c
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tests/tcg/multiarch/sigbus.c
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#define _GNU_SOURCE 1
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#include <assert.h>
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#include <stdlib.h>
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#include <signal.h>
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#include <endian.h>
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unsigned long long x = 0x8877665544332211ull;
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void * volatile p = (void *)&x + 1;
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void sigbus(int sig, siginfo_t *info, void *uc)
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{
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assert(sig == SIGBUS);
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assert(info->si_signo == SIGBUS);
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#ifdef BUS_ADRALN
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assert(info->si_code == BUS_ADRALN);
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#endif
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assert(info->si_addr == p);
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exit(EXIT_SUCCESS);
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}
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int main()
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{
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struct sigaction sa = {
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.sa_sigaction = sigbus,
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.sa_flags = SA_SIGINFO
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};
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int allow_fail = 0;
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int tmp;
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tmp = sigaction(SIGBUS, &sa, NULL);
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assert(tmp == 0);
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/*
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* Select an operation that's likely to enforce alignment.
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* On many guests that support unaligned accesses by default,
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* this is often an atomic operation.
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*/
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#if defined(__aarch64__)
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asm volatile("ldxr %w0,[%1]" : "=r"(tmp) : "r"(p) : "memory");
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#elif defined(__alpha__)
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asm volatile("ldl_l %0,0(%1)" : "=r"(tmp) : "r"(p) : "memory");
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#elif defined(__arm__)
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asm volatile("ldrex %0,[%1]" : "=r"(tmp) : "r"(p) : "memory");
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#elif defined(__powerpc__)
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asm volatile("lwarx %0,0,%1" : "=r"(tmp) : "r"(p) : "memory");
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#elif defined(__riscv_atomic)
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asm volatile("lr.w %0,(%1)" : "=r"(tmp) : "r"(p) : "memory");
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#else
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/* No insn known to fault unaligned -- try for a straight load. */
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allow_fail = 1;
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tmp = *(volatile int *)p;
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#endif
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assert(allow_fail);
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/*
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* We didn't see a signal.
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* We might as well validate the unaligned load worked.
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*/
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if (BYTE_ORDER == LITTLE_ENDIAN) {
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assert(tmp == 0x55443322);
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} else {
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assert(tmp == 0x77665544);
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}
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return EXIT_SUCCESS;
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}
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