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https://gitlab.com/qemu-project/qemu
synced 2024-09-06 01:43:39 +00:00
mips: use MIPSCPU instead of CPUMIPSState
This changes a cpu.h dependency into a cpu-qom.h dependency. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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0774831d08
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@ -81,11 +81,12 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
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error_setg(errp, "%s: CPU initialization failed\n", __func__);
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return;
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}
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env = &cpu->env;
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/* Init internal devices */
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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cpu_mips_irq_init_cpu(cpu);
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cpu_mips_clock_init(cpu);
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env = &cpu->env;
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if (cpu_mips_itu_supported(env)) {
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itu_present = true;
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/* Attach ITC Tag to the VP */
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@ -151,8 +151,10 @@ static void mips_timer_cb (void *opaque)
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env->CP0_Count--;
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}
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void cpu_mips_clock_init (CPUMIPSState *env)
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void cpu_mips_clock_init (MIPSCPU *cpu)
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{
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CPUMIPSState *env = &cpu->env;
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/*
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* If we're in KVM mode, don't create the periodic timer, that is handled in
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* kernel.
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@ -334,8 +334,8 @@ static void mips_fulong2e_init(MachineState *machine)
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}
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/* Init internal devices */
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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cpu_mips_irq_init_cpu(cpu);
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cpu_mips_clock_init(cpu);
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/* North bridge, Bonito --> IP2 */
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pci_bus = bonito_init((qemu_irq *)&(env->irq[2]));
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@ -58,8 +58,9 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
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}
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}
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void cpu_mips_irq_init_cpu(CPUMIPSState *env)
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void cpu_mips_irq_init_cpu(MIPSCPU *cpu)
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{
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CPUMIPSState *env = &cpu->env;
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qemu_irq *qi;
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int i;
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@ -201,8 +201,8 @@ static void mips_jazz_init(MachineState *machine,
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}
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/* Init CPU internal devices */
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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cpu_mips_irq_init_cpu(cpu);
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cpu_mips_clock_init(cpu);
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/* Chipset */
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rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
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@ -923,11 +923,10 @@ static void create_cpu_without_cps(const char *cpu_model,
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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env = &cpu->env;
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/* Init internal devices */
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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cpu_mips_irq_init_cpu(cpu);
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cpu_mips_clock_init(cpu);
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qemu_register_reset(main_cpu_reset, cpu);
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}
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@ -216,8 +216,8 @@ mips_mipssim_init(MachineState *machine)
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}
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/* Init CPU internal devices. */
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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cpu_mips_irq_init_cpu(cpu);
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cpu_mips_clock_init(cpu);
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/* Register 64 KB of ISA IO space at 0x1fd00000. */
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memory_region_init_alias(isa, NULL, "isa_mmio",
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@ -267,8 +267,8 @@ void mips_r4k_init(MachineState *machine)
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}
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/* Init CPU internal devices */
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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cpu_mips_irq_init_cpu(cpu);
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cpu_mips_clock_init(cpu);
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/* ISA bus: IO space at 0x14000000, mem space at 0x10000000 */
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memory_region_init_alias(isa_io, NULL, "isa-io",
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@ -1,5 +1,8 @@
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#ifndef HW_MIPS_CPUDEVS_H
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#define HW_MIPS_CPUDEVS_H
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#include "target-mips/cpu-qom.h"
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/* Definitions for MIPS CPU internal devices. */
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/* mips_addr.c */
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@ -9,9 +12,9 @@ uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
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/* mips_int.c */
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void cpu_mips_irq_init_cpu(CPUMIPSState *env);
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void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
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/* mips_timer.c */
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void cpu_mips_clock_init(CPUMIPSState *);
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void cpu_mips_clock_init(MIPSCPU *cpu);
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#endif
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