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target-tricore: Add instructions of ABS, ABSB opcode format
Add instructions of ABS, ABSB opcode format. Add microcode generator functions for ld/st of two 32bit reg as one 64bit value. Add microcode generator functions for ldmst and swap. Add helper ldlcx, lducx, stlcx and stucx. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Bastian Koppelmann
parent
030c58dfb7
commit
59543d4ee1
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@ -23,3 +23,7 @@ DEF_HELPER_2(call, void, env, i32)
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DEF_HELPER_1(ret, void, env)
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DEF_HELPER_2(bisr, void, env, i32)
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DEF_HELPER_1(rfe, void, env)
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DEF_HELPER_2(ldlcx, void, env, i32)
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DEF_HELPER_2(lducx, void, env, i32)
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DEF_HELPER_2(stlcx, void, env, i32)
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DEF_HELPER_2(stucx, void, env, i32)
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@ -175,6 +175,27 @@ static void restore_context_upper(CPUTriCoreState *env, int ea,
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env->gpr_d[15] = cpu_ldl_data(env, ea+60);
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}
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static void restore_context_lower(CPUTriCoreState *env, int ea,
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target_ulong *ra, target_ulong *pcxi)
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{
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*pcxi = cpu_ldl_data(env, ea);
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*ra = cpu_ldl_data(env, ea+4);
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env->gpr_a[2] = cpu_ldl_data(env, ea+8);
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env->gpr_a[3] = cpu_ldl_data(env, ea+12);
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env->gpr_d[0] = cpu_ldl_data(env, ea+16);
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env->gpr_d[1] = cpu_ldl_data(env, ea+20);
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env->gpr_d[2] = cpu_ldl_data(env, ea+24);
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env->gpr_d[3] = cpu_ldl_data(env, ea+28);
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env->gpr_a[4] = cpu_ldl_data(env, ea+32);
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env->gpr_a[5] = cpu_ldl_data(env, ea+36);
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env->gpr_a[6] = cpu_ldl_data(env, ea+40);
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env->gpr_a[7] = cpu_ldl_data(env, ea+44);
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env->gpr_d[4] = cpu_ldl_data(env, ea+48);
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env->gpr_d[5] = cpu_ldl_data(env, ea+52);
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env->gpr_d[6] = cpu_ldl_data(env, ea+56);
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env->gpr_d[7] = cpu_ldl_data(env, ea+60);
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}
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void helper_call(CPUTriCoreState *env, uint32_t next_pc)
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{
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target_ulong tmp_FCX;
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@ -356,6 +377,30 @@ void helper_rfe(CPUTriCoreState *env)
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psw_write(env, new_PSW);
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}
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void helper_ldlcx(CPUTriCoreState *env, uint32_t ea)
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{
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uint32_t dummy;
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/* insn doesn't load PCXI and RA */
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restore_context_lower(env, ea, &dummy, &dummy);
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}
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void helper_lducx(CPUTriCoreState *env, uint32_t ea)
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{
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uint32_t dummy;
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/* insn doesn't load PCXI and PSW */
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restore_context_upper(env, ea, &dummy, &dummy);
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}
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void helper_stlcx(CPUTriCoreState *env, uint32_t ea)
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{
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save_context_lower(env, ea);
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}
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void helper_stucx(CPUTriCoreState *env, uint32_t ea)
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{
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save_context_upper(env, ea);
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}
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static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env,
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uint32_t exception,
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int error_code,
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@ -115,6 +115,8 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
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tcg_temp_free_i32(helper_tmp); \
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} while (0)
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#define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
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/* Functions for load/save to/from memory */
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static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
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@ -135,6 +137,62 @@ static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
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tcg_temp_free(temp);
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}
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static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
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{
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TCGv_i64 temp = tcg_temp_new_i64();
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tcg_gen_concat_i32_i64(temp, rl, rh);
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tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
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tcg_temp_free_i64(temp);
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}
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static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
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{
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TCGv_i64 temp = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
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/* write back to two 32 bit regs */
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tcg_gen_extr_i64_i32(rl, rh, temp);
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tcg_temp_free_i64(temp);
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}
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/* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
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static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
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{
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TCGv temp = tcg_temp_new();
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TCGv temp2 = tcg_temp_new();
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/* temp = (M(EA, word) */
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tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
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/* temp = temp & ~E[a][63:32]) */
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tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
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/* temp2 = (E[a][31:0] & E[a][63:32]); */
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tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
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/* temp = temp | temp2; */
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tcg_gen_or_tl(temp, temp, temp2);
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/* M(EA, word) = temp; */
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tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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}
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/* tmp = M(EA, word);
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M(EA, word) = D[a];
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D[a] = tmp[31:0];*/
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static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
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{
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TCGv temp = tcg_temp_new();
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tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
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tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
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tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
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tcg_temp_free(temp);
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}
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/* Functions for arithmetic instructions */
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static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
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@ -1099,8 +1157,253 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
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}
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}
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/*
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* 32 bit instructions
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*/
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/* ABS-format */
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static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
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{
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int32_t op2;
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int32_t r1;
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uint32_t address;
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TCGv temp;
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r1 = MASK_OP_ABS_S1D(ctx->opcode);
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address = MASK_OP_ABS_OFF18(ctx->opcode);
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op2 = MASK_OP_ABS_OP2(ctx->opcode);
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temp = tcg_const_i32(EA_ABS_FORMAT(address));
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switch (op2) {
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case OPC2_32_ABS_LD_A:
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tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
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break;
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case OPC2_32_ABS_LD_D:
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gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
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break;
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case OPC2_32_ABS_LD_DA:
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gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
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break;
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case OPC2_32_ABS_LD_W:
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tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
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break;
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}
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tcg_temp_free(temp);
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}
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static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
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{
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int32_t op2;
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int32_t r1;
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uint32_t address;
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TCGv temp;
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r1 = MASK_OP_ABS_S1D(ctx->opcode);
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address = MASK_OP_ABS_OFF18(ctx->opcode);
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op2 = MASK_OP_ABS_OP2(ctx->opcode);
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temp = tcg_const_i32(EA_ABS_FORMAT(address));
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switch (op2) {
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case OPC2_32_ABS_LD_B:
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tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
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break;
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case OPC2_32_ABS_LD_BU:
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tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
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break;
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case OPC2_32_ABS_LD_H:
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tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
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break;
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case OPC2_32_ABS_LD_HU:
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tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
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break;
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}
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tcg_temp_free(temp);
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}
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static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
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{
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int32_t op2;
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int32_t r1;
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uint32_t address;
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TCGv temp;
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r1 = MASK_OP_ABS_S1D(ctx->opcode);
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address = MASK_OP_ABS_OFF18(ctx->opcode);
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op2 = MASK_OP_ABS_OP2(ctx->opcode);
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temp = tcg_const_i32(EA_ABS_FORMAT(address));
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switch (op2) {
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case OPC2_32_ABS_LDMST:
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gen_ldmst(ctx, r1, temp);
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break;
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case OPC2_32_ABS_SWAP_W:
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gen_swap(ctx, r1, temp);
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break;
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}
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tcg_temp_free(temp);
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}
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static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
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{
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uint32_t op2;
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int32_t off18;
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off18 = MASK_OP_ABS_OFF18(ctx->opcode);
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op2 = MASK_OP_ABS_OP2(ctx->opcode);
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switch (op2) {
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case OPC2_32_ABS_LDLCX:
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gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
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break;
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case OPC2_32_ABS_LDUCX:
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gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
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break;
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case OPC2_32_ABS_STLCX:
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gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
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break;
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case OPC2_32_ABS_STUCX:
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gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
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break;
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}
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}
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static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
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{
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int32_t op2;
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int32_t r1;
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uint32_t address;
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TCGv temp;
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r1 = MASK_OP_ABS_S1D(ctx->opcode);
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address = MASK_OP_ABS_OFF18(ctx->opcode);
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op2 = MASK_OP_ABS_OP2(ctx->opcode);
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temp = tcg_const_i32(EA_ABS_FORMAT(address));
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switch (op2) {
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case OPC2_32_ABS_ST_A:
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tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
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break;
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case OPC2_32_ABS_ST_D:
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gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
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break;
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case OPC2_32_ABS_ST_DA:
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gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
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break;
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case OPC2_32_ABS_ST_W:
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tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
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break;
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}
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tcg_temp_free(temp);
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}
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static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
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{
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int32_t op2;
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int32_t r1;
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uint32_t address;
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TCGv temp;
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r1 = MASK_OP_ABS_S1D(ctx->opcode);
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address = MASK_OP_ABS_OFF18(ctx->opcode);
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op2 = MASK_OP_ABS_OP2(ctx->opcode);
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temp = tcg_const_i32(EA_ABS_FORMAT(address));
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switch (op2) {
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case OPC2_32_ABS_ST_B:
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tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
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break;
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case OPC2_32_ABS_ST_H:
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tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
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break;
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}
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tcg_temp_free(temp);
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}
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static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
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{
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int op1;
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int32_t r1;
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int32_t address;
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int8_t b;
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int32_t bpos;
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TCGv temp, temp2;
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op1 = MASK_OP_MAJOR(ctx->opcode);
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switch (op1) {
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/* ABS-format */
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case OPCM_32_ABS_LDW:
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decode_abs_ldw(env, ctx);
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break;
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case OPCM_32_ABS_LDB:
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decode_abs_ldb(env, ctx);
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break;
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case OPCM_32_ABS_LDMST_SWAP:
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decode_abs_ldst_swap(env, ctx);
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break;
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case OPCM_32_ABS_LDST_CONTEXT:
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decode_abs_ldst_context(env, ctx);
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break;
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case OPCM_32_ABS_STORE:
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decode_abs_store(env, ctx);
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break;
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case OPCM_32_ABS_STOREB_H:
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decode_abs_storeb_h(env, ctx);
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break;
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case OPC1_32_ABS_STOREQ:
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address = MASK_OP_ABS_OFF18(ctx->opcode);
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r1 = MASK_OP_ABS_S1D(ctx->opcode);
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temp = tcg_const_i32(EA_ABS_FORMAT(address));
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temp2 = tcg_temp_new();
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tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
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tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
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tcg_temp_free(temp2);
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tcg_temp_free(temp);
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break;
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case OPC1_32_ABS_LD_Q:
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address = MASK_OP_ABS_OFF18(ctx->opcode);
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r1 = MASK_OP_ABS_S1D(ctx->opcode);
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temp = tcg_const_i32(EA_ABS_FORMAT(address));
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tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
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tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
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tcg_temp_free(temp);
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break;
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case OPC1_32_ABS_LEA:
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address = MASK_OP_ABS_OFF18(ctx->opcode);
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r1 = MASK_OP_ABS_S1D(ctx->opcode);
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tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
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break;
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/* ABSB-format */
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case OPC1_32_ABSB_ST_T:
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address = MASK_OP_ABS_OFF18(ctx->opcode);
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b = MASK_OP_ABSB_B(ctx->opcode);
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bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
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temp = tcg_const_i32(EA_ABS_FORMAT(address));
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temp2 = tcg_temp_new();
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tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
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tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
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tcg_gen_ori_tl(temp2, temp2, (b << bpos));
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tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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break;
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}
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}
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static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
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