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hw/dma.c: Replace register_ioport_*
Replace all register_ioport_*() with the new Memory API functions. This permits to use the new Memory stuff like listeners. Signed-off-by: Julien Grall <julien.grall@citrix.com> Acked-by: Avi Kivity <avi@redhat.com> [AF: Rebased onto hwaddr] Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Julien Grall
Andreas Färber
parent
258711c644
commit
5822993368
1 changed files with 70 additions and 36 deletions
106
hw/dma.c
106
hw/dma.c
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@ -58,6 +58,8 @@ static struct dma_cont {
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int dshift;
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struct dma_regs regs[4];
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qemu_irq *cpu_request_exit;
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MemoryRegion channel_io;
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MemoryRegion cont_io;
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} dma_controllers[2];
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enum {
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@ -149,7 +151,7 @@ static inline int getff (struct dma_cont *d)
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return ff;
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}
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static uint32_t read_chan (void *opaque, uint32_t nport)
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static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size)
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{
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struct dma_cont *d = opaque;
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int ichan, nreg, iport, ff, val, dir;
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@ -171,7 +173,8 @@ static uint32_t read_chan (void *opaque, uint32_t nport)
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return (val >> (d->dshift + (ff << 3))) & 0xff;
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}
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static void write_chan (void *opaque, uint32_t nport, uint32_t data)
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static void write_chan(void *opaque, hwaddr nport, uint64_t data,
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unsigned size)
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{
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struct dma_cont *d = opaque;
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int iport, ichan, nreg;
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@ -189,22 +192,23 @@ static void write_chan (void *opaque, uint32_t nport, uint32_t data)
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}
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}
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static void write_cont (void *opaque, uint32_t nport, uint32_t data)
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static void write_cont(void *opaque, hwaddr nport, uint64_t data,
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unsigned size)
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{
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struct dma_cont *d = opaque;
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int iport, ichan = 0;
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iport = (nport >> d->dshift) & 0x0f;
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switch (iport) {
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case 0x08: /* command */
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case 0x01: /* command */
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if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
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dolog ("command %#x not supported\n", data);
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dolog("command %"PRIx64" not supported\n", data);
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return;
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}
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d->command = data;
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break;
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case 0x09:
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case 0x02:
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ichan = data & 3;
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if (data & 4) {
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d->status |= 1 << (ichan + 4);
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@ -216,7 +220,7 @@ static void write_cont (void *opaque, uint32_t nport, uint32_t data)
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DMA_run();
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break;
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case 0x0a: /* single mask */
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case 0x03: /* single mask */
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if (data & 4)
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d->mask |= 1 << (data & 3);
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else
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@ -224,7 +228,7 @@ static void write_cont (void *opaque, uint32_t nport, uint32_t data)
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DMA_run();
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break;
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case 0x0b: /* mode */
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case 0x04: /* mode */
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{
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ichan = data & 3;
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#ifdef DEBUG_DMA
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@ -243,23 +247,23 @@ static void write_cont (void *opaque, uint32_t nport, uint32_t data)
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break;
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}
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case 0x0c: /* clear flip flop */
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case 0x05: /* clear flip flop */
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d->flip_flop = 0;
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break;
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case 0x0d: /* reset */
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case 0x06: /* reset */
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d->flip_flop = 0;
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d->mask = ~0;
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d->status = 0;
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d->command = 0;
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break;
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case 0x0e: /* clear mask for all channels */
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case 0x07: /* clear mask for all channels */
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d->mask = 0;
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DMA_run();
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break;
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case 0x0f: /* write mask for all channels */
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case 0x08: /* write mask for all channels */
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d->mask = data;
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DMA_run();
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break;
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@ -277,7 +281,7 @@ static void write_cont (void *opaque, uint32_t nport, uint32_t data)
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#endif
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}
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static uint32_t read_cont (void *opaque, uint32_t nport)
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static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size)
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{
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struct dma_cont *d = opaque;
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int iport, val;
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@ -463,7 +467,7 @@ void DMA_schedule(int nchan)
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static void dma_reset(void *opaque)
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{
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struct dma_cont *d = opaque;
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write_cont (d, (0x0d << d->dshift), 0);
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write_cont(d, (0x06 << d->dshift), 0, 1);
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}
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static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len)
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@ -473,38 +477,68 @@ static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len)
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return dma_pos;
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}
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static const MemoryRegionOps channel_io_ops = {
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.read = read_chan,
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.write = write_chan,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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/* IOport from page_base */
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static const MemoryRegionPortio page_portio_list[] = {
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{ 0x01, 3, 1, .write = write_page, .read = read_page, },
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{ 0x07, 1, 1, .write = write_page, .read = read_page, },
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PORTIO_END_OF_LIST(),
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};
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/* IOport from pageh_base */
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static const MemoryRegionPortio pageh_portio_list[] = {
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{ 0x01, 3, 1, .write = write_pageh, .read = read_pageh, },
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{ 0x07, 3, 1, .write = write_pageh, .read = read_pageh, },
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PORTIO_END_OF_LIST(),
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};
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static const MemoryRegionOps cont_io_ops = {
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.read = read_cont,
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.write = write_cont,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
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static void dma_init2(struct dma_cont *d, int base, int dshift,
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int page_base, int pageh_base,
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qemu_irq *cpu_request_exit)
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{
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static const int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
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int i;
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d->dshift = dshift;
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d->cpu_request_exit = cpu_request_exit;
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for (i = 0; i < 8; i++) {
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register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);
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register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
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}
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for (i = 0; i < ARRAY_SIZE (page_port_list); i++) {
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register_ioport_write (page_base + page_port_list[i], 1, 1,
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write_page, d);
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register_ioport_read (page_base + page_port_list[i], 1, 1,
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read_page, d);
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if (pageh_base >= 0) {
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register_ioport_write (pageh_base + page_port_list[i], 1, 1,
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write_pageh, d);
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register_ioport_read (pageh_base + page_port_list[i], 1, 1,
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read_pageh, d);
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}
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}
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for (i = 0; i < 8; i++) {
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register_ioport_write (base + ((i + 8) << dshift), 1, 1,
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write_cont, d);
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register_ioport_read (base + ((i + 8) << dshift), 1, 1,
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read_cont, d);
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memory_region_init_io(&d->channel_io, &channel_io_ops, d,
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"dma-chan", 8 << d->dshift);
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memory_region_add_subregion(isa_address_space_io(NULL),
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base, &d->channel_io);
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isa_register_portio_list(NULL, page_base, page_portio_list, d,
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"dma-page");
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if (pageh_base >= 0) {
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isa_register_portio_list(NULL, pageh_base, pageh_portio_list, d,
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"dma-pageh");
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}
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memory_region_init_io(&d->cont_io, &cont_io_ops, d, "dma-cont",
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8 << d->dshift);
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memory_region_add_subregion(isa_address_space_io(NULL),
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base + (8 << d->dshift), &d->cont_io);
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qemu_register_reset(dma_reset, d);
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dma_reset(d);
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for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {
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