mirror of
https://gitlab.com/qemu-project/qemu
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aspeed queue:
* extension of the rainier machine with VPD contents * fixes for Coverity issues * new "bmc-console" machine option * new "vfp-d32" ARM CPU property -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmSLQjcACgkQUaNDx8/7 7KE/XRAAkMZN7o+5vR7NocAbj9FasFq8G5Du8L5V52k7kjhmTIMtY2StKyXYBI4o MXe89P88gT5kmwAzyzFVkbLwZcS9wnA/71Pv+dc9Fe9fK9Q+1Tn9AGR+nJM7ZsOk qOP2SUfKqoeHBlFaWJAFSs09jPOzQr0elB55YErwXkjkJN9+PcI5l8E3aZGZz9qQ SZY1JpBYXidoF3bqEfQUs1SzszfFOrW9QYO5s93EYfyXTsV93JPfKVviy8DtNQjc EE+mSgvGSELu8ODMzk/b+O1OQ39S+AJ/qoqhYFZWrsxhROfLiFxV8ksAX52sdJeY z7hot8KUaAka2to+7OFQJn6N9i12MsSZ17XQhoOKC0IMwDtFIMFTIm7fkwxuJh9m ktiadL6MEWZCiiq8jLkM1sz/V9BcVEV/zI2WAJnOh8tniGG9U2xWGL7Ijf2Lnxs7 P8cjT0XfBB6LzyEk1OSCScoBBdc3bHJD4xUpnr1ehscg58gyaPVMkkTziqWbeVH1 CvxmGufS0jYXYS5R4/U4PEY5FQdBww77x/JTXx/NYc0ZWetgKCA/jqFtSgINgtdd jKFHPnvOv8NWDagy/+Vb0xZPHbXoYkliMtAV789FujI/6VzPrdW8YljPos/rX/oY b6/Yh1vCwuzVRut5wqMNefmX1ez36rdy3KDvg99Pu3Ln4QqBXhE= =qTHL -----END PGP SIGNATURE----- Merge tag 'pull-aspeed-20230615' of https://github.com/legoater/qemu into staging aspeed queue: * extension of the rainier machine with VPD contents * fixes for Coverity issues * new "bmc-console" machine option * new "vfp-d32" ARM CPU property # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmSLQjcACgkQUaNDx8/7 # 7KE/XRAAkMZN7o+5vR7NocAbj9FasFq8G5Du8L5V52k7kjhmTIMtY2StKyXYBI4o # MXe89P88gT5kmwAzyzFVkbLwZcS9wnA/71Pv+dc9Fe9fK9Q+1Tn9AGR+nJM7ZsOk # qOP2SUfKqoeHBlFaWJAFSs09jPOzQr0elB55YErwXkjkJN9+PcI5l8E3aZGZz9qQ # SZY1JpBYXidoF3bqEfQUs1SzszfFOrW9QYO5s93EYfyXTsV93JPfKVviy8DtNQjc # EE+mSgvGSELu8ODMzk/b+O1OQ39S+AJ/qoqhYFZWrsxhROfLiFxV8ksAX52sdJeY # z7hot8KUaAka2to+7OFQJn6N9i12MsSZ17XQhoOKC0IMwDtFIMFTIm7fkwxuJh9m # ktiadL6MEWZCiiq8jLkM1sz/V9BcVEV/zI2WAJnOh8tniGG9U2xWGL7Ijf2Lnxs7 # P8cjT0XfBB6LzyEk1OSCScoBBdc3bHJD4xUpnr1ehscg58gyaPVMkkTziqWbeVH1 # CvxmGufS0jYXYS5R4/U4PEY5FQdBww77x/JTXx/NYc0ZWetgKCA/jqFtSgINgtdd # jKFHPnvOv8NWDagy/+Vb0xZPHbXoYkliMtAV789FujI/6VzPrdW8YljPos/rX/oY # b6/Yh1vCwuzVRut5wqMNefmX1ez36rdy3KDvg99Pu3Ln4QqBXhE= # =qTHL # -----END PGP SIGNATURE----- # gpg: Signature made Thu 15 Jun 2023 06:54:15 PM CEST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20230615' of https://github.com/legoater/qemu: target/arm: Allow users to set the number of VFP registers aspeed: Introduce a "bmc-console" machine option aspeed: Use the boot_rom region of the fby35 machine aspeed: Introduce a boot_rom region at the machine level aspeed/hace: Initialize g_autofree pointer hw/arm/aspeed: Add VPD data for Rainier machine Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
5692a39f32
9 changed files with 159 additions and 25 deletions
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@ -122,6 +122,11 @@ Options specific to Aspeed machines are :
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* ``spi-model`` to change the SPI Flash model.
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* ``bmc-console`` to change the default console device. Most of the
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machines use the ``UART5`` device for a boot console, which is
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mapped on ``/dev/ttyS4`` under Linux, but it is not always the
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case.
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For instance, to start the ``ast2500-evb`` machine with a different
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FMC chip and a bigger (64M) SPI chip, use :
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@ -129,6 +134,12 @@ FMC chip and a bigger (64M) SPI chip, use :
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-M ast2500-evb,fmc-model=mx25l25635e,spi-model=mx66u51235f
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To change the boot console and use device ``UART3`` (``/dev/ttyS2``
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under Linux), use :
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.. code-block:: bash
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-M ast2500-evb,bmc-console=uart3
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Aspeed minibmc family boards (``ast1030-evb``)
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==================================================================
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@ -40,7 +40,9 @@ struct AspeedMachineState {
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/* Public */
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AspeedSoCState soc;
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MemoryRegion boot_rom;
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bool mmio_exec;
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uint32_t uart_chosen;
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char *fmc_model;
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char *spi_model;
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};
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@ -275,15 +277,15 @@ static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
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* Create a ROM and copy the flash contents at the expected address
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* (0x0). Boots faster than execute-in-place.
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*/
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static void aspeed_install_boot_rom(AspeedSoCState *soc, BlockBackend *blk,
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static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
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uint64_t rom_size)
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{
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MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
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AspeedSoCState *soc = &bmc->soc;
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memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", rom_size,
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memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
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&error_abort);
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memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
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boot_rom, 1);
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&bmc->boot_rom, 1);
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write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort);
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}
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@ -332,10 +334,11 @@ static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
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AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
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AspeedSoCState *s = &bmc->soc;
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
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aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0));
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aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));
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for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
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if (uart == amc->uart_default) {
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if (uart == uart_chosen) {
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continue;
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}
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aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
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@ -431,8 +434,7 @@ static void aspeed_machine_init(MachineState *machine)
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if (mtd0) {
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uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
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aspeed_install_boot_rom(&bmc->soc, blk_by_legacy_dinfo(mtd0),
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rom_size);
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aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(mtd0), rom_size);
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}
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}
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@ -788,8 +790,10 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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0x48);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
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0x4a);
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at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
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at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
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at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50,
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64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len);
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at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51,
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64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len);
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create_pca9552(soc, 8, 0x60);
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create_pca9552(soc, 8, 0x61);
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/* Bus 8: ucd90320@11 */
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@ -1076,6 +1080,35 @@ static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
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bmc->spi_model = g_strdup(value);
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}
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static char *aspeed_get_bmc_console(Object *obj, Error **errp)
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{
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AspeedMachineState *bmc = ASPEED_MACHINE(obj);
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AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
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int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
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return g_strdup_printf("uart%d", uart_chosen - ASPEED_DEV_UART1 + 1);
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}
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static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
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{
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AspeedMachineState *bmc = ASPEED_MACHINE(obj);
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AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
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AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
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int val;
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if (sscanf(value, "uart%u", &val) != 1) {
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error_setg(errp, "Bad value for \"uart\" property");
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return;
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}
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/* The number of UART depends on the SoC */
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if (val < 1 || val > sc->uarts_num) {
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error_setg(errp, "\"uart\" should be in range [1 - %d]", sc->uarts_num);
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return;
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}
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bmc->uart_chosen = ASPEED_DEV_UART1 + val - 1;
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}
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static void aspeed_machine_class_props_init(ObjectClass *oc)
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{
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object_class_property_add_bool(oc, "execute-in-place",
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@ -1084,6 +1117,11 @@ static void aspeed_machine_class_props_init(ObjectClass *oc)
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object_class_property_set_description(oc, "execute-in-place",
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"boot directly from CE0 flash device");
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object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console,
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aspeed_set_bmc_console);
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object_class_property_set_description(oc, "bmc-console",
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"Change the default UART to \"uartX\"");
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object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
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aspeed_set_fmc_model);
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object_class_property_set_description(oc, "fmc-model",
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@ -316,6 +316,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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&error_abort);
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object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
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&error_abort);
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object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
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&error_abort);
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object_property_set_link(OBJECT(&s->cpu[i]), "memory",
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OBJECT(s->memory), &error_abort);
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@ -119,9 +119,52 @@ const uint8_t yosemitev2_bmc_fruid[] = {
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0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45,
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};
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const uint8_t rainier_bb_fruid[] = {
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84,
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0x28, 0x00, 0x52, 0x54, 0x04, 0x56, 0x48, 0x44, 0x52, 0x56, 0x44, 0x02,
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0x01, 0x00, 0x50, 0x54, 0x0e, 0x56, 0x54, 0x4f, 0x43, 0x00, 0x00, 0x37,
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0x00, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x08, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x00, 0x52, 0x54,
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0x04, 0x56, 0x54, 0x4f, 0x43, 0x50, 0x54, 0x38, 0x56, 0x49, 0x4e, 0x49,
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0x00, 0x00, 0x81, 0x00, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x56, 0x53,
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0x59, 0x53, 0x00, 0x00, 0xbb, 0x00, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x56, 0x43, 0x45, 0x4e, 0x00, 0x00, 0xe2, 0x00, 0x27, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x56, 0x53, 0x42, 0x50, 0x00, 0x00, 0x09, 0x01, 0x19, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x01, 0x00, 0x00, 0x00, 0x36, 0x00,
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0x52, 0x54, 0x04, 0x56, 0x49, 0x4e, 0x49, 0x44, 0x52, 0x04, 0x44, 0x45,
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0x53, 0x43, 0x48, 0x57, 0x02, 0x30, 0x31, 0x43, 0x43, 0x04, 0x33, 0x34,
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0x35, 0x36, 0x46, 0x4e, 0x04, 0x46, 0x52, 0x34, 0x39, 0x53, 0x4e, 0x04,
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0x53, 0x52, 0x31, 0x32, 0x50, 0x4e, 0x04, 0x50, 0x52, 0x39, 0x39, 0x50,
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0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x00, 0x52, 0x54,
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0x04, 0x56, 0x53, 0x59, 0x53, 0x53, 0x45, 0x07, 0x49, 0x42, 0x4d, 0x53,
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0x59, 0x53, 0x31, 0x54, 0x4d, 0x08, 0x32, 0x32, 0x32, 0x32, 0x2d, 0x32,
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0x32, 0x32, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
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0x00, 0x52, 0x54, 0x04, 0x56, 0x43, 0x45, 0x4e, 0x53, 0x45, 0x07, 0x31,
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0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x46, 0x43, 0x08, 0x31, 0x31, 0x31,
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0x31, 0x2d, 0x31, 0x31, 0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x15, 0x00, 0x52, 0x54, 0x04, 0x56, 0x53, 0x42, 0x50, 0x49,
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0x4d, 0x04, 0x50, 0x00, 0x10, 0x01, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00,
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0x00, 0x00,
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};
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/* Rainier BMC FRU */
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const uint8_t rainier_bmc_fruid[] = {
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84,
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0x28, 0x00, 0x52, 0x54, 0x04, 0x56, 0x48, 0x44, 0x52, 0x56, 0x44, 0x02,
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0x01, 0x00, 0x50, 0x54, 0x0e, 0x56, 0x54, 0x4f, 0x43, 0x00, 0x00, 0x37,
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0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x08, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x52, 0x54,
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0x04, 0x56, 0x54, 0x4f, 0x43, 0x50, 0x54, 0x0e, 0x56, 0x49, 0x4e, 0x49,
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0x00, 0x00, 0x57, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46,
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0x01, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x52, 0x54, 0x04, 0x56, 0x49, 0x4e,
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0x49, 0x44, 0x52, 0x04, 0x44, 0x45, 0x53, 0x43, 0x48, 0x57, 0x02, 0x30,
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0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
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};
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const size_t tiogapass_bmc_fruid_len = sizeof(tiogapass_bmc_fruid);
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const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
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const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
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const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
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const size_t yosemitev2_bmc_fruid_len = sizeof(yosemitev2_bmc_fruid);
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const size_t rainier_bb_fruid_len = sizeof(rainier_bb_fruid);
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const size_t rainier_bmc_fruid_len = sizeof(rainier_bmc_fruid);
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@ -22,4 +22,9 @@ extern const size_t fby35_bmc_fruid_len;
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extern const uint8_t yosemitev2_bmc_fruid[];
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extern const size_t yosemitev2_bmc_fruid_len;
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extern const uint8_t rainier_bb_fruid[];
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extern const size_t rainier_bb_fruid_len;
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extern const uint8_t rainier_bmc_fruid[];
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extern const size_t rainier_bmc_fruid_len;
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#endif
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@ -70,8 +70,6 @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
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static void fby35_bmc_init(Fby35State *s)
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{
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DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
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object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
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memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
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@ -95,18 +93,21 @@ static void fby35_bmc_init(Fby35State *s)
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aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0);
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/* Install first FMC flash content as a boot rom. */
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if (drive0) {
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AspeedSMCFlash *fl = &s->bmc.fmc.flashes[0];
|
||||
MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
|
||||
uint64_t size = memory_region_size(&fl->mmio);
|
||||
if (!s->mmio_exec) {
|
||||
DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
|
||||
|
||||
if (!s->mmio_exec) {
|
||||
memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
|
||||
size, &error_abort);
|
||||
memory_region_add_subregion(&s->bmc_memory, FBY35_BMC_FIRMWARE_ADDR,
|
||||
boot_rom);
|
||||
fby35_bmc_write_boot_rom(drive0, boot_rom, FBY35_BMC_FIRMWARE_ADDR,
|
||||
size, &error_abort);
|
||||
if (mtd0) {
|
||||
AspeedSoCState *bmc = &s->bmc;
|
||||
uint64_t rom_size = memory_region_size(&bmc->spi_boot);
|
||||
|
||||
memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom",
|
||||
rom_size, &error_abort);
|
||||
memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0,
|
||||
&s->bmc_boot_rom, 1);
|
||||
|
||||
fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom,
|
||||
FBY35_BMC_FIRMWARE_ADDR,
|
||||
rom_size, &error_abort);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -189,7 +189,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
|
|||
bool acc_mode)
|
||||
{
|
||||
struct iovec iov[ASPEED_HACE_MAX_SG];
|
||||
g_autofree uint8_t *digest_buf;
|
||||
g_autofree uint8_t *digest_buf = NULL;
|
||||
size_t digest_len = 0;
|
||||
int niov = 0;
|
||||
int i;
|
||||
|
|
|
|||
|
|
@ -1277,6 +1277,9 @@ static Property arm_cpu_cfgend_property =
|
|||
static Property arm_cpu_has_vfp_property =
|
||||
DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
|
||||
|
||||
static Property arm_cpu_has_vfp_d32_property =
|
||||
DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true);
|
||||
|
||||
static Property arm_cpu_has_neon_property =
|
||||
DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
|
||||
|
||||
|
|
@ -1408,6 +1411,22 @@ void arm_cpu_post_init(Object *obj)
|
|||
}
|
||||
}
|
||||
|
||||
if (cpu->has_vfp && cpu_isar_feature(aa32_simd_r32, cpu)) {
|
||||
cpu->has_vfp_d32 = true;
|
||||
if (!kvm_enabled()) {
|
||||
/*
|
||||
* The permitted values of the SIMDReg bits [3:0] on
|
||||
* Armv8-A are either 0b0000 and 0b0010. On such CPUs,
|
||||
* make sure that has_vfp_d32 can not be set to false.
|
||||
*/
|
||||
if (!(arm_feature(&cpu->env, ARM_FEATURE_V8) &&
|
||||
!arm_feature(&cpu->env, ARM_FEATURE_M))) {
|
||||
qdev_property_add_static(DEVICE(obj),
|
||||
&arm_cpu_has_vfp_d32_property);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
|
||||
cpu->has_neon = true;
|
||||
if (!kvm_enabled()) {
|
||||
|
|
@ -1674,6 +1693,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
|
|||
return;
|
||||
}
|
||||
|
||||
if (cpu->has_vfp_d32 != cpu->has_neon) {
|
||||
error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!cpu->has_vfp_d32) {
|
||||
uint32_t u;
|
||||
|
||||
u = cpu->isar.mvfr0;
|
||||
u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */
|
||||
cpu->isar.mvfr0 = u;
|
||||
}
|
||||
|
||||
if (!cpu->has_vfp) {
|
||||
uint64_t t;
|
||||
uint32_t u;
|
||||
|
|
|
|||
|
|
@ -924,6 +924,8 @@ struct ArchCPU {
|
|||
bool has_pmu;
|
||||
/* CPU has VFP */
|
||||
bool has_vfp;
|
||||
/* CPU has 32 VFP registers */
|
||||
bool has_vfp_d32;
|
||||
/* CPU has Neon */
|
||||
bool has_neon;
|
||||
/* CPU has M-profile DSP extension */
|
||||
|
|
|
|||
Loading…
Reference in a new issue