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mips_malta: move i8259 initialization after piix4 initialization
i8259 is an ISA device (or at least, depends on the ISA infrastructure to register its ioport); and the ISA bus is supplied by piix4. Later patches make this dependency explicit. Use qemu_irq_proxy() to stop the cycle by adding an extra layer of indirection. Signed-off-by: Avi Kivity <avi@redhat.com>
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1 changed files with 15 additions and 5 deletions
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@ -778,7 +778,7 @@ void mips_malta_init (ram_addr_t ram_size,
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int64_t kernel_entry;
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PCIBus *pci_bus;
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CPUState *env;
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qemu_irq *i8259;
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qemu_irq *i8259 = NULL, *isa_irq;
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qemu_irq *cpu_exit_irq;
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int piix4_devfn;
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i2c_bus *smbus;
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@ -928,17 +928,27 @@ void mips_malta_init (ram_addr_t ram_size,
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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/* Interrupt controller */
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/* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
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i8259 = i8259_init(env->irq[2]);
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/*
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* We have a circular dependency problem: pci_bus depends on isa_irq,
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* isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
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* on piix4, and piix4 depends on pci_bus. To stop the cycle we have
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* qemu_irq_proxy() adds an extra bit of indirection, allowing us
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* to resolve the isa_irq -> i8259 dependency after i8259 is initialized.
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*/
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isa_irq = qemu_irq_proxy(&i8259, 16);
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/* Northbridge */
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pci_bus = gt64120_register(i8259);
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pci_bus = gt64120_register(isa_irq);
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/* Southbridge */
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ide_drive_get(hd, MAX_IDE_BUS);
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piix4_devfn = piix4_init(pci_bus, 80);
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/* Interrupt controller */
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/* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
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i8259 = i8259_init(env->irq[2]);
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isa_bus_irqs(i8259);
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pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
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usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
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