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hw/intc: sifive_plic: fix hard-coded max priority level
The maximum priority level is hard-coded when writing to interrupt priority register. However, when writing to priority threshold register, the maximum priority level is from num_priorities Property which is configured by platform. Also change interrupt priority register to use num_priorities Property in maximum priority level. Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com> Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221003041440.2320-2-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -180,8 +180,10 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
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if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
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uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
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plic->source_priority[irq] = value & 7;
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sifive_plic_update(plic);
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if (value <= plic->num_priorities) {
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plic->source_priority[irq] = value;
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sifive_plic_update(plic);
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}
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} else if (addr_between(addr, plic->pending_base,
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plic->num_sources >> 3)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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