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target-arm queue:

Browse source 
* don't expose "ieee_half" via gdbstub (prevents gdb crashes or errors
    with older GDB versions)
  * hw/arm/collie: Put StrongARMState* into a CollieMachineState struct
  * PSTATE.PAN should not clear exec bits
  * hw/gpio/aspeed_gpio.c: Don't directly include assert.h
    (fixes compilation on some Windows build scenarios)
  * dump: Fix writing of ELF section
  * dma/xlnx-zdma: various bug fixes
  * target/arm/helperc. delete obsolete TODO comment
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200406' into staging

target-arm queue:
 * don't expose "ieee_half" via gdbstub (prevents gdb crashes or errors
   with older GDB versions)
 * hw/arm/collie: Put StrongARMState* into a CollieMachineState struct
 * PSTATE.PAN should not clear exec bits
 * hw/gpio/aspeed_gpio.c: Don't directly include assert.h
   (fixes compilation on some Windows build scenarios)
 * dump: Fix writing of ELF section
 * dma/xlnx-zdma: various bug fixes
 * target/arm/helperc. delete obsolete TODO comment

# gpg: Signature made Mon 06 Apr 2020 11:04:01 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200406:
  dma/xlnx-zdma: Reorg to fix CUR_DSCR
  dma/xlnx-zdma: Advance the descriptor address when stopping
  dma/xlnx-zdma: Clear DMA_DONE when halting
  dma/xlnx-zdma: Populate DBG0.CMN_BUF_FREE
  dma/xlnx-zdma: Remove comment
  dump: Fix writing of ELF section
  hw/gpio/aspeed_gpio.c: Don't directly include assert.h
  target/arm: Remove obsolete TODO note from get_phys_addr_lpae()
  target/arm: PSTATE.PAN should not clear exec bits
  hw/arm/collie: Put StrongARMState* into a CollieMachineState struct
  target/arm: don't expose "ieee_half" via gdbstub

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-04-06 12:36:45 +01:00
commit 53ef8a92eb
6 changed files with 69 additions and 44 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
dump/dump.c
View file

@ -364,7 +364,7 @@ static void write_elf_section(DumpState *s, int type, Error **errp)
shdr = &shdr64;
}
ret = fd_write_vmcore(&shdr, shdr_size, s);
ret = fd_write_vmcore(shdr, shdr_size, s);
if (ret < 0) {
error_setg_errno(errp, -ret,
"dump: failed to write section header table");

33
hw/arm/collie.c
View file

@ -19,6 +19,16 @@
#include "exec/address-spaces.h"
#include "cpu.h"
typedef struct {
MachineState parent;
StrongARMState *sa1110;
} CollieMachineState;
#define TYPE_COLLIE_MACHINE MACHINE_TYPE_NAME("collie")
#define COLLIE_MACHINE(obj) \
OBJECT_CHECK(CollieMachineState, obj, TYPE_COLLIE_MACHINE)
static struct arm_boot_info collie_binfo = {
.loader_start = SA_SDCS0,
.ram_size = 0x20000000,
@ -26,9 +36,9 @@ static struct arm_boot_info collie_binfo = {
static void collie_init(MachineState *machine)
{
StrongARMState *s;
DriveInfo *dinfo;
MachineClass *mc = MACHINE_GET_CLASS(machine);
CollieMachineState *cms = COLLIE_MACHINE(machine);
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
@ -37,7 +47,7 @@ static void collie_init(MachineState *machine)
exit(EXIT_FAILURE);
}
s = sa1110_init(machine->cpu_type);
cms->sa1110 = sa1110_init(machine->cpu_type);
memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram);
@ -54,11 +64,13 @@ static void collie_init(MachineState *machine)
sysbus_create_simple("scoop", 0x40800000, NULL);
collie_binfo.board_id = 0x208;
arm_load_kernel(s->cpu, machine, &collie_binfo);
arm_load_kernel(cms->sa1110->cpu, machine, &collie_binfo);
}
static void collie_machine_init(MachineClass *mc)
static void collie_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)";
mc->init = collie_init;
mc->ignore_memory_transaction_failures = true;
@ -67,4 +79,15 @@ static void collie_machine_init(MachineClass *mc)
mc->default_ram_id = "strongarm.sdram";
}
DEFINE_MACHINE("collie", collie_machine_init)
static const TypeInfo collie_machine_typeinfo = {
.name = TYPE_COLLIE_MACHINE,
.parent = TYPE_MACHINE,
.class_init = collie_machine_class_init,
.instance_size = sizeof(CollieMachineState),
};
static void collie_machine_register_types(void)
{
type_register_static(&collie_machine_typeinfo);
}
type_init(collie_machine_register_types);

56
hw/dma/xlnx-zdma.c
View file

@ -333,10 +333,28 @@ static void zdma_load_src_descriptor(XlnxZDMA *s)
}
}
static void zdma_update_descr_addr(XlnxZDMA *s, bool type,
unsigned int basereg)
{
uint64_t addr, next;
if (type == DTYPE_LINEAR) {
addr = zdma_get_regaddr64(s, basereg);
next = addr + sizeof(s->dsc_dst);
} else {
addr = zdma_get_regaddr64(s, basereg);
addr += sizeof(s->dsc_dst);
address_space_read(s->dma_as, addr, s->attr, (void *) &next, 8);
}
zdma_put_regaddr64(s, basereg, next);
}
static void zdma_load_dst_descriptor(XlnxZDMA *s)
{
uint64_t dst_addr;
unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
bool dst_type;
if (ptype == PT_REG) {
memcpy(&s->dsc_dst, &s->regs[R_ZDMA_CH_DST_DSCR_WORD0],
@ -349,24 +367,10 @@ static void zdma_load_dst_descriptor(XlnxZDMA *s)
if (!zdma_load_descriptor(s, dst_addr, &s->dsc_dst)) {
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_DST_DSCR, true);
}
}
static uint64_t zdma_update_descr_addr(XlnxZDMA *s, bool type,
unsigned int basereg)
{
uint64_t addr, next;
if (type == DTYPE_LINEAR) {
next = zdma_get_regaddr64(s, basereg);
next += sizeof(s->dsc_dst);
zdma_put_regaddr64(s, basereg, next);
} else {
addr = zdma_get_regaddr64(s, basereg);
addr += sizeof(s->dsc_dst);
address_space_read(s->dma_as, addr, s->attr, &next, 8);
zdma_put_regaddr64(s, basereg, next);
}
return next;
/* Advance the descriptor pointer. */
dst_type = FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_WORD3, TYPE);
zdma_update_descr_addr(s, dst_type, R_ZDMA_CH_DST_CUR_DSCR_LSB);
}
static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, uint32_t len)
@ -387,14 +391,7 @@ static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, uint32_t len)
dst_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2,
SIZE);
if (dst_size == 0 && ptype == PT_MEM) {
uint64_t next;
bool dst_type = FIELD_EX32(s->dsc_dst.words[3],
ZDMA_CH_DST_DSCR_WORD3,
TYPE);
next = zdma_update_descr_addr(s, dst_type,
R_ZDMA_CH_DST_CUR_DSCR_LSB);
zdma_load_descriptor(s, next, &s->dsc_dst);
zdma_load_dst_descriptor(s);
dst_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2,
SIZE);
}
@ -511,16 +508,15 @@ static void zdma_process_descr(XlnxZDMA *s)
zdma_src_done(s);
}
/* Load next descriptor. */
if (ptype == PT_REG || src_cmd == CMD_STOP) {
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL2, EN, 0);
zdma_set_state(s, DISABLED);
return;
}
if (src_cmd == CMD_HALT) {
zdma_set_state(s, PAUSED);
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_PAUSE, 1);
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_DONE, false);
zdma_ch_imr_update_irq(s);
return;
}
@ -681,6 +677,12 @@ static RegisterAccessInfo zdma_regs_info[] = {
},{ .name = "ZDMA_CH_DBG0", .addr = A_ZDMA_CH_DBG0,
.rsvd = 0xfffffe00,
.ro = 0x1ff,
/*
* There's SW out there that will check the debug regs for free space.
* Claim that we always have 0x100 free.
*/
.reset = 0x100
},{ .name = "ZDMA_CH_DBG1", .addr = A_ZDMA_CH_DBG1,
.rsvd = 0xfffffe00,
.ro = 0x1ff,

2
hw/gpio/aspeed_gpio.c
View file

@ -6,8 +6,6 @@
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <assert.h>
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
#include "qemu/log.h"

7
target/arm/gdbstub.c
View file

@ -192,7 +192,12 @@ static const struct TypeSize vec_lanes[] = {
/* 16 bit */
{ "uint16", 16, 'h', 'u' },
{ "int16", 16, 'h', 's' },
{ "ieee_half", 16, 'h', 'f' },
/*
* TODO: currently there is no reliable way of telling
* if the remote gdb actually understands ieee_half so
* we don't expose it in the target description for now.
* { "ieee_half", 16, 'h', 'f' },
*/
/* bytes */
{ "uint8", 8, 'b', 'u' },
{ "int8", 8, 'b', 's' },

13
target/arm/helper.c
View file

@ -10025,9 +10025,11 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
prot_rw = user_rw;
} else {
if (user_rw && regime_is_pan(env, mmu_idx)) {
return 0;
/* PAN forbids data accesses but doesn't affect insn fetch */
prot_rw = 0;
} else {
prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
}
prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
}
if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
@ -10751,12 +10753,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
bool aarch64 = arm_el_is_aa64(env, el);
bool guarded = false;
/* TODO:
* This code does not handle the different format TCR for VTCR_EL2.
* This code also does not support shareability levels.
* Attribute and permission bit handling should also be checked when adding
* support for those page table walks.
*/
/* TODO: This code does not support shareability levels. */
if (aarch64) {
param = aa64_va_parameters(env, address, mmu_idx,
access_type != MMU_INST_FETCH);