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target/microblaze: Convert msrclr, msrset to decodetree
Split this out of dec_msr. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -24,6 +24,7 @@
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&typeb rd ra imm
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&typeb_br rd imm
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&typeb_bc ra imm
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&type_msr rd imm
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# Include any IMM prefix in the value reported.
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%extimm 0:s16 !function=typeb_imm
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@ -55,6 +56,8 @@
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%ieimm 6:5 0:5
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@typeb_ie ...... rd:5 ra:5 ..... ..... . ..... &typeb imm=%ieimm
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@type_msr ...... rd:5 ...... imm:15 &type_msr
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###
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{
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@ -179,6 +182,9 @@ lwi 111010 ..... ..... ................ @typeb
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mbar 101110 imm:5 00010 0000 0000 0000 0100
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msrclr 100101 ..... 100010 ............... @type_msr
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msrset 100101 ..... 100000 ............... @type_msr
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mul 010000 ..... ..... ..... 000 0000 0000 @typea
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mulh 010000 ..... ..... ..... 000 0000 0001 @typea
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mulhu 010000 ..... ..... ..... 000 0000 0011 @typea
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@ -1311,16 +1311,61 @@ static void msr_write(DisasContext *dc, TCGv_i32 v)
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tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR));
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}
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static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set)
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{
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uint32_t imm = arg->imm;
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if (trap_userspace(dc, imm != MSR_C)) {
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return true;
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}
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if (arg->rd) {
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msr_read(dc, cpu_R[arg->rd]);
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}
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/*
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* Handle the carry bit separately.
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* This is the only bit that userspace can modify.
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*/
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if (imm & MSR_C) {
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tcg_gen_movi_i32(cpu_msr_c, set);
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}
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/*
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* MSR_C and MSR_CC set above.
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* MSR_PVR is not writable, and is always clear.
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*/
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imm &= ~(MSR_C | MSR_CC | MSR_PVR);
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if (imm != 0) {
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if (set) {
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tcg_gen_ori_i32(cpu_msr, cpu_msr, imm);
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} else {
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tcg_gen_andi_i32(cpu_msr, cpu_msr, ~imm);
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}
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dc->cpustate_changed = 1;
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}
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return true;
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}
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static bool trans_msrclr(DisasContext *dc, arg_type_msr *arg)
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{
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return do_msrclrset(dc, arg, false);
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}
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static bool trans_msrset(DisasContext *dc, arg_type_msr *arg)
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{
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return do_msrclrset(dc, arg, true);
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}
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static void dec_msr(DisasContext *dc)
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{
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CPUState *cs = CPU(dc->cpu);
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TCGv_i32 t0, t1;
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unsigned int sr, rn;
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bool to, clrset, extended = false;
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bool to, extended = false;
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sr = extract32(dc->imm, 0, 14);
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to = extract32(dc->imm, 14, 1);
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clrset = extract32(dc->imm, 15, 1) == 0;
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dc->type_b = 1;
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if (to) {
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dc->cpustate_changed = 1;
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@ -1334,40 +1379,6 @@ static void dec_msr(DisasContext *dc)
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extended = extract32(dc->imm, e_bit[to], 1);
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}
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/* msrclr and msrset. */
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if (clrset) {
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bool clr = extract32(dc->ir, 16, 1);
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if (!dc->cpu->cfg.use_msr_instr) {
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/* nop??? */
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return;
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}
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if (trap_userspace(dc, dc->imm != 4 && dc->imm != 0)) {
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return;
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}
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if (dc->rd)
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msr_read(dc, cpu_R[dc->rd]);
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t0 = tcg_temp_new_i32();
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t1 = tcg_temp_new_i32();
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msr_read(dc, t0);
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tcg_gen_mov_i32(t1, *(dec_alu_op_b(dc)));
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if (clr) {
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tcg_gen_not_i32(t1, t1);
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tcg_gen_and_i32(t0, t0, t1);
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} else
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tcg_gen_or_i32(t0, t0, t1);
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msr_write(dc, t0);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t1);
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tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4);
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dc->base.is_jmp = DISAS_UPDATE;
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return;
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}
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if (trap_userspace(dc, to)) {
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return;
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}
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