system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-11-05 20:35:44 +00:00
Code Issues Projects Releases Packages Wiki Activity

target-arm: Use sextract32() in branch decode

Browse source 
In the decode of ARM B and BL insns, swap the order of the
"append 2 implicit zeros to imm24" and the sign extend, and
use the new sextract32() utility function to do the latter.
This avoids a direct dependency on the undefined C behaviour
of shifting into the sign bit of an integer.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1378391908-22137-2-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2013-09-10 19:09:32 +01:00
parent f5f6d38b74
commit 534df15609
1 changed files with 3 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
target-arm/translate.c
View file

@ -28,6 +28,7 @@
#include "disas/disas.h"
#include "tcg-op.h"
#include "qemu/log.h"
#include "qemu/bitops.h"
#include "helper.h"
#define GEN_HELPER 1
@ -7957,8 +7958,8 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
tcg_gen_movi_i32(tmp, val);
store_reg(s, 14, tmp);
}
offset = (((int32_t)insn << 8) >> 8);
val += (offset << 2) + 4;
offset = sextract32(insn << 2, 0, 26);
val += offset + 4;
gen_jmp(s, val);
}
break;