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https://gitlab.com/qemu-project/qemu
synced 2024-10-14 23:13:30 +00:00
Omap DPLL & APLL locking logic.
Reset I2C fifo on new transfers. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4919 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
parent
74b9decc47
commit
51fec3cc7e
119
hw/omap2.c
119
hw/omap2.c
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@ -2727,6 +2727,8 @@ struct omap_prcm_s {
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uint32_t ev;
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uint32_t evtime[2];
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int dpll_lock, apll_lock[2];
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};
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static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
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@ -2739,6 +2741,7 @@ static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
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{
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struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
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int offset = addr - s->base;
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uint32_t ret;
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switch (offset) {
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case 0x000: /* PRCM_REVISION */
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@ -2922,14 +2925,17 @@ static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
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case 0x500: /* CM_CLKEN_PLL */
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return s->clken[9];
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case 0x520: /* CM_IDLEST_CKGEN */
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/* Core uses 32-kHz clock */
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ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
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if (!(s->clksel[6] & 3))
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return 0x00000377;
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/* DPLL not in lock mode, core uses ref_clk */
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if ((s->clken[9] & 3) != 3)
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return 0x00000375;
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/* Core uses DPLL */
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return 0x00000376;
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/* Core uses 32-kHz clock */
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ret |= 3 << 0;
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else if (!s->dpll_lock)
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/* DPLL not locked, core uses ref_clk */
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ret |= 1 << 0;
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else
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/* Core uses DPLL */
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ret |= 2 << 0;
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return ret;
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case 0x530: /* CM_AUTOIDLE_PLL */
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return s->clkidle[5];
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case 0x540: /* CM_CLKSEL1_PLL */
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@ -2976,6 +2982,69 @@ static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
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return 0;
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}
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static void omap_prcm_apll_update(struct omap_prcm_s *s)
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{
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int mode[2];
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mode[0] = (s->clken[9] >> 6) & 3;
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s->apll_lock[0] = (mode[0] == 3);
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mode[1] = (s->clken[9] >> 2) & 3;
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s->apll_lock[1] = (mode[1] == 3);
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/* TODO: update clocks */
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if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[2] == 2)
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fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
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__FUNCTION__);
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}
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static void omap_prcm_dpll_update(struct omap_prcm_s *s)
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{
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omap_clk dpll = omap_findclk(s->mpu, "dpll");
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omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
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omap_clk core = omap_findclk(s->mpu, "core_clk");
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int mode = (s->clken[9] >> 0) & 3;
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int mult, div;
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mult = (s->clksel[5] >> 12) & 0x3ff;
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div = (s->clksel[5] >> 8) & 0xf;
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if (mult == 0 || mult == 1)
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mode = 1; /* Bypass */
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s->dpll_lock = 0;
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switch (mode) {
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case 0:
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fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__);
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break;
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case 1: /* Low-power bypass mode (Default) */
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case 2: /* Fast-relock bypass mode */
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omap_clk_setrate(dpll, 1, 1);
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omap_clk_setrate(dpll_x2, 1, 1);
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break;
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case 3: /* Lock mode */
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s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
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omap_clk_setrate(dpll, div + 1, mult);
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omap_clk_setrate(dpll_x2, div + 1, mult * 2);
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break;
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}
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switch ((s->clksel[6] >> 0) & 3) {
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case 0:
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omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
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break;
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case 1:
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omap_clk_reparent(core, dpll);
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break;
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case 2:
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/* Default */
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omap_clk_reparent(core, dpll_x2);
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break;
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case 3:
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fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__);
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break;
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}
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}
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static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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@ -3235,20 +3304,44 @@ static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
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break;
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case 0x500: /* CM_CLKEN_PLL */
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s->clken[9] = value & 0xcf;
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/* TODO update clocks */
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if (value & 0xffffff30)
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fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
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"future compatiblity\n", __FUNCTION__);
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if ((s->clken[9] ^ value) & 0xcc) {
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s->clken[9] &= ~0xcc;
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s->clken[9] |= value & 0xcc;
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omap_prcm_apll_update(s);
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}
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if ((s->clken[9] ^ value) & 3) {
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s->clken[9] &= ~3;
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s->clken[9] |= value & 3;
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omap_prcm_dpll_update(s);
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}
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break;
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case 0x530: /* CM_AUTOIDLE_PLL */
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s->clkidle[5] = value & 0x000000cf;
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/* TODO update clocks */
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break;
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case 0x540: /* CM_CLKSEL1_PLL */
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if (value & 0xfc4000d7)
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fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
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"future compatiblity\n", __FUNCTION__);
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if ((s->clksel[5] ^ value) & 0x003fff00) {
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s->clksel[5] = value & 0x03bfff28;
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omap_prcm_dpll_update(s);
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}
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/* TODO update the other clocks */
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s->clksel[5] = value & 0x03bfff28;
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/* TODO update clocks */
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break;
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case 0x544: /* CM_CLKSEL2_PLL */
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s->clksel[6] = value & 3;
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/* TODO update clocks */
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if (value & ~3)
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fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
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"future compatiblity\n", __FUNCTION__);
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if (s->clksel[6] != (value & 3)) {
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s->clksel[6] = value & 3;
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omap_prcm_dpll_update(s);
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}
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break;
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case 0x800: /* CM_FCLKEN_DSP */
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@ -3373,6 +3466,8 @@ static void omap_prcm_reset(struct omap_prcm_s *s)
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s->power[3] = 0x14;
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s->rstctrl[0] = 1;
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s->rst[3] = 1;
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omap_prcm_apll_update(s);
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omap_prcm_dpll_update(s);
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}
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static void omap_prcm_coldreset(struct omap_prcm_s *s)
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@ -510,18 +510,25 @@ static struct clk clk32k = {
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.parent = &xtal_osc32k,
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};
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static struct clk ref_clk = {
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.name = "ref_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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.rate = 12000000, /* 12 MHz or 13 MHz or 19.2 MHz */
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/*.parent = sys.xtalin */
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};
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static struct clk apll_96m = {
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.name = "apll_96m",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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.rate = 96000000,
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/*.parent = sys.xtalin */
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/*.parent = ref_clk */
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};
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static struct clk apll_54m = {
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.name = "apll_54m",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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.rate = 54000000,
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/*.parent = sys.xtalin */
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/*.parent = ref_clk */
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};
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static struct clk sys_clk = {
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@ -541,13 +548,13 @@ static struct clk sleep_clk = {
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static struct clk dpll_ck = {
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.name = "dpll",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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/*.parent = sys.xtalin */
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.parent = &ref_clk,
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};
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static struct clk dpll_x2_ck = {
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.name = "dpll_x2",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
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/*.parent = sys.xtalin */
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.parent = &ref_clk,
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};
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static struct clk wdt1_sys_clk = {
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@ -600,7 +607,7 @@ static struct clk sys_clkout2 = {
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static struct clk core_clk = {
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.name = "core_clk",
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.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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.parent = &dpll_ck,
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.parent = &dpll_x2_ck, /* Switchable between dpll_ck and clk32k */
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};
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static struct clk l3_clk = {
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@ -1009,6 +1016,7 @@ static struct clk *onchip_clks[] = {
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/* OMAP 2 */
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&ref_clk,
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&apll_96m,
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&apll_54m,
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&sys_clk,
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@ -395,6 +395,7 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
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(~value >> 9) & 1); /* TRX */
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s->stat |= nack << 1; /* NACK */
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s->control &= ~(1 << 0); /* STT */
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s->fifo = 0;
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if (nack)
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s->control &= ~(1 << 1); /* STP */
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else {
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