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Use firmware configuration instead of NVRAM (initial patch by Aurelien Jarno)

Browse source 
Use firmware configuration device for boot device, kernel, initrd and
kernel command line parameters on PPC, Sparc32 and Sparc64.

Update OpenBIOS images to r479 which supports the change.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6777 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2009-03-08 09:51:29 +00:00
parent 7e12f65678
commit 513f789f6b
10 changed files with 112 additions and 261 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

127
hw/firmware_abi.h
View file

@ -1,113 +1,6 @@
#ifndef FIRMWARE_ABI_H
#define FIRMWARE_ABI_H
#ifndef __ASSEMBLY__
/* Open Hack'Ware NVRAM configuration structure */
/* Version 3 */
typedef struct ohwcfg_v3_t ohwcfg_v3_t;
struct ohwcfg_v3_t {
/* 0x00: structure identifier */
uint8_t struct_ident[0x10];
/* 0x10: structure version and NVRAM description */
uint32_t struct_version;
uint16_t nvram_size;
uint16_t pad0;
uint16_t nvram_arch_ptr;
uint16_t nvram_arch_size;
uint16_t nvram_arch_crc;
uint8_t pad1[0x02];
/* 0x20: host architecture */
uint8_t arch[0x10];
/* 0x30: RAM/ROM description */
uint64_t RAM0_base;
uint64_t RAM0_size;
uint64_t RAM1_base;
uint64_t RAM1_size;
uint64_t RAM2_base;
uint64_t RAM2_size;
uint64_t RAM3_base;
uint64_t RAM3_size;
uint64_t ROM_base;
uint64_t ROM_size;
/* 0x80: Kernel description */
uint64_t kernel_image;
uint64_t kernel_size;
/* 0x90: Kernel command line */
uint64_t cmdline;
uint64_t cmdline_size;
/* 0xA0: Kernel boot image */
uint64_t initrd_image;
uint64_t initrd_size;
/* 0xB0: NVRAM image */
uint64_t NVRAM_image;
uint8_t pad2[8];
/* 0xC0: graphic configuration */
uint16_t width;
uint16_t height;
uint16_t depth;
uint16_t graphic_flags;
/* 0xC8: CPUs description */
uint8_t nb_cpus;
uint8_t boot_cpu;
uint8_t nboot_devices;
uint8_t pad3[5];
/* 0xD0: boot devices */
uint8_t boot_devices[0x10];
/* 0xE0 */
uint8_t pad4[0x1C]; /* 28 */
/* 0xFC: checksum */
uint16_t crc;
uint8_t pad5[0x02];
} __attribute__ (( packed ));
#define OHW_GF_NOGRAPHICS 0x0001
static inline uint16_t
OHW_crc_update (uint16_t prev, uint16_t value)
{
uint16_t tmp;
uint16_t pd, pd1, pd2;
tmp = prev >> 8;
pd = prev ^ value;
pd1 = pd & 0x000F;
pd2 = ((pd >> 4) & 0x000F) ^ pd1;
tmp ^= (pd1 << 3) | (pd1 << 8);
tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
return tmp;
}
static inline uint16_t
OHW_compute_crc (ohwcfg_v3_t *header, uint32_t start, uint32_t count)
{
uint32_t i;
uint16_t crc = 0xFFFF;
uint8_t *ptr = (uint8_t *)header;
int odd;
odd = count & 1;
count &= ~1;
for (i = 0; i != count; i++) {
crc = OHW_crc_update(crc, (ptr[start + i] << 8) | ptr[start + i + 1]);
}
if (odd) {
crc = OHW_crc_update(crc, ptr[start + i] << 8);
}
return crc;
}
/* Sparc32 runtime NVRAM structure for SMP CPU boot */
struct sparc_arch_cfg {
uint32_t smp_ctx;
uint32_t smp_ctxtbl;
uint32_t smp_entry;
uint8_t valid;
uint8_t unused[51];
};
/* OpenBIOS NVRAM partition */
struct OpenBIOS_nvpart_v1 {
uint8_t signature;
@ -175,24 +68,4 @@ Sun_init_header(struct Sun_nvram *header, const uint8_t *macaddr, int machine_id
header->checksum = tmp;
}
#else /* __ASSEMBLY__ */
/* Structure offsets for asm use */
/* Open Hack'Ware NVRAM configuration structure */
#define OHW_ARCH_PTR 0x18
#define OHW_RAM_SIZE 0x38
#define OHW_BOOT_CPU 0xC9
/* Sparc32 runtime NVRAM structure for SMP CPU boot */
#define SPARC_SMP_CTX 0x0
#define SPARC_SMP_CTXTBL 0x4
#define SPARC_SMP_ENTRY 0x8
#define SPARC_SMP_VALID 0xc
/* Sun IDPROM structure at the end of NVRAM */
#define SPARC_MACHINE_ID 0x1fd9
#endif /* __ASSEMBLY__ */
#endif /* FIRMWARE_ABI_H */

1
hw/ppc_mac.h
View file

@ -35,6 +35,7 @@
#define PROM_ADDR 0xfff00000
#define KERNEL_LOAD_ADDR 0x01000000
#define CMDLINE_ADDR 0x017ff000
#define INITRD_LOAD_ADDR 0x01800000
#define ESCC_CLOCK 3686400

37
hw/ppc_newworld.c
View file

@ -78,6 +78,12 @@ static CPUReadMemoryFunc *unin_read[] = {
&unin_readl,
};
static int fw_cfg_boot_set(void *opaque, const char *boot_device)
{
fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
return 0;
}
/* PowerPC Mac99 hardware initialisation */
static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device,
@ -167,9 +173,24 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
}
if (linux_boot) {
uint64_t lowaddr = 0;
kernel_base = KERNEL_LOAD_ADDR;
/* now we can load the kernel */
kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
/* Now we can load the kernel. The first step tries to load the kernel
supposing PhysAddr = 0x00000000. If that was wrong the kernel is
loaded again, the new PhysAddr being computed from lowaddr. */
kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL);
if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) {
kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr,
NULL, 0, NULL);
}
if (kernel_size < 0)
kernel_size = load_aout(kernel_filename, kernel_base,
ram_size - kernel_base);
if (kernel_size < 0)
kernel_size = load_image_targphys(kernel_filename,
kernel_base,
ram_size - kernel_base);
if (kernel_size < 0) {
cpu_abort(env, "qemu: could not load kernel '%s'\n",
kernel_filename);
@ -321,6 +342,18 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_MAC99);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
QEMUMachine core99_machine = {

33
hw/ppc_oldworld.c
View file

@ -108,6 +108,12 @@ static int vga_osi_call (CPUState *env)
return 1; /* osi_call handled */
}
static int fw_cfg_boot_set(void *opaque, const char *boot_device)
{
fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
return 0;
}
static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device,
const char *kernel_filename,
@ -118,8 +124,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
CPUState *env = NULL, *envs[MAX_CPUS];
char buf[1024];
qemu_irq *pic, **heathrow_irqs;
nvram_t nvram;
m48t59_t *m48t59;
int linux_boot, i;
ram_addr_t ram_offset, vga_ram_offset, bios_offset, vga_bios_offset;
uint32_t kernel_base, initrd_base;
@ -129,7 +133,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
int vga_bios_size, bios_size;
int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
int escc_mem_index, ide_mem_index[2];
int ppc_boot_device;
uint16_t ppc_boot_device;
BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
int index;
void *fw_cfg;
@ -363,23 +367,24 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
graphic_depth = 15;
m48t59 = m48t59_init(0, 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
nvram.opaque = m48t59;
nvram.read_fn = &m48t59_read;
nvram.write_fn = &m48t59_write;
PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
ppc_boot_device, kernel_base, kernel_size,
kernel_cmdline,
initrd_base, initrd_size,
/* XXX: need an option to load a NVRAM image */
0,
graphic_width, graphic_height, graphic_depth);
/* No PCI init: the BIOS will do it */
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
QEMUMachine heathrow_machine = {

98
hw/sun4m.c
View file

@ -174,24 +174,9 @@ void DMA_register_channel (int nchan,
{
}
static int nvram_boot_set(void *opaque, const char *boot_device)
static int fw_cfg_boot_set(void *opaque, const char *boot_device)
{
unsigned int i;
uint8_t image[sizeof(ohwcfg_v3_t)];
ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
m48t59_t *nvram = (m48t59_t *)opaque;
for (i = 0; i < sizeof(image); i++)
image[i] = m48t59_read(nvram, i) & 0xff;
pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
boot_device);
header->nboot_devices = strlen(boot_device) & 0xff;
header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
for (i = 0; i < sizeof(image); i++)
m48t59_write(nvram, i, image[i]);
fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
return 0;
}
@ -204,48 +189,11 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
unsigned int i;
uint32_t start, end;
uint8_t image[0x1ff0];
ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
struct sparc_arch_cfg *sparc_header;
struct OpenBIOS_nvpart_v1 *part_header;
memset(image, '\0', sizeof(image));
// Try to match PPC NVRAM
pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
"QEMU_BIOS");
header->struct_version = cpu_to_be32(3); /* structure v3 */
header->nvram_size = cpu_to_be16(0x2000);
header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
pstrcpy((char *)header->arch, sizeof(header->arch), arch);
header->nb_cpus = smp_cpus & 0xff;
header->RAM0_base = 0;
header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
boot_devices);
header->nboot_devices = strlen(boot_devices) & 0xff;
header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
if (cmdline) {
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
}
// XXX add initrd_image, initrd_size
header->width = cpu_to_be16(width);
header->height = cpu_to_be16(height);
header->depth = cpu_to_be16(depth);
if (nographic)
header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
// Architecture specific header
start = sizeof(ohwcfg_v3_t);
sparc_header = (struct sparc_arch_cfg *)&image[start];
sparc_header->valid = 0;
start += sizeof(struct sparc_arch_cfg);
start = 0;
// OpenBIOS nvram variables
// Variable partition
@ -277,8 +225,6 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
for (i = 0; i < sizeof(image); i++)
m48t59_write(nvram, i, image[i]);
qemu_register_boot_set(nvram_boot_set, nvram);
}
static void *slavio_intctl;
@ -604,6 +550,18 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
enum {
@ -1362,6 +1320,19 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
/* SPARCserver 1000 hardware initialisation */
@ -1580,6 +1551,19 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
/* SPARCstation 2 hardware initialisation */

75
hw/sun4u.c
View file

@ -89,24 +89,9 @@ void DMA_register_channel (int nchan,
{
}
static int nvram_boot_set(void *opaque, const char *boot_device)
static int fw_cfg_boot_set(void *opaque, const char *boot_device)
{
unsigned int i;
uint8_t image[sizeof(ohwcfg_v3_t)];
ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
m48t59_t *nvram = (m48t59_t *)opaque;
for (i = 0; i < sizeof(image); i++)
image[i] = m48t59_read(nvram, i) & 0xff;
pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
boot_device);
header->nboot_devices = strlen(boot_device) & 0xff;
header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
for (i = 0; i < sizeof(image); i++)
m48t59_write(nvram, i, image[i]);
fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
return 0;
}
@ -124,51 +109,11 @@ static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
unsigned int i;
uint32_t start, end;
uint8_t image[0x1ff0];
ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
struct sparc_arch_cfg *sparc_header;
struct OpenBIOS_nvpart_v1 *part_header;
memset(image, '\0', sizeof(image));
// Try to match PPC NVRAM
pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
"QEMU_BIOS");
header->struct_version = cpu_to_be32(3); /* structure v3 */
header->nvram_size = cpu_to_be16(NVRAM_size);
header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
pstrcpy((char *)header->arch, sizeof(header->arch), arch);
header->nb_cpus = smp_cpus & 0xff;
header->RAM0_base = 0;
header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
boot_devices);
header->nboot_devices = strlen(boot_devices) & 0xff;
header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
if (cmdline) {
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
}
header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
header->width = cpu_to_be16(width);
header->height = cpu_to_be16(height);
header->depth = cpu_to_be16(depth);
if (nographic)
header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
// Architecture specific header
start = sizeof(ohwcfg_v3_t);
sparc_header = (struct sparc_arch_cfg *)&image[start];
sparc_header->valid = 0;
start += sizeof(struct sparc_arch_cfg);
start = 0;
// OpenBIOS nvram variables
// Variable partition
@ -200,8 +145,6 @@ static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
for (i = 0; i < sizeof(image); i++)
m48t59_write(nvram, i, image[i]);
qemu_register_boot_set(nvram_boot_set, nvram);
return 0;
}
@ -575,6 +518,18 @@ static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
enum {

2
pc-bios/README
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@ -42,7 +42,7 @@
firmware implementation. The goal is to implement a 100% IEEE
1275-1994 (referred to as Open Firmware) compliant firmware.
The included images for Sparc32, Sparc64 and PowerPC (for 32 and 64 bit
PPC CPUs) are built from OpenBIOS 1.0 release (SVN revision 463).
PPC CPUs) are built from OpenBIOS SVN revision 479.
- The PXE roms come from Rom-o-Matic etherboot 5.4.2.
pcnet32:pcnet32 -- [0x1022,0x2000]

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pc-bios/openbios-ppc
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pc-bios/openbios-sparc32
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pc-bios/openbios-sparc64
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