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target-ppc: Introduce DFP Reround
Add emulation of the PowerPC Decimal Floating Point Reround instructions drrnd[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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3 changed files with 103 additions and 0 deletions
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@ -376,6 +376,23 @@ static inline void dfp_makeQNaN(decNumber *dn)
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dn->bits |= DECNAN;
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}
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static inline int dfp_get_digit(decNumber *dn, int n)
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{
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assert(DECDPUN == 3);
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int unit = n / DECDPUN;
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int dig = n % DECDPUN;
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switch (dig) {
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case 0:
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return dn->lsu[unit] % 10;
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case 1:
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return (dn->lsu[unit] / 10) % 10;
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case 2:
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return dn->lsu[unit] / 100;
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default:
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assert(0);
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}
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}
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#define DFP_HELPER_TAB(op, dnop, postprocs, size) \
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void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *a, uint64_t *b) \
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{ \
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@ -703,3 +720,83 @@ void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *a, \
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DFP_HELPER_QUA(dqua, 64)
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DFP_HELPER_QUA(dquaq, 128)
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static void _dfp_reround(uint8_t rmc, int32_t ref_sig, int32_t xmax,
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struct PPC_DFP *dfp)
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{
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int msd_orig, msd_rslt;
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if (unlikely((ref_sig == 0) || (dfp->b.digits <= ref_sig))) {
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dfp->t = dfp->b;
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if (decNumberIsSNaN(&dfp->b)) {
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dfp_makeQNaN(&dfp->t);
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dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXSNAN, FPSCR_VE);
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}
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return;
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}
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/* Reround is equivalent to quantizing b with 1**E(n) where */
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/* n = exp(b) + numDigits(b) - reference_significance. */
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decNumberFromUInt32(&dfp->a, 1);
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dfp->a.exponent = dfp->b.exponent + dfp->b.digits - ref_sig;
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if (unlikely(dfp->a.exponent > xmax)) {
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dfp->t.digits = 0;
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dfp->t.bits &= ~DECNEG;
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dfp_makeQNaN(&dfp->t);
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dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXCVI, FPSCR_VE);
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return;
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}
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dfp_quantize(rmc, dfp);
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msd_orig = dfp_get_digit(&dfp->b, dfp->b.digits-1);
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msd_rslt = dfp_get_digit(&dfp->t, dfp->t.digits-1);
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/* If the quantization resulted in rounding up to the next magnitude, */
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/* then we need to shift the significand and adjust the exponent. */
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if (unlikely((msd_orig == 9) && (msd_rslt == 1))) {
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decNumber negone;
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decNumberFromInt32(&negone, -1);
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decNumberShift(&dfp->t, &dfp->t, &negone, &dfp->context);
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dfp->t.exponent++;
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if (unlikely(dfp->t.exponent > xmax)) {
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dfp_makeQNaN(&dfp->t);
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dfp->t.digits = 0;
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dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXCVI, FP_VE);
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/* Inhibit XX in this case */
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decContextClearStatus(&dfp->context, DEC_Inexact);
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}
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}
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}
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#define DFP_HELPER_RRND(op, size) \
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void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *a, \
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uint64_t *b, uint32_t rmc) \
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{ \
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struct PPC_DFP dfp; \
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int32_t ref_sig = *a & 0x3F; \
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int32_t xmax = ((size) == 64) ? 369 : 6111; \
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\
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dfp_prepare_decimal##size(&dfp, 0, b, env); \
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\
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_dfp_reround(rmc, ref_sig, xmax, &dfp); \
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decimal##size##FromNumber((decimal##size *)dfp.t64, &dfp.t, \
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&dfp.context); \
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QUA_PPs(&dfp); \
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\
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if (size == 64) { \
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t[0] = dfp.t64[0]; \
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} else if (size == 128) { \
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t[0] = dfp.t64[HI_IDX]; \
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t[1] = dfp.t64[LO_IDX]; \
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} \
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}
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DFP_HELPER_RRND(drrnd, 64)
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DFP_HELPER_RRND(drrndq, 128)
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@ -640,3 +640,5 @@ DEF_HELPER_5(dquai, void, env, fprp, fprp, i32, i32)
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DEF_HELPER_5(dquaiq, void, env, fprp, fprp, i32, i32)
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DEF_HELPER_5(dqua, void, env, fprp, fprp, fprp, i32)
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DEF_HELPER_5(dquaq, void, env, fprp, fprp, fprp, i32)
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DEF_HELPER_5(drrnd, void, env, fprp, fprp, fprp, i32)
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DEF_HELPER_5(drrndq, void, env, fprp, fprp, fprp, i32)
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@ -8380,6 +8380,8 @@ GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
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GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
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GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
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GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
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GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
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GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
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/*** SPE extension ***/
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/* Register moves */
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@ -11331,6 +11333,8 @@ GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
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GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
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GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
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GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
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GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
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GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
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#undef GEN_SPE
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#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
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GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
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