mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-09-06 09:55:55 +00:00
linux-headers: Update
Update to mainline commit: d1eef1c61974 ("Linux 5.5-rc2") Signed-off-by: Bharata B Rao <bharata@linux.ibm.com> Message-Id: <20191219031445.8949-2-bharata@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
parent
bc5fdfc0a1
commit
50fd0c375b
|
@ -2,7 +2,7 @@
|
||||||
#ifndef _ASM_X86_BOOTPARAM_H
|
#ifndef _ASM_X86_BOOTPARAM_H
|
||||||
#define _ASM_X86_BOOTPARAM_H
|
#define _ASM_X86_BOOTPARAM_H
|
||||||
|
|
||||||
/* setup_data types */
|
/* setup_data/setup_indirect types */
|
||||||
#define SETUP_NONE 0
|
#define SETUP_NONE 0
|
||||||
#define SETUP_E820_EXT 1
|
#define SETUP_E820_EXT 1
|
||||||
#define SETUP_DTB 2
|
#define SETUP_DTB 2
|
||||||
|
@ -11,6 +11,11 @@
|
||||||
#define SETUP_APPLE_PROPERTIES 5
|
#define SETUP_APPLE_PROPERTIES 5
|
||||||
#define SETUP_JAILHOUSE 6
|
#define SETUP_JAILHOUSE 6
|
||||||
|
|
||||||
|
#define SETUP_INDIRECT (1<<31)
|
||||||
|
|
||||||
|
/* SETUP_INDIRECT | max(SETUP_*) */
|
||||||
|
#define SETUP_TYPE_MAX (SETUP_INDIRECT | SETUP_JAILHOUSE)
|
||||||
|
|
||||||
/* ram_size flags */
|
/* ram_size flags */
|
||||||
#define RAMDISK_IMAGE_START_MASK 0x07FF
|
#define RAMDISK_IMAGE_START_MASK 0x07FF
|
||||||
#define RAMDISK_PROMPT_FLAG 0x8000
|
#define RAMDISK_PROMPT_FLAG 0x8000
|
||||||
|
|
|
@ -58,7 +58,8 @@
|
||||||
#define PVRDMA_ROCEV1_VERSION 17
|
#define PVRDMA_ROCEV1_VERSION 17
|
||||||
#define PVRDMA_ROCEV2_VERSION 18
|
#define PVRDMA_ROCEV2_VERSION 18
|
||||||
#define PVRDMA_PPN64_VERSION 19
|
#define PVRDMA_PPN64_VERSION 19
|
||||||
#define PVRDMA_VERSION PVRDMA_PPN64_VERSION
|
#define PVRDMA_QPHANDLE_VERSION 20
|
||||||
|
#define PVRDMA_VERSION PVRDMA_QPHANDLE_VERSION
|
||||||
|
|
||||||
#define PVRDMA_BOARD_ID 1
|
#define PVRDMA_BOARD_ID 1
|
||||||
#define PVRDMA_REV_ID 1
|
#define PVRDMA_REV_ID 1
|
||||||
|
@ -581,6 +582,17 @@ struct pvrdma_cmd_create_qp_resp {
|
||||||
uint32_t max_inline_data;
|
uint32_t max_inline_data;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
struct pvrdma_cmd_create_qp_resp_v2 {
|
||||||
|
struct pvrdma_cmd_resp_hdr hdr;
|
||||||
|
uint32_t qpn;
|
||||||
|
uint32_t qp_handle;
|
||||||
|
uint32_t max_send_wr;
|
||||||
|
uint32_t max_recv_wr;
|
||||||
|
uint32_t max_send_sge;
|
||||||
|
uint32_t max_recv_sge;
|
||||||
|
uint32_t max_inline_data;
|
||||||
|
};
|
||||||
|
|
||||||
struct pvrdma_cmd_modify_qp {
|
struct pvrdma_cmd_modify_qp {
|
||||||
struct pvrdma_cmd_hdr hdr;
|
struct pvrdma_cmd_hdr hdr;
|
||||||
uint32_t qp_handle;
|
uint32_t qp_handle;
|
||||||
|
@ -663,6 +675,7 @@ union pvrdma_cmd_resp {
|
||||||
struct pvrdma_cmd_create_cq_resp create_cq_resp;
|
struct pvrdma_cmd_create_cq_resp create_cq_resp;
|
||||||
struct pvrdma_cmd_resize_cq_resp resize_cq_resp;
|
struct pvrdma_cmd_resize_cq_resp resize_cq_resp;
|
||||||
struct pvrdma_cmd_create_qp_resp create_qp_resp;
|
struct pvrdma_cmd_create_qp_resp create_qp_resp;
|
||||||
|
struct pvrdma_cmd_create_qp_resp_v2 create_qp_resp_v2;
|
||||||
struct pvrdma_cmd_query_qp_resp query_qp_resp;
|
struct pvrdma_cmd_query_qp_resp query_qp_resp;
|
||||||
struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp;
|
struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp;
|
||||||
struct pvrdma_cmd_create_srq_resp create_srq_resp;
|
struct pvrdma_cmd_create_srq_resp create_srq_resp;
|
||||||
|
|
|
@ -68,7 +68,7 @@ extern "C" {
|
||||||
#define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \
|
#define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \
|
||||||
((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
|
((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
|
||||||
|
|
||||||
#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
|
#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
|
||||||
|
|
||||||
/* Reserve 0 for the invalid format specifier */
|
/* Reserve 0 for the invalid format specifier */
|
||||||
#define DRM_FORMAT_INVALID 0
|
#define DRM_FORMAT_INVALID 0
|
||||||
|
@ -647,7 +647,21 @@ extern "C" {
|
||||||
* Further information on the use of AFBC modifiers can be found in
|
* Further information on the use of AFBC modifiers can be found in
|
||||||
* Documentation/gpu/afbc.rst
|
* Documentation/gpu/afbc.rst
|
||||||
*/
|
*/
|
||||||
#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
|
|
||||||
|
/*
|
||||||
|
* The top 4 bits (out of the 56 bits alloted for specifying vendor specific
|
||||||
|
* modifiers) denote the category for modifiers. Currently we have only two
|
||||||
|
* categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
|
||||||
|
* different categories.
|
||||||
|
*/
|
||||||
|
#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
|
||||||
|
fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
|
||||||
|
|
||||||
|
#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
|
||||||
|
#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
|
||||||
|
|
||||||
|
#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
|
||||||
|
DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* AFBC superblock size
|
* AFBC superblock size
|
||||||
|
@ -741,6 +755,16 @@ extern "C" {
|
||||||
*/
|
*/
|
||||||
#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
|
#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm 16x16 Block U-Interleaved modifier
|
||||||
|
*
|
||||||
|
* This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
|
||||||
|
* into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
|
||||||
|
* in the block are reordered.
|
||||||
|
*/
|
||||||
|
#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
|
||||||
|
DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Allwinner tiled modifier
|
* Allwinner tiled modifier
|
||||||
*
|
*
|
||||||
|
|
|
@ -649,6 +649,83 @@
|
||||||
*/
|
*/
|
||||||
#define KEY_DATA 0x277
|
#define KEY_DATA 0x277
|
||||||
#define KEY_ONSCREEN_KEYBOARD 0x278
|
#define KEY_ONSCREEN_KEYBOARD 0x278
|
||||||
|
/* Electronic privacy screen control */
|
||||||
|
#define KEY_PRIVACY_SCREEN_TOGGLE 0x279
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Some keyboards have keys which do not have a defined meaning, these keys
|
||||||
|
* are intended to be programmed / bound to macros by the user. For most
|
||||||
|
* keyboards with these macro-keys the key-sequence to inject, or action to
|
||||||
|
* take, is all handled by software on the host side. So from the kernel's
|
||||||
|
* point of view these are just normal keys.
|
||||||
|
*
|
||||||
|
* The KEY_MACRO# codes below are intended for such keys, which may be labeled
|
||||||
|
* e.g. G1-G18, or S1 - S30. The KEY_MACRO# codes MUST NOT be used for keys
|
||||||
|
* where the marking on the key does indicate a defined meaning / purpose.
|
||||||
|
*
|
||||||
|
* The KEY_MACRO# codes MUST also NOT be used as fallback for when no existing
|
||||||
|
* KEY_FOO define matches the marking / purpose. In this case a new KEY_FOO
|
||||||
|
* define MUST be added.
|
||||||
|
*/
|
||||||
|
#define KEY_MACRO1 0x290
|
||||||
|
#define KEY_MACRO2 0x291
|
||||||
|
#define KEY_MACRO3 0x292
|
||||||
|
#define KEY_MACRO4 0x293
|
||||||
|
#define KEY_MACRO5 0x294
|
||||||
|
#define KEY_MACRO6 0x295
|
||||||
|
#define KEY_MACRO7 0x296
|
||||||
|
#define KEY_MACRO8 0x297
|
||||||
|
#define KEY_MACRO9 0x298
|
||||||
|
#define KEY_MACRO10 0x299
|
||||||
|
#define KEY_MACRO11 0x29a
|
||||||
|
#define KEY_MACRO12 0x29b
|
||||||
|
#define KEY_MACRO13 0x29c
|
||||||
|
#define KEY_MACRO14 0x29d
|
||||||
|
#define KEY_MACRO15 0x29e
|
||||||
|
#define KEY_MACRO16 0x29f
|
||||||
|
#define KEY_MACRO17 0x2a0
|
||||||
|
#define KEY_MACRO18 0x2a1
|
||||||
|
#define KEY_MACRO19 0x2a2
|
||||||
|
#define KEY_MACRO20 0x2a3
|
||||||
|
#define KEY_MACRO21 0x2a4
|
||||||
|
#define KEY_MACRO22 0x2a5
|
||||||
|
#define KEY_MACRO23 0x2a6
|
||||||
|
#define KEY_MACRO24 0x2a7
|
||||||
|
#define KEY_MACRO25 0x2a8
|
||||||
|
#define KEY_MACRO26 0x2a9
|
||||||
|
#define KEY_MACRO27 0x2aa
|
||||||
|
#define KEY_MACRO28 0x2ab
|
||||||
|
#define KEY_MACRO29 0x2ac
|
||||||
|
#define KEY_MACRO30 0x2ad
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Some keyboards with the macro-keys described above have some extra keys
|
||||||
|
* for controlling the host-side software responsible for the macro handling:
|
||||||
|
* -A macro recording start/stop key. Note that not all keyboards which emit
|
||||||
|
* KEY_MACRO_RECORD_START will also emit KEY_MACRO_RECORD_STOP if
|
||||||
|
* KEY_MACRO_RECORD_STOP is not advertised, then KEY_MACRO_RECORD_START
|
||||||
|
* should be interpreted as a recording start/stop toggle;
|
||||||
|
* -Keys for switching between different macro (pre)sets, either a key for
|
||||||
|
* cycling through the configured presets or keys to directly select a preset.
|
||||||
|
*/
|
||||||
|
#define KEY_MACRO_RECORD_START 0x2b0
|
||||||
|
#define KEY_MACRO_RECORD_STOP 0x2b1
|
||||||
|
#define KEY_MACRO_PRESET_CYCLE 0x2b2
|
||||||
|
#define KEY_MACRO_PRESET1 0x2b3
|
||||||
|
#define KEY_MACRO_PRESET2 0x2b4
|
||||||
|
#define KEY_MACRO_PRESET3 0x2b5
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Some keyboards have a buildin LCD panel where the contents are controlled
|
||||||
|
* by the host. Often these have a number of keys directly below the LCD
|
||||||
|
* intended for controlling a menu shown on the LCD. These keys often don't
|
||||||
|
* have any labeling so we just name them KEY_KBD_LCD_MENU#
|
||||||
|
*/
|
||||||
|
#define KEY_KBD_LCD_MENU1 0x2b8
|
||||||
|
#define KEY_KBD_LCD_MENU2 0x2b9
|
||||||
|
#define KEY_KBD_LCD_MENU3 0x2ba
|
||||||
|
#define KEY_KBD_LCD_MENU4 0x2bb
|
||||||
|
#define KEY_KBD_LCD_MENU5 0x2bc
|
||||||
|
|
||||||
#define BTN_TRIGGER_HAPPY 0x2c0
|
#define BTN_TRIGGER_HAPPY 0x2c0
|
||||||
#define BTN_TRIGGER_HAPPY1 0x2c0
|
#define BTN_TRIGGER_HAPPY1 0x2c0
|
||||||
|
|
|
@ -34,6 +34,7 @@
|
||||||
* of which the first 64 bytes are standardized as follows:
|
* of which the first 64 bytes are standardized as follows:
|
||||||
*/
|
*/
|
||||||
#define PCI_STD_HEADER_SIZEOF 64
|
#define PCI_STD_HEADER_SIZEOF 64
|
||||||
|
#define PCI_STD_NUM_BARS 6 /* Number of standard BARs */
|
||||||
#define PCI_VENDOR_ID 0x00 /* 16 bits */
|
#define PCI_VENDOR_ID 0x00 /* 16 bits */
|
||||||
#define PCI_DEVICE_ID 0x02 /* 16 bits */
|
#define PCI_DEVICE_ID 0x02 /* 16 bits */
|
||||||
#define PCI_COMMAND 0x04 /* 16 bits */
|
#define PCI_COMMAND 0x04 /* 16 bits */
|
||||||
|
@ -673,6 +674,8 @@
|
||||||
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
|
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
|
||||||
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
|
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
|
||||||
#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
|
#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
|
||||||
|
#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
|
||||||
|
#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
|
||||||
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
|
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
|
||||||
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
|
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
|
||||||
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
|
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
|
||||||
|
|
|
@ -179,6 +179,11 @@ struct pvrdma_create_qp {
|
||||||
uint64_t __attribute__((aligned(8))) qp_addr;
|
uint64_t __attribute__((aligned(8))) qp_addr;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
struct pvrdma_create_qp_resp {
|
||||||
|
uint32_t qpn;
|
||||||
|
uint32_t qp_handle;
|
||||||
|
};
|
||||||
|
|
||||||
/* PVRDMA masked atomic compare and swap */
|
/* PVRDMA masked atomic compare and swap */
|
||||||
struct pvrdma_ex_cmp_swap {
|
struct pvrdma_ex_cmp_swap {
|
||||||
uint64_t __attribute__((aligned(8))) swap_val;
|
uint64_t __attribute__((aligned(8))) swap_val;
|
||||||
|
|
|
@ -1348,6 +1348,7 @@ struct kvm_s390_ucas_mapping {
|
||||||
#define KVM_PPC_GET_CPU_CHAR _IOR(KVMIO, 0xb1, struct kvm_ppc_cpu_char)
|
#define KVM_PPC_GET_CPU_CHAR _IOR(KVMIO, 0xb1, struct kvm_ppc_cpu_char)
|
||||||
/* Available with KVM_CAP_PMU_EVENT_FILTER */
|
/* Available with KVM_CAP_PMU_EVENT_FILTER */
|
||||||
#define KVM_SET_PMU_EVENT_FILTER _IOW(KVMIO, 0xb2, struct kvm_pmu_event_filter)
|
#define KVM_SET_PMU_EVENT_FILTER _IOW(KVMIO, 0xb2, struct kvm_pmu_event_filter)
|
||||||
|
#define KVM_PPC_SVM_OFF _IO(KVMIO, 0xb3)
|
||||||
|
|
||||||
/* ioctl for vm fd */
|
/* ioctl for vm fd */
|
||||||
#define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device)
|
#define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device)
|
||||||
|
|
Loading…
Reference in a new issue