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linux-headers: Update
Update to mainline commit: d1eef1c61974 ("Linux 5.5-rc2") Signed-off-by: Bharata B Rao <bharata@linux.ibm.com> Message-Id: <20191219031445.8949-2-bharata@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
parent
bc5fdfc0a1
commit
50fd0c375b
7 changed files with 132 additions and 4 deletions
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@ -2,7 +2,7 @@
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#ifndef _ASM_X86_BOOTPARAM_H
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#define _ASM_X86_BOOTPARAM_H
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/* setup_data types */
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/* setup_data/setup_indirect types */
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#define SETUP_NONE 0
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#define SETUP_E820_EXT 1
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#define SETUP_DTB 2
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@ -11,6 +11,11 @@
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#define SETUP_APPLE_PROPERTIES 5
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#define SETUP_JAILHOUSE 6
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#define SETUP_INDIRECT (1<<31)
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/* SETUP_INDIRECT | max(SETUP_*) */
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#define SETUP_TYPE_MAX (SETUP_INDIRECT | SETUP_JAILHOUSE)
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/* ram_size flags */
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#define RAMDISK_IMAGE_START_MASK 0x07FF
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#define RAMDISK_PROMPT_FLAG 0x8000
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@ -58,7 +58,8 @@
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#define PVRDMA_ROCEV1_VERSION 17
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#define PVRDMA_ROCEV2_VERSION 18
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#define PVRDMA_PPN64_VERSION 19
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#define PVRDMA_VERSION PVRDMA_PPN64_VERSION
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#define PVRDMA_QPHANDLE_VERSION 20
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#define PVRDMA_VERSION PVRDMA_QPHANDLE_VERSION
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#define PVRDMA_BOARD_ID 1
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#define PVRDMA_REV_ID 1
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@ -581,6 +582,17 @@ struct pvrdma_cmd_create_qp_resp {
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uint32_t max_inline_data;
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};
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struct pvrdma_cmd_create_qp_resp_v2 {
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struct pvrdma_cmd_resp_hdr hdr;
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uint32_t qpn;
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uint32_t qp_handle;
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uint32_t max_send_wr;
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uint32_t max_recv_wr;
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uint32_t max_send_sge;
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uint32_t max_recv_sge;
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uint32_t max_inline_data;
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};
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struct pvrdma_cmd_modify_qp {
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struct pvrdma_cmd_hdr hdr;
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uint32_t qp_handle;
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@ -663,6 +675,7 @@ union pvrdma_cmd_resp {
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struct pvrdma_cmd_create_cq_resp create_cq_resp;
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struct pvrdma_cmd_resize_cq_resp resize_cq_resp;
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struct pvrdma_cmd_create_qp_resp create_qp_resp;
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struct pvrdma_cmd_create_qp_resp_v2 create_qp_resp_v2;
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struct pvrdma_cmd_query_qp_resp query_qp_resp;
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struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp;
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struct pvrdma_cmd_create_srq_resp create_srq_resp;
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@ -68,7 +68,7 @@ extern "C" {
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#define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \
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((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
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#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
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#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
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/* Reserve 0 for the invalid format specifier */
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#define DRM_FORMAT_INVALID 0
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@ -647,7 +647,21 @@ extern "C" {
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* Further information on the use of AFBC modifiers can be found in
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* Documentation/gpu/afbc.rst
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*/
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#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
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/*
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* The top 4 bits (out of the 56 bits alloted for specifying vendor specific
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* modifiers) denote the category for modifiers. Currently we have only two
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* categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
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* different categories.
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*/
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#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
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fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
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#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
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#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
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#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
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DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
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/*
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* AFBC superblock size
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@ -741,6 +755,16 @@ extern "C" {
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*/
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#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
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/*
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* Arm 16x16 Block U-Interleaved modifier
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*
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* This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
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* into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
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* in the block are reordered.
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*/
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#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
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DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
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/*
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* Allwinner tiled modifier
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*
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@ -649,6 +649,83 @@
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*/
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#define KEY_DATA 0x277
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#define KEY_ONSCREEN_KEYBOARD 0x278
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/* Electronic privacy screen control */
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#define KEY_PRIVACY_SCREEN_TOGGLE 0x279
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/*
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* Some keyboards have keys which do not have a defined meaning, these keys
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* are intended to be programmed / bound to macros by the user. For most
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* keyboards with these macro-keys the key-sequence to inject, or action to
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* take, is all handled by software on the host side. So from the kernel's
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* point of view these are just normal keys.
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*
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* The KEY_MACRO# codes below are intended for such keys, which may be labeled
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* e.g. G1-G18, or S1 - S30. The KEY_MACRO# codes MUST NOT be used for keys
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* where the marking on the key does indicate a defined meaning / purpose.
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*
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* The KEY_MACRO# codes MUST also NOT be used as fallback for when no existing
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* KEY_FOO define matches the marking / purpose. In this case a new KEY_FOO
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* define MUST be added.
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*/
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#define KEY_MACRO1 0x290
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#define KEY_MACRO2 0x291
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#define KEY_MACRO3 0x292
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#define KEY_MACRO4 0x293
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#define KEY_MACRO5 0x294
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#define KEY_MACRO6 0x295
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#define KEY_MACRO7 0x296
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#define KEY_MACRO8 0x297
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#define KEY_MACRO9 0x298
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#define KEY_MACRO10 0x299
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#define KEY_MACRO11 0x29a
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#define KEY_MACRO12 0x29b
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#define KEY_MACRO13 0x29c
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#define KEY_MACRO14 0x29d
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#define KEY_MACRO15 0x29e
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#define KEY_MACRO16 0x29f
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#define KEY_MACRO17 0x2a0
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#define KEY_MACRO18 0x2a1
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#define KEY_MACRO19 0x2a2
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#define KEY_MACRO20 0x2a3
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#define KEY_MACRO21 0x2a4
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#define KEY_MACRO22 0x2a5
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#define KEY_MACRO23 0x2a6
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#define KEY_MACRO24 0x2a7
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#define KEY_MACRO25 0x2a8
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#define KEY_MACRO26 0x2a9
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#define KEY_MACRO27 0x2aa
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#define KEY_MACRO28 0x2ab
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#define KEY_MACRO29 0x2ac
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#define KEY_MACRO30 0x2ad
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/*
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* Some keyboards with the macro-keys described above have some extra keys
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* for controlling the host-side software responsible for the macro handling:
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* -A macro recording start/stop key. Note that not all keyboards which emit
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* KEY_MACRO_RECORD_START will also emit KEY_MACRO_RECORD_STOP if
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* KEY_MACRO_RECORD_STOP is not advertised, then KEY_MACRO_RECORD_START
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* should be interpreted as a recording start/stop toggle;
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* -Keys for switching between different macro (pre)sets, either a key for
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* cycling through the configured presets or keys to directly select a preset.
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*/
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#define KEY_MACRO_RECORD_START 0x2b0
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#define KEY_MACRO_RECORD_STOP 0x2b1
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#define KEY_MACRO_PRESET_CYCLE 0x2b2
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#define KEY_MACRO_PRESET1 0x2b3
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#define KEY_MACRO_PRESET2 0x2b4
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#define KEY_MACRO_PRESET3 0x2b5
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/*
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* Some keyboards have a buildin LCD panel where the contents are controlled
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* by the host. Often these have a number of keys directly below the LCD
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* intended for controlling a menu shown on the LCD. These keys often don't
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* have any labeling so we just name them KEY_KBD_LCD_MENU#
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*/
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#define KEY_KBD_LCD_MENU1 0x2b8
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#define KEY_KBD_LCD_MENU2 0x2b9
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#define KEY_KBD_LCD_MENU3 0x2ba
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#define KEY_KBD_LCD_MENU4 0x2bb
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#define KEY_KBD_LCD_MENU5 0x2bc
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#define BTN_TRIGGER_HAPPY 0x2c0
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#define BTN_TRIGGER_HAPPY1 0x2c0
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@ -34,6 +34,7 @@
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* of which the first 64 bytes are standardized as follows:
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*/
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#define PCI_STD_HEADER_SIZEOF 64
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#define PCI_STD_NUM_BARS 6 /* Number of standard BARs */
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#define PCI_VENDOR_ID 0x00 /* 16 bits */
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#define PCI_DEVICE_ID 0x02 /* 16 bits */
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#define PCI_COMMAND 0x04 /* 16 bits */
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#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
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#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
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#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
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#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
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#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
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#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
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#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
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#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
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@ -179,6 +179,11 @@ struct pvrdma_create_qp {
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uint64_t __attribute__((aligned(8))) qp_addr;
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};
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struct pvrdma_create_qp_resp {
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uint32_t qpn;
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uint32_t qp_handle;
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};
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/* PVRDMA masked atomic compare and swap */
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struct pvrdma_ex_cmp_swap {
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uint64_t __attribute__((aligned(8))) swap_val;
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@ -1348,6 +1348,7 @@ struct kvm_s390_ucas_mapping {
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#define KVM_PPC_GET_CPU_CHAR _IOR(KVMIO, 0xb1, struct kvm_ppc_cpu_char)
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/* Available with KVM_CAP_PMU_EVENT_FILTER */
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#define KVM_SET_PMU_EVENT_FILTER _IOW(KVMIO, 0xb2, struct kvm_pmu_event_filter)
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#define KVM_PPC_SVM_OFF _IO(KVMIO, 0xb3)
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/* ioctl for vm fd */
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#define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device)
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