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target/riscv: rvv-1.0: mask-register logical instructions

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Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-50-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2021-12-10 15:56:35 +08:00 committed by Alistair Francis
parent e70aa16e5e
commit 50f6696c0f
2 changed files with 2 additions and 5 deletions
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3
target/riscv/insn_trans/trans_rvv.c.inc
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@ -2652,7 +2652,8 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
#define GEN_MM_TRANS(NAME) \ #define GEN_MM_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_r *a) \ static bool trans_##NAME(DisasContext *s, arg_r *a) \
{ \ { \
if (vext_check_isa_ill(s)) { \ if (require_rvv(s) && \
vext_check_isa_ill(s)) { \
uint32_t data = 0; \ uint32_t data = 0; \
gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \ gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
TCGLabel *over = gen_new_label(); \ TCGLabel *over = gen_new_label(); \

4
target/riscv/vector_helper.c
View file

@ -4231,7 +4231,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \ void *vs2, CPURISCVState *env, \
uint32_t desc) \ uint32_t desc) \
{ \ { \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vl = env->vl; \ uint32_t vl = env->vl; \
uint32_t i; \ uint32_t i; \
int a, b; \ int a, b; \
@ -4241,9 +4240,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
b = vext_elem_mask(vs2, i); \ b = vext_elem_mask(vs2, i); \
vext_set_elem_mask(vd, i, OP(b, a)); \ vext_set_elem_mask(vd, i, OP(b, a)); \
} \ } \
for (; i < vlmax; i++) { \
vext_set_elem_mask(vd, i, 0); \
} \
} }
#define DO_NAND(N, M) (!(N & M)) #define DO_NAND(N, M) (!(N & M))