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https://gitlab.com/qemu-project/qemu
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target/arm: Implement MVE VLDR/VSTR (non-widening forms)
Implement the forms of the MVE VLDR and VSTR insns which perform non-widening loads of bytes, halfwords or words from memory into vector elements of the same width (encodings T5, T6, T7). (At the moment we know for MVE and M-profile in general that vfp_access_check() can never return false, but we include the conventional return-true-on-failure check for consistency with non-M-profile translation code.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-2-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
88137f787f
commit
507b6a500c
7 changed files with 351 additions and 0 deletions
24
target/arm/helper-mve.h
Normal file
24
target/arm/helper-mve.h
Normal file
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@ -0,0 +1,24 @@
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/*
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* M-profile MVE specific helper definitions
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*
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* Copyright (c) 2021 Linaro, Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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DEF_HELPER_FLAGS_3(mve_vldrb, TCG_CALL_NO_WG, void, env, ptr, i32)
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DEF_HELPER_FLAGS_3(mve_vldrh, TCG_CALL_NO_WG, void, env, ptr, i32)
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DEF_HELPER_FLAGS_3(mve_vldrw, TCG_CALL_NO_WG, void, env, ptr, i32)
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DEF_HELPER_FLAGS_3(mve_vstrb, TCG_CALL_NO_WG, void, env, ptr, i32)
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DEF_HELPER_FLAGS_3(mve_vstrh, TCG_CALL_NO_WG, void, env, ptr, i32)
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DEF_HELPER_FLAGS_3(mve_vstrw, TCG_CALL_NO_WG, void, env, ptr, i32)
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@ -1019,3 +1019,5 @@ DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG,
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#include "helper-a64.h"
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#include "helper-sve.h"
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#endif
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#include "helper-mve.h"
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@ -1202,4 +1202,15 @@ static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr)
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return ptr;
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}
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/* Values for M-profile PSR.ECI for MVE insns */
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enum MVEECIState {
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ECI_NONE = 0, /* No completed beats */
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ECI_A0 = 1, /* Completed: A0 */
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ECI_A0A1 = 2, /* Completed: A0, A1 */
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/* 3 is reserved */
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ECI_A0A1A2 = 4, /* Completed: A0, A1, A2 */
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ECI_A0A1A2B0 = 5, /* Completed: A0, A1, A2, B0 */
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/* All other values reserved */
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};
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#endif
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@ -23,6 +23,7 @@ arm_ss.add(files(
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'helper.c',
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'iwmmxt_helper.c',
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'm_helper.c',
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'mve_helper.c',
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'neon_helper.c',
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'op_helper.c',
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'tlb_helper.c',
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@ -18,3 +18,25 @@
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#
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# This file is processed by scripts/decodetree.py
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#
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%qd 22:1 13:3
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&vldr_vstr rn qd imm p a w size l
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@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd
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# Vector loads and stores
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# Non-widening loads/stores (P=0 W=0 is 'related encoding')
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VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111100 ....... @vldr_vstr \
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size=0 p=0 w=1
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VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111101 ....... @vldr_vstr \
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size=1 p=0 w=1
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VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111110 ....... @vldr_vstr \
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size=2 p=0 w=1
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VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111100 ....... @vldr_vstr \
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size=0 p=1
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VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101 ....... @vldr_vstr \
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size=1 p=1
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VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \
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size=2 p=1
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172
target/arm/mve_helper.c
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172
target/arm/mve_helper.c
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@ -0,0 +1,172 @@
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/*
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* M-profile MVE Operations
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*
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* Copyright (c) 2021 Linaro, Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internals.h"
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#include "vec_internal.h"
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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#include "exec/exec-all.h"
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static uint16_t mve_element_mask(CPUARMState *env)
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{
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/*
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* Return the mask of which elements in the MVE vector should be
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* updated. This is a combination of multiple things:
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* (1) by default, we update every lane in the vector
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* (2) VPT predication stores its state in the VPR register;
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* (3) low-overhead-branch tail predication will mask out part
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* the vector on the final iteration of the loop
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* (4) if EPSR.ECI is set then we must execute only some beats
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* of the insn
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* We combine all these into a 16-bit result with the same semantics
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* as VPR.P0: 0 to mask the lane, 1 if it is active.
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* 8-bit vector ops will look at all bits of the result;
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* 16-bit ops will look at bits 0, 2, 4, ...;
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* 32-bit ops will look at bits 0, 4, 8 and 12.
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* Compare pseudocode GetCurInstrBeat(), though that only returns
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* the 4-bit slice of the mask corresponding to a single beat.
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*/
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uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0);
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if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) {
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mask |= 0xff;
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}
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if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) {
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mask |= 0xff00;
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}
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if (env->v7m.ltpsize < 4 &&
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env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) {
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/*
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* Tail predication active, and this is the last loop iteration.
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* The element size is (1 << ltpsize), and we only want to process
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* loopcount elements, so we want to retain the least significant
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* (loopcount * esize) predicate bits and zero out bits above that.
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*/
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int masklen = env->regs[14] << env->v7m.ltpsize;
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assert(masklen <= 16);
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mask &= MAKE_64BIT_MASK(0, masklen);
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}
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if ((env->condexec_bits & 0xf) == 0) {
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/*
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* ECI bits indicate which beats are already executed;
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* we handle this by effectively predicating them out.
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*/
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int eci = env->condexec_bits >> 4;
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switch (eci) {
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case ECI_NONE:
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break;
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case ECI_A0:
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mask &= 0xfff0;
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break;
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case ECI_A0A1:
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mask &= 0xff00;
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break;
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case ECI_A0A1A2:
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case ECI_A0A1A2B0:
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mask &= 0xf000;
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break;
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default:
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g_assert_not_reached();
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}
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}
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return mask;
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}
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static void mve_advance_vpt(CPUARMState *env)
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{
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/* Advance the VPT and ECI state if necessary */
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uint32_t vpr = env->v7m.vpr;
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unsigned mask01, mask23;
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if ((env->condexec_bits & 0xf) == 0) {
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env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ?
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(ECI_A0 << 4) : (ECI_NONE << 4);
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}
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if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) {
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/* VPT not enabled, nothing to do */
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return;
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}
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mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01);
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mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23);
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if (mask01 > 8) {
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/* high bit set, but not 0b1000: invert the relevant half of P0 */
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vpr ^= 0xff;
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}
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if (mask23 > 8) {
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/* high bit set, but not 0b1000: invert the relevant half of P0 */
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vpr ^= 0xff00;
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}
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vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1);
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vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1);
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env->v7m.vpr = vpr;
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}
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#define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \
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void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \
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{ \
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TYPE *d = vd; \
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uint16_t mask = mve_element_mask(env); \
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unsigned b, e; \
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/* \
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* R_SXTM allows the dest reg to become UNKNOWN for abandoned \
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* beats so we don't care if we update part of the dest and \
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* then take an exception. \
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*/ \
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for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \
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if (mask & (1 << b)) { \
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d[H##ESIZE(e)] = cpu_##LDTYPE##_data_ra(env, addr, GETPC()); \
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} \
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addr += MSIZE; \
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} \
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mve_advance_vpt(env); \
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}
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#define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \
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void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \
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{ \
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TYPE *d = vd; \
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uint16_t mask = mve_element_mask(env); \
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unsigned b, e; \
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for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \
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if (mask & (1 << b)) { \
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cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \
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} \
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addr += MSIZE; \
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} \
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mve_advance_vpt(env); \
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}
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DO_VLDR(vldrb, 1, ldub, 1, uint8_t)
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DO_VLDR(vldrh, 2, lduw, 2, uint16_t)
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DO_VLDR(vldrw, 4, ldl, 4, uint32_t)
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DO_VSTR(vstrb, 1, stb, 1, uint8_t)
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DO_VSTR(vstrh, 2, stw, 2, uint16_t)
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DO_VSTR(vstrw, 4, stl, 4, uint32_t)
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#undef DO_VLDR
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#undef DO_VSTR
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@ -27,3 +27,122 @@
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/* Include the generated decoder */
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#include "decode-mve.c.inc"
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typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
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/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
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static inline long mve_qreg_offset(unsigned reg)
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{
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return offsetof(CPUARMState, vfp.zregs[reg].d[0]);
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}
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static TCGv_ptr mve_qreg_ptr(unsigned reg)
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{
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TCGv_ptr ret = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg));
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return ret;
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}
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static bool mve_check_qreg_bank(DisasContext *s, int qmask)
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{
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/*
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* Check whether Qregs are in range. For v8.1M only Q0..Q7
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* are supported, see VFPSmallRegisterBank().
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*/
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return qmask < 8;
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}
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static bool mve_eci_check(DisasContext *s)
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{
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/*
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* This is a beatwise insn: check that ECI is valid (not a
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* reserved value) and note that we are handling it.
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* Return true if OK, false if we generated an exception.
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*/
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s->eci_handled = true;
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switch (s->eci) {
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case ECI_NONE:
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case ECI_A0:
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case ECI_A0A1:
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case ECI_A0A1A2:
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case ECI_A0A1A2B0:
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return true;
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default:
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/* Reserved value: INVSTATE UsageFault */
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gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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default_exception_el(s));
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return false;
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}
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}
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static void mve_update_eci(DisasContext *s)
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{
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/*
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* The helper function will always update the CPUState field,
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* so we only need to update the DisasContext field.
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*/
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if (s->eci) {
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s->eci = (s->eci == ECI_A0A1A2B0) ? ECI_A0 : ECI_NONE;
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}
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}
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static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
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{
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TCGv_i32 addr;
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uint32_t offset;
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TCGv_ptr qreg;
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if (!dc_isar_feature(aa32_mve, s) ||
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!mve_check_qreg_bank(s, a->qd) ||
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!fn) {
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return false;
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}
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/* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */
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if (a->rn == 15 || (a->rn == 13 && a->w)) {
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return false;
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}
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if (!mve_eci_check(s) || !vfp_access_check(s)) {
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return true;
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}
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offset = a->imm << a->size;
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if (!a->a) {
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offset = -offset;
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}
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addr = load_reg(s, a->rn);
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if (a->p) {
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tcg_gen_addi_i32(addr, addr, offset);
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}
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qreg = mve_qreg_ptr(a->qd);
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fn(cpu_env, qreg, addr);
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tcg_temp_free_ptr(qreg);
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/*
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* Writeback always happens after the last beat of the insn,
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* regardless of predication
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*/
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if (a->w) {
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if (!a->p) {
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tcg_gen_addi_i32(addr, addr, offset);
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}
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store_reg(s, a->rn, addr);
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} else {
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tcg_temp_free_i32(addr);
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}
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mve_update_eci(s);
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return true;
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}
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static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
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{
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static MVEGenLdStFn * const ldstfns[4][2] = {
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{ gen_helper_mve_vstrb, gen_helper_mve_vldrb },
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{ gen_helper_mve_vstrh, gen_helper_mve_vldrh },
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{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
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{ NULL, NULL }
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};
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return do_ldst(s, a, ldstfns[a->size][a->l]);
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}
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