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hw/onenand: Qdevify

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Qdevify the ONENAND device.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
[Riku Voipio: Fixes and restructuring patchset]
Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
[Peter Maydell: More fixes and cleanups for upstream submission]
Signed-off-by:  Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Juha Riihimäki 2011-08-28 16:22:17 +00:00 committed by Peter Maydell
parent 82866965e9
commit 500954e35c
3 changed files with 133 additions and 53 deletions
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7
hw/flash.h
View file

@ -36,12 +36,7 @@ uint32_t nand_getbuswidth(DeviceState *dev);
#define NAND_MFR_MICRON 0x2c
/* onenand.c */
void onenand_base_update(void *opaque, target_phys_addr_t new);
void onenand_base_unmap(void *opaque);
void *onenand_init(BlockDriverState *bdrv,
uint16_t man_id, uint16_t dev_id, uint16_t ver_id,
int regshift, qemu_irq irq);
void *onenand_raw_otp(void *opaque);
void *onenand_raw_otp(DeviceState *onenand_device);
/* ecc.c */
typedef struct {

25
hw/nseries.c
View file

@ -33,6 +33,7 @@
#include "loader.h"
#include "blockdev.h"
#include "tusb6010.h"
#include "sysbus.h"
/* Nokia N8x0 support */
struct n800_s {
@ -52,7 +53,7 @@ struct n800_s {
TUSBState *usb;
void *retu;
void *tahvo;
void *nand;
DeviceState *nand;
};
/* GPIO pins */
@ -167,13 +168,23 @@ static void n8x0_nand_setup(struct n800_s *s)
char *otp_region;
DriveInfo *dinfo;
dinfo = drive_get(IF_MTD, 0, 0);
s->nand = qdev_create(NULL, "onenand");
qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
/* Either 0x40 or 0x48 are OK for the device ID */
s->nand = onenand_init(dinfo ? dinfo->bdrv : 0,
NAND_MFR_SAMSUNG, 0x48, 0, 1,
qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
onenand_base_unmap, s->nand);
qdev_prop_set_uint16(s->nand, "device_id", 0x48);
qdev_prop_set_uint16(s->nand, "version_id", 0);
qdev_prop_set_int32(s->nand, "shift", 1);
dinfo = drive_get(IF_MTD, 0, 0);
if (dinfo && dinfo->bdrv) {
qdev_prop_set_drive_nofail(s->nand, "drive", dinfo->bdrv);
}
qdev_init_nofail(s->nand);
sysbus_connect_irq(sysbus_from_qdev(s->nand), 0,
qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS,
sysbus_mmio_get_region(sysbus_from_qdev(s->nand), 0),
NULL, NULL,
s->nand);
otp_region = onenand_raw_otp(s->nand);
memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));

154
hw/onenand.c
View file

@ -25,6 +25,7 @@
#include "blockdev.h"
#include "memory.h"
#include "exec-memory.h"
#include "sysbus.h"
/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
#define PAGE_SHIFT 11
@ -33,6 +34,7 @@
#define BLOCK_SHIFT (PAGE_SHIFT + 6)
typedef struct {
SysBusDevice busdev;
struct {
uint16_t man;
uint16_t dev;
@ -49,6 +51,7 @@ typedef struct {
uint8_t *current;
MemoryRegion ram;
MemoryRegion mapped_ram;
uint8_t current_direction;
uint8_t *boot[2];
uint8_t *data[2][2];
MemoryRegion iomem;
@ -120,27 +123,72 @@ static void onenand_mem_setup(OneNANDState *s)
1);
}
void onenand_base_update(void *opaque, target_phys_addr_t new)
{
OneNANDState *s = (OneNANDState *) opaque;
s->base = new;
memory_region_add_subregion(get_system_memory(), s->base, &s->container);
}
void onenand_base_unmap(void *opaque)
{
OneNANDState *s = (OneNANDState *) opaque;
memory_region_del_subregion(get_system_memory(), &s->container);
}
static void onenand_intr_update(OneNANDState *s)
{
qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1);
}
static void onenand_pre_save(void *opaque)
{
OneNANDState *s = opaque;
if (s->current == s->otp) {
s->current_direction = 1;
} else if (s->current == s->image) {
s->current_direction = 2;
} else {
s->current_direction = 0;
}
}
static int onenand_post_load(void *opaque, int version_id)
{
OneNANDState *s = opaque;
switch (s->current_direction) {
case 0:
break;
case 1:
s->current = s->otp;
break;
case 2:
s->current = s->image;
break;
default:
return -1;
}
onenand_intr_update(s);
return 0;
}
static const VMStateDescription vmstate_onenand = {
.name = "onenand",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.pre_save = onenand_pre_save,
.post_load = onenand_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT8(current_direction, OneNANDState),
VMSTATE_INT32(cycle, OneNANDState),
VMSTATE_INT32(otpmode, OneNANDState),
VMSTATE_UINT16_ARRAY(addr, OneNANDState, 8),
VMSTATE_UINT16_ARRAY(unladdr, OneNANDState, 8),
VMSTATE_INT32(bufaddr, OneNANDState),
VMSTATE_INT32(count, OneNANDState),
VMSTATE_UINT16(command, OneNANDState),
VMSTATE_UINT16_ARRAY(config, OneNANDState, 2),
VMSTATE_UINT16(status, OneNANDState),
VMSTATE_UINT16(intstatus, OneNANDState),
VMSTATE_UINT16(wpstatus, OneNANDState),
VMSTATE_INT32(secs_cur, OneNANDState),
VMSTATE_PARTIAL_VBUFFER(blockwp, OneNANDState, blocks),
VMSTATE_UINT8(ecc.cp, OneNANDState),
VMSTATE_UINT16_ARRAY(ecc.lp, OneNANDState, 2),
VMSTATE_UINT16(ecc.count, OneNANDState),
VMSTATE_BUFFER_UNSAFE(otp, OneNANDState, 0, ((64 + 2) << PAGE_SHIFT)),
VMSTATE_END_OF_LIST()
}
};
/* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
static void onenand_reset(OneNANDState *s, int cold)
{
@ -167,11 +215,17 @@ static void onenand_reset(OneNANDState *s, int cold)
/* Lock the whole flash */
memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks);
if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0)
hw_error("%s: Loading the BootRAM failed.\n", __FUNCTION__);
if (s->bdrv_cur && bdrv_read(s->bdrv_cur, 0, s->boot[0], 8) < 0) {
hw_error("%s: Loading the BootRAM failed.\n", __func__);
}
}
}
static void onenand_system_reset(DeviceState *dev)
{
onenand_reset(FROM_SYSBUS(OneNANDState, sysbus_from_qdev(dev)), 1);
}
static inline int onenand_load_main(OneNANDState *s, int sec, int secn,
void *dest)
{
@ -700,30 +754,25 @@ static const MemoryRegionOps onenand_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
void *onenand_init(BlockDriverState *bdrv,
uint16_t man_id, uint16_t dev_id, uint16_t ver_id,
int regshift, qemu_irq irq)
static int onenand_initfn(SysBusDevice *dev)
{
OneNANDState *s = (OneNANDState *) g_malloc0(sizeof(*s));
uint32_t size = 1 << (24 + ((dev_id >> 4) & 7));
OneNANDState *s = (OneNANDState *)dev;
uint32_t size = 1 << (24 + ((s->id.dev >> 4) & 7));
void *ram;
s->shift = regshift;
s->intr = irq;
s->base = (target_phys_addr_t)-1;
s->rdy = NULL;
s->id.man = man_id;
s->id.dev = dev_id;
s->id.ver = ver_id;
s->blocks = size >> BLOCK_SHIFT;
s->secs = size >> 9;
s->blockwp = g_malloc(s->blocks);
s->density_mask = (dev_id & 0x08) ? (1 << (6 + ((dev_id >> 4) & 7))) : 0;
s->density_mask = (s->id.dev & 0x08)
? (1 << (6 + ((s->id.dev >> 4) & 7))) : 0;
memory_region_init_io(&s->iomem, &onenand_ops, s, "onenand",
0x10000 << s->shift);
s->bdrv = bdrv;
if (!s->bdrv) {
s->image = memset(g_malloc(size + (size >> 5)),
0xff, size + (size >> 5));
0xff, size + (size >> 5));
} else {
s->bdrv_cur = s->bdrv;
}
s->otp = memset(g_malloc((64 + 2) << PAGE_SHIFT),
0xff, (64 + 2) << PAGE_SHIFT);
@ -736,15 +785,40 @@ void *onenand_init(BlockDriverState *bdrv,
s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift);
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift);
onenand_mem_setup(s);
onenand_reset(s, 1);
return s;
sysbus_init_irq(dev, &s->intr);
sysbus_init_mmio_region(dev, &s->container);
vmstate_register(&dev->qdev,
((s->shift & 0x7f) << 24)
| ((s->id.man & 0xff) << 16)
| ((s->id.dev & 0xff) << 8)
| (s->id.ver & 0xff),
&vmstate_onenand, s);
return 0;
}
void *onenand_raw_otp(void *opaque)
static SysBusDeviceInfo onenand_info = {
.init = onenand_initfn,
.qdev.name = "onenand",
.qdev.size = sizeof(OneNANDState),
.qdev.reset = onenand_system_reset,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT16("manufacturer_id", OneNANDState, id.man, 0),
DEFINE_PROP_UINT16("device_id", OneNANDState, id.dev, 0),
DEFINE_PROP_UINT16("version_id", OneNANDState, id.ver, 0),
DEFINE_PROP_INT32("shift", OneNANDState, shift, 0),
DEFINE_PROP_DRIVE("drive", OneNANDState, bdrv),
DEFINE_PROP_END_OF_LIST()
}
};
static void onenand_register_device(void)
{
OneNANDState *s = (OneNANDState *) opaque;
return s->otp;
sysbus_register_withprop(&onenand_info);
}
void *onenand_raw_otp(DeviceState *onenand_device)
{
return FROM_SYSBUS(OneNANDState, sysbus_from_qdev(onenand_device))->otp;
}
device_init(onenand_register_device)