system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-10-17 08:23:02 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Split out aarch32_cpsr_valid_mask

Browse source 
Split this helper out of msr_mask in translate.c.  At the same time,
transform the negative reductive logic to positive accumulative logic.
It will be usable along the exception paths.

While touching msr_mask, fix up formatting.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200208125816.14954-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-08 12:58:01 +00:00 committed by Peter Maydell
parent d8564ee4e5
commit 4f9584ed4b
2 changed files with 38 additions and 23 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
target/arm/internals.h
View file

@ -1061,6 +1061,27 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx)
}
}
static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
const ARMISARegisters *id)
{
uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV | CPSR_J;
if ((features >> ARM_FEATURE_V4T) & 1) {
valid |= CPSR_T;
}
if ((features >> ARM_FEATURE_V5) & 1) {
valid |= CPSR_Q; /* V5TE in reality*/
}
if ((features >> ARM_FEATURE_V6) & 1) {
valid |= CPSR_E | CPSR_GE;
}
if ((features >> ARM_FEATURE_THUMB2) & 1) {
valid |= CPSR_IT;
}
return valid;
}
/*
* Parameters of a given virtual address, as extracted from the
* translation control register (TCR) for a given regime.

40
target/arm/translate.c
View file

@ -2734,39 +2734,33 @@ static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y)
/* Return the mask of PSR bits set by a MSR instruction. */
static uint32_t msr_mask(DisasContext *s, int flags, int spsr)
{
uint32_t mask;
uint32_t mask = 0;
mask = 0;
if (flags & (1 << 0))
if (flags & (1 << 0)) {
mask |= 0xff;
if (flags & (1 << 1))
}
if (flags & (1 << 1)) {
mask |= 0xff00;
if (flags & (1 << 2))
}
if (flags & (1 << 2)) {
mask |= 0xff0000;
if (flags & (1 << 3))
}
if (flags & (1 << 3)) {
mask |= 0xff000000;
}
/* Mask out undefined bits. */
mask &= ~CPSR_RESERVED;
if (!arm_dc_feature(s, ARM_FEATURE_V4T)) {
mask &= ~CPSR_T;
}
if (!arm_dc_feature(s, ARM_FEATURE_V5)) {
mask &= ~CPSR_Q; /* V5TE in reality*/
}
if (!arm_dc_feature(s, ARM_FEATURE_V6)) {
mask &= ~(CPSR_E | CPSR_GE);
}
if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
mask &= ~CPSR_IT;
}
/* Mask out execution state and reserved bits. */
/* Mask out undefined and reserved bits. */
mask &= aarch32_cpsr_valid_mask(s->features, s->isar);
/* Mask out execution state. */
if (!spsr) {
mask &= ~(CPSR_EXEC | CPSR_RESERVED);
mask &= ~CPSR_EXEC;
}
/* Mask out privileged bits. */
if (IS_USER(s))
if (IS_USER(s)) {
mask &= CPSR_USER;
}
return mask;
}