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uninorth: trivial style fixups
This makes sure we keep patchew/checkpatch happy during the remainder of this patchset. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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parent
ca92651697
commit
4d309c9663
1 changed files with 19 additions and 10 deletions
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@ -272,7 +272,6 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
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UNINState *d;
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/* Uninorth AGP bus */
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dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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@ -302,16 +301,23 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
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static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
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{
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x10; // latency_timer
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d->config[0x34] = 0x00; // capabilities_pointer
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/* cache_line_size */
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d->config[0x0C] = 0x08;
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/* latency_timer */
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d->config[0x0D] = 0x10;
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/* capabilities_pointer */
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d->config[0x34] = 0x00;
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}
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static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
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{
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x10; // latency_timer
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// d->config[0x34] = 0x80; // capabilities_pointer
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/* cache_line_size */
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d->config[0x0C] = 0x08;
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/* latency_timer */
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d->config[0x0D] = 0x10;
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/* capabilities_pointer
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d->config[0x34] = 0x80; */
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/*
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* Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
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* memory space with base 0x80000000, size 0x10000000 for Apple's
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@ -333,9 +339,12 @@ static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
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static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
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{
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x10; // latency_timer
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d->config[0x34] = 0x00; // capabilities_pointer
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/* cache_line_size */
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d->config[0x0C] = 0x08;
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/* latency_timer */
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d->config[0x0D] = 0x10;
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/* capabilities_pointer */
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d->config[0x34] = 0x00;
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}
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static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
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