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https://gitlab.com/qemu-project/qemu
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target/loongarch: Implement vdiv/vmod
This patch includes:
- VDIV.{B/H/W/D}[U];
- VMOD.{B/H/W/D}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-17-gaosong@loongson.cn>
This commit is contained in:
Song Gao
parent
d3aec65bc1
commit
4cc4c0f78b
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@ -1044,3 +1044,20 @@ INSN_LSX(vmaddwod_h_bu_b, vvv)
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INSN_LSX(vmaddwod_w_hu_h, vvv)
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INSN_LSX(vmaddwod_d_wu_w, vvv)
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INSN_LSX(vmaddwod_q_du_d, vvv)
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INSN_LSX(vdiv_b, vvv)
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INSN_LSX(vdiv_h, vvv)
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INSN_LSX(vdiv_w, vvv)
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INSN_LSX(vdiv_d, vvv)
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INSN_LSX(vdiv_bu, vvv)
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INSN_LSX(vdiv_hu, vvv)
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INSN_LSX(vdiv_wu, vvv)
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INSN_LSX(vdiv_du, vvv)
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INSN_LSX(vmod_b, vvv)
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INSN_LSX(vmod_h, vvv)
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INSN_LSX(vmod_w, vvv)
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INSN_LSX(vmod_d, vvv)
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INSN_LSX(vmod_bu, vvv)
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INSN_LSX(vmod_hu, vvv)
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INSN_LSX(vmod_wu, vvv)
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INSN_LSX(vmod_du, vvv)
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@ -303,3 +303,20 @@ DEF_HELPER_FLAGS_4(vmaddwev_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(vmaddwod_h_bu_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(vmaddwod_w_hu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(vmaddwod_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_4(vdiv_b, void, env, i32, i32, i32)
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DEF_HELPER_4(vdiv_h, void, env, i32, i32, i32)
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DEF_HELPER_4(vdiv_w, void, env, i32, i32, i32)
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DEF_HELPER_4(vdiv_d, void, env, i32, i32, i32)
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DEF_HELPER_4(vdiv_bu, void, env, i32, i32, i32)
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DEF_HELPER_4(vdiv_hu, void, env, i32, i32, i32)
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DEF_HELPER_4(vdiv_wu, void, env, i32, i32, i32)
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DEF_HELPER_4(vdiv_du, void, env, i32, i32, i32)
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DEF_HELPER_4(vmod_b, void, env, i32, i32, i32)
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DEF_HELPER_4(vmod_h, void, env, i32, i32, i32)
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DEF_HELPER_4(vmod_w, void, env, i32, i32, i32)
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DEF_HELPER_4(vmod_d, void, env, i32, i32, i32)
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DEF_HELPER_4(vmod_bu, void, env, i32, i32, i32)
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DEF_HELPER_4(vmod_hu, void, env, i32, i32, i32)
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DEF_HELPER_4(vmod_wu, void, env, i32, i32, i32)
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DEF_HELPER_4(vmod_du, void, env, i32, i32, i32)
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@ -2676,3 +2676,20 @@ static void do_vmaddwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
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TRANS(vmaddwod_h_bu_b, gvec_vvv, MO_8, do_vmaddwod_u_s)
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TRANS(vmaddwod_w_hu_h, gvec_vvv, MO_16, do_vmaddwod_u_s)
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TRANS(vmaddwod_d_wu_w, gvec_vvv, MO_32, do_vmaddwod_u_s)
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TRANS(vdiv_b, gen_vvv, gen_helper_vdiv_b)
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TRANS(vdiv_h, gen_vvv, gen_helper_vdiv_h)
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TRANS(vdiv_w, gen_vvv, gen_helper_vdiv_w)
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TRANS(vdiv_d, gen_vvv, gen_helper_vdiv_d)
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TRANS(vdiv_bu, gen_vvv, gen_helper_vdiv_bu)
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TRANS(vdiv_hu, gen_vvv, gen_helper_vdiv_hu)
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TRANS(vdiv_wu, gen_vvv, gen_helper_vdiv_wu)
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TRANS(vdiv_du, gen_vvv, gen_helper_vdiv_du)
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TRANS(vmod_b, gen_vvv, gen_helper_vmod_b)
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TRANS(vmod_h, gen_vvv, gen_helper_vmod_h)
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TRANS(vmod_w, gen_vvv, gen_helper_vmod_w)
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TRANS(vmod_d, gen_vvv, gen_helper_vmod_d)
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TRANS(vmod_bu, gen_vvv, gen_helper_vmod_bu)
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TRANS(vmod_hu, gen_vvv, gen_helper_vmod_hu)
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TRANS(vmod_wu, gen_vvv, gen_helper_vmod_wu)
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TRANS(vmod_du, gen_vvv, gen_helper_vmod_du)
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@ -740,3 +740,20 @@ vmaddwod_h_bu_b 0111 00001011 11100 ..... ..... ..... @vvv
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vmaddwod_w_hu_h 0111 00001011 11101 ..... ..... ..... @vvv
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vmaddwod_d_wu_w 0111 00001011 11110 ..... ..... ..... @vvv
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vmaddwod_q_du_d 0111 00001011 11111 ..... ..... ..... @vvv
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vdiv_b 0111 00001110 00000 ..... ..... ..... @vvv
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vdiv_h 0111 00001110 00001 ..... ..... ..... @vvv
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vdiv_w 0111 00001110 00010 ..... ..... ..... @vvv
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vdiv_d 0111 00001110 00011 ..... ..... ..... @vvv
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vdiv_bu 0111 00001110 01000 ..... ..... ..... @vvv
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vdiv_hu 0111 00001110 01001 ..... ..... ..... @vvv
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vdiv_wu 0111 00001110 01010 ..... ..... ..... @vvv
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vdiv_du 0111 00001110 01011 ..... ..... ..... @vvv
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vmod_b 0111 00001110 00100 ..... ..... ..... @vvv
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vmod_h 0111 00001110 00101 ..... ..... ..... @vvv
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vmod_w 0111 00001110 00110 ..... ..... ..... @vvv
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vmod_d 0111 00001110 00111 ..... ..... ..... @vvv
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vmod_bu 0111 00001110 01100 ..... ..... ..... @vvv
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vmod_hu 0111 00001110 01101 ..... ..... ..... @vvv
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vmod_wu 0111 00001110 01110 ..... ..... ..... @vvv
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vmod_du 0111 00001110 01111 ..... ..... ..... @vvv
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@ -553,3 +553,40 @@ void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t v) \
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VMADDWOD_U_S(vmaddwod_h_bu_b, 16, H, UH, B, UB, DO_MUL)
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VMADDWOD_U_S(vmaddwod_w_hu_h, 32, W, UW, H, UH, DO_MUL)
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VMADDWOD_U_S(vmaddwod_d_wu_w, 64, D, UD, W, UW, DO_MUL)
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#define DO_DIVU(N, M) (unlikely(M == 0) ? 0 : N / M)
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#define DO_REMU(N, M) (unlikely(M == 0) ? 0 : N % M)
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#define DO_DIV(N, M) (unlikely(M == 0) ? 0 :\
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unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
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#define DO_REM(N, M) (unlikely(M == 0) ? 0 :\
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unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
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#define VDIV(NAME, BIT, E, DO_OP) \
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void HELPER(NAME)(CPULoongArchState *env, \
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uint32_t vd, uint32_t vj, uint32_t vk) \
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{ \
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int i; \
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VReg *Vd = &(env->fpr[vd].vreg); \
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VReg *Vj = &(env->fpr[vj].vreg); \
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VReg *Vk = &(env->fpr[vk].vreg); \
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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Vd->E(i) = DO_OP(Vj->E(i), Vk->E(i)); \
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} \
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}
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VDIV(vdiv_b, 8, B, DO_DIV)
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VDIV(vdiv_h, 16, H, DO_DIV)
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VDIV(vdiv_w, 32, W, DO_DIV)
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VDIV(vdiv_d, 64, D, DO_DIV)
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VDIV(vdiv_bu, 8, UB, DO_DIVU)
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VDIV(vdiv_hu, 16, UH, DO_DIVU)
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VDIV(vdiv_wu, 32, UW, DO_DIVU)
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VDIV(vdiv_du, 64, UD, DO_DIVU)
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VDIV(vmod_b, 8, B, DO_REM)
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VDIV(vmod_h, 16, H, DO_REM)
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VDIV(vmod_w, 32, W, DO_REM)
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VDIV(vmod_d, 64, D, DO_REM)
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VDIV(vmod_bu, 8, UB, DO_REMU)
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VDIV(vmod_hu, 16, UH, DO_REMU)
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VDIV(vmod_wu, 32, UW, DO_REMU)
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VDIV(vmod_du, 64, UD, DO_REMU)
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