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https://gitlab.com/qemu-project/qemu
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ppc: Add aCube Sam460ex board
Add emulation of aCube Sam460ex board based on AMCC 460EX embedded SoC. This is not a complete implementation yet with a lot of components still missing but enough for the U-Boot firmware to start and to boot a Linux kernel or AROS. Signed-off-by: François Revol <revol@free.fr> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
BALATON Zoltan
David Gibson
parent
82e65fe01e
commit
4b387f9ee1
7 changed files with 1175 additions and 2 deletions
2
Makefile
2
Makefile
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@ -779,7 +779,7 @@ efi-e1000.rom efi-eepro100.rom efi-ne2k_pci.rom \
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efi-pcnet.rom efi-rtl8139.rom efi-virtio.rom \
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efi-e1000e.rom efi-vmxnet3.rom \
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qemu-icon.bmp qemu_logo_no_text.svg \
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bamboo.dtb petalogix-s3adsp1800.dtb petalogix-ml605.dtb \
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bamboo.dtb canyonlands.dtb petalogix-s3adsp1800.dtb petalogix-ml605.dtb \
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multiboot.bin linuxboot.bin linuxboot_dma.bin kvmvapic.bin \
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s390-ccw.img s390-netboot.img \
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spapr-rtas.bin slof.bin skiboot.lid \
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@ -21,6 +21,8 @@ CONFIG_E500=y
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CONFIG_OPENPIC_KVM=$(call land,$(CONFIG_E500),$(CONFIG_KVM))
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CONFIG_PLATFORM_BUS=y
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CONFIG_ETSEC=y
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# For Sam460ex
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CONFIG_USB_EHCI_SYSBUS=y
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CONFIG_SM501=y
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CONFIG_IDE_SII3112=y
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CONFIG_I2C=y
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@ -15,6 +15,7 @@ CONFIG_PTIMER=y
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CONFIG_I8259=y
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CONFIG_XILINX=y
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CONFIG_XILINX_ETHLITE=y
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CONFIG_USB_EHCI_SYSBUS=y
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CONFIG_SM501=y
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CONFIG_IDE_SII3112=y
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CONFIG_I2C=y
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@ -13,7 +13,8 @@ endif
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obj-$(CONFIG_PSERIES) += spapr_rtas_ddw.o
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# PowerPC 4xx boards
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obj-y += ppc4xx_devs.o ppc405_uc.o
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obj-$(CONFIG_PPC4XX) += ppc4xx_pci.o ppc405_boards.o ppc440_bamboo.o ppc440_pcix.o
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obj-$(CONFIG_PPC4XX) += ppc4xx_pci.o ppc405_boards.o
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obj-$(CONFIG_PPC4XX) += ppc440_bamboo.o ppc440_pcix.o ppc440_uc.o sam460ex.o
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# PReP
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obj-$(CONFIG_PREP) += prep.o
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obj-$(CONFIG_PREP) += prep_systemio.o
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603
hw/ppc/sam460ex.c
Normal file
603
hw/ppc/sam460ex.c
Normal file
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@ -0,0 +1,603 @@
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/*
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* QEMU aCube Sam460ex board emulation
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*
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* Copyright (c) 2012 François Revol
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* Copyright (c) 2016-2018 BALATON Zoltan
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*
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* This file is derived from hw/ppc440_bamboo.c,
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* the copyright for that material belongs to the original owners.
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qemu/cutils.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "sysemu/blockdev.h"
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#include "hw/boards.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/block-backend.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "exec/address-spaces.h"
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#include "exec/memory.h"
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#include "hw/ppc/ppc440.h"
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#include "hw/ppc/ppc405.h"
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#include "hw/block/flash.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/qtest.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "hw/i2c/ppc4xx_i2c.h"
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#include "hw/i2c/smbus.h"
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#include "hw/usb/hcd-ehci.h"
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#define BINARY_DEVICE_TREE_FILE "canyonlands.dtb"
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#define UBOOT_FILENAME "u-boot-sam460-20100605.bin"
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/* to extract the official U-Boot bin from the updater: */
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/* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \
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if=updater/updater-460 of=u-boot-sam460-20100605.bin */
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/* from Sam460 U-Boot include/configs/Sam460ex.h */
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#define FLASH_BASE 0xfff00000
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#define FLASH_BASE_H 0x4
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#define FLASH_SIZE (1 << 20)
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#define UBOOT_LOAD_BASE 0xfff80000
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#define UBOOT_SIZE 0x00080000
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#define UBOOT_ENTRY 0xfffffffc
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/* from U-Boot */
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#define EPAPR_MAGIC (0x45504150)
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#define KERNEL_ADDR 0x1000000
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#define FDT_ADDR 0x1800000
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#define RAMDISK_ADDR 0x1900000
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/* Sam460ex IRQ MAP:
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IRQ0 = ETH_INT
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IRQ1 = FPGA_INT
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IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB)
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IRQ3 = FPGA_INT2
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IRQ11 = RTC_INT
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IRQ12 = SM502_INT
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*/
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#define SDRAM_NR_BANKS 4
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/* FIXME: See u-boot.git 8ac41e, also fix in ppc440_uc.c */
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static const unsigned int ppc460ex_sdram_bank_sizes[] = {
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1024 << 20, 512 << 20, 256 << 20, 128 << 20, 64 << 20, 32 << 20, 0
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};
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struct boot_info {
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uint32_t dt_base;
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uint32_t dt_size;
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uint32_t entry;
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};
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/*****************************************************************************/
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/* SPD eeprom content from mips_malta.c */
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struct _eeprom24c0x_t {
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uint8_t tick;
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uint8_t address;
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uint8_t command;
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uint8_t ack;
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uint8_t scl;
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uint8_t sda;
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uint8_t data;
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uint8_t contents[256];
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};
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typedef struct _eeprom24c0x_t eeprom24c0x_t;
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static eeprom24c0x_t spd_eeprom = {
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.contents = {
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/* 00000000: */ 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
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/* 00000008: */ 0x04, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
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/* 00000010: */ 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
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/* 00000018: */ 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
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/* 00000020: */ 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
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/* 00000028: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000030: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000038: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
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/* 00000040: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000048: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000050: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000058: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000060: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000068: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000070: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000078: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
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},
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};
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static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
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{
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enum { SDR = 0x4, DDR1 = 0x7, DDR2 = 0x8 } type;
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uint8_t *spd = spd_eeprom.contents;
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uint8_t nbanks = 0;
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uint16_t density = 0;
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int i;
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/* work in terms of MB */
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ram_size >>= 20;
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while ((ram_size >= 4) && (nbanks <= 2)) {
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int sz_log2 = MIN(31 - clz32(ram_size), 14);
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nbanks++;
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density |= 1 << (sz_log2 - 2);
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ram_size -= 1 << sz_log2;
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}
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/* split to 2 banks if possible */
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if ((nbanks == 1) && (density > 1)) {
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nbanks++;
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density >>= 1;
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}
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if (density & 0xff00) {
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density = (density & 0xe0) | ((density >> 8) & 0x1f);
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type = DDR2;
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} else if (!(density & 0x1f)) {
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type = DDR2;
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} else {
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type = SDR;
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}
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if (ram_size) {
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warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
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" of SDRAM", ram_size);
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}
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/* fill in SPD memory information */
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spd[2] = type;
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spd[5] = nbanks;
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spd[31] = density;
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/* XXX: this is totally random */
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spd[9] = 0x10; /* CAS tcyc */
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spd[18] = 0x20; /* CAS bit */
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spd[23] = 0x10; /* CAS tcyc */
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spd[25] = 0x10; /* CAS tcyc */
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/* checksum */
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spd[63] = 0;
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for (i = 0; i < 63; i++) {
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spd[63] += spd[i];
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}
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/* copy for SMBUS */
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memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
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}
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static void generate_eeprom_serial(uint8_t *eeprom)
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{
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int i, pos = 0;
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uint8_t mac[6] = { 0x00 };
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uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
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/* version */
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eeprom[pos++] = 0x01;
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/* count */
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eeprom[pos++] = 0x02;
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/* MAC address */
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eeprom[pos++] = 0x01; /* MAC */
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eeprom[pos++] = 0x06; /* length */
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memcpy(&eeprom[pos], mac, sizeof(mac));
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pos += sizeof(mac);
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/* serial number */
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eeprom[pos++] = 0x02; /* serial */
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eeprom[pos++] = 0x05; /* length */
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memcpy(&eeprom[pos], sn, sizeof(sn));
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pos += sizeof(sn);
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/* checksum */
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eeprom[pos] = 0;
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for (i = 0; i < pos; i++) {
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eeprom[pos] += eeprom[i];
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}
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}
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/*****************************************************************************/
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static int sam460ex_load_uboot(void)
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{
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DriveInfo *dinfo;
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BlockBackend *blk = NULL;
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hwaddr base = FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32);
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long bios_size = FLASH_SIZE;
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int fl_sectors;
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dinfo = drive_get(IF_PFLASH, 0, 0);
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if (dinfo) {
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blk = blk_by_legacy_dinfo(dinfo);
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bios_size = blk_getlength(blk);
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}
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fl_sectors = (bios_size + 65535) >> 16;
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if (!pflash_cfi01_register(base, NULL, "sam460ex.flash", bios_size,
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blk, (64 * 1024), fl_sectors,
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1, 0x89, 0x18, 0x0000, 0x0, 1)) {
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error_report("qemu: Error registering flash memory.");
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/* XXX: return an error instead? */
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exit(1);
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}
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if (!blk) {
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/*error_report("No flash image given with the 'pflash' parameter,"
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" using default u-boot image");*/
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base = UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32);
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rom_add_file_fixed(UBOOT_FILENAME, base, -1);
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}
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return 0;
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}
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static int sam460ex_load_device_tree(hwaddr addr,
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uint32_t ramsize,
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hwaddr initrd_base,
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hwaddr initrd_size,
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const char *kernel_cmdline)
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{
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int ret = -1;
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uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
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char *filename;
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int fdt_size;
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void *fdt;
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uint32_t tb_freq = 50000000;
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uint32_t clock_freq = 50000000;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
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if (!filename) {
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goto out;
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}
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fdt = load_device_tree(filename, &fdt_size);
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g_free(filename);
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if (fdt == NULL) {
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goto out;
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}
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/* Manipulate device tree in memory. */
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ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
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sizeof(mem_reg_property));
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if (ret < 0) {
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error_report("couldn't set /memory/reg");
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}
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/* default FDT doesn't have a /chosen node... */
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qemu_fdt_add_subnode(fdt, "/chosen");
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ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
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initrd_base);
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if (ret < 0) {
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error_report("couldn't set /chosen/linux,initrd-start");
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}
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ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
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(initrd_base + initrd_size));
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if (ret < 0) {
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error_report("couldn't set /chosen/linux,initrd-end");
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}
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ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
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kernel_cmdline);
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if (ret < 0) {
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error_report("couldn't set /chosen/bootargs");
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}
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/* Copy data from the host device tree into the guest. Since the guest can
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* directly access the timebase without host involvement, we must expose
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* the correct frequencies. */
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if (kvm_enabled()) {
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tb_freq = kvmppc_get_tbfreq();
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clock_freq = kvmppc_get_clockfreq();
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}
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qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
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clock_freq);
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qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
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tb_freq);
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rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
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g_free(fdt);
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ret = fdt_size;
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out:
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return ret;
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}
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/* Create reset TLB entries for BookE, mapping only the flash memory. */
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static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env)
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{
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ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
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/* on reset the flash is mapped by a shadow TLB,
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* but since we don't implement them we need to use
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* the same values U-Boot will use to avoid a fault.
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*/
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tlb->attr = 0;
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tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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tlb->size = 0x10000000; /* up to 0xffffffff */
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tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK;
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tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4;
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tlb->PID = 0;
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}
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/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
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static void mmubooke_create_initial_mapping(CPUPPCState *env,
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target_ulong va,
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hwaddr pa)
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{
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ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
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tlb->attr = 0;
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tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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tlb->size = 1 << 31; /* up to 0x80000000 */
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tlb->EPN = va & TARGET_PAGE_MASK;
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tlb->RPN = pa & TARGET_PAGE_MASK;
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tlb->PID = 0;
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}
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static void main_cpu_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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struct boot_info *bi = env->load_info;
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cpu_reset(CPU(cpu));
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/* either we have a kernel to boot or we jump to U-Boot */
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if (bi->entry != UBOOT_ENTRY) {
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env->gpr[1] = (16 << 20) - 8;
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env->gpr[3] = FDT_ADDR;
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env->nip = bi->entry;
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/* Create a mapping for the kernel. */
|
||||
mmubooke_create_initial_mapping(env, 0, 0);
|
||||
env->gpr[6] = tswap32(EPAPR_MAGIC);
|
||||
env->gpr[7] = (16 << 20) - 8; /*bi->ima_size;*/
|
||||
|
||||
} else {
|
||||
env->nip = UBOOT_ENTRY;
|
||||
mmubooke_create_initial_mapping_uboot(env);
|
||||
}
|
||||
}
|
||||
|
||||
static void sam460ex_init(MachineState *machine)
|
||||
{
|
||||
MemoryRegion *address_space_mem = get_system_memory();
|
||||
MemoryRegion *isa = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS);
|
||||
hwaddr ram_bases[SDRAM_NR_BANKS];
|
||||
hwaddr ram_sizes[SDRAM_NR_BANKS];
|
||||
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
|
||||
qemu_irq *irqs, *uic[4];
|
||||
PCIBus *pci_bus;
|
||||
PowerPCCPU *cpu;
|
||||
CPUPPCState *env;
|
||||
PPC4xxI2CState *i2c[2];
|
||||
hwaddr entry = UBOOT_ENTRY;
|
||||
hwaddr loadaddr = 0;
|
||||
target_long initrd_size = 0;
|
||||
DeviceState *dev;
|
||||
SysBusDevice *sbdev;
|
||||
int success;
|
||||
int i;
|
||||
struct boot_info *boot_info;
|
||||
const size_t smbus_eeprom_size = 8 * 256;
|
||||
uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
|
||||
|
||||
cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
|
||||
env = &cpu->env;
|
||||
if (env->mmu_model != POWERPC_MMU_BOOKE) {
|
||||
error_report("Only MMU model BookE is supported by this machine.");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
#ifdef TARGET_PPCEMB
|
||||
if (!qtest_enabled()) {
|
||||
warn_report("qemu-system-ppcemb is deprecated, "
|
||||
"please use qemu-system-ppc instead.");
|
||||
}
|
||||
#endif
|
||||
|
||||
qemu_register_reset(main_cpu_reset, cpu);
|
||||
boot_info = g_malloc0(sizeof(*boot_info));
|
||||
env->load_info = boot_info;
|
||||
|
||||
ppc_booke_timers_init(cpu, 50000000, 0);
|
||||
ppc_dcr_init(env, NULL, NULL);
|
||||
|
||||
/* PLB arbitrer */
|
||||
ppc4xx_plb_init(env);
|
||||
|
||||
/* interrupt controllers */
|
||||
irqs = g_malloc0(sizeof(*irqs) * PPCUIC_OUTPUT_NB);
|
||||
irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
|
||||
irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
|
||||
uic[0] = ppcuic_init(env, irqs, 0xc0, 0, 1);
|
||||
uic[1] = ppcuic_init(env, &uic[0][30], 0xd0, 0, 1);
|
||||
uic[2] = ppcuic_init(env, &uic[0][10], 0xe0, 0, 1);
|
||||
uic[3] = ppcuic_init(env, &uic[0][16], 0xf0, 0, 1);
|
||||
|
||||
/* SDRAM controller */
|
||||
memset(ram_bases, 0, sizeof(ram_bases));
|
||||
memset(ram_sizes, 0, sizeof(ram_sizes));
|
||||
/* put all RAM on first bank because board has one slot
|
||||
* and firmware only checks that */
|
||||
machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1,
|
||||
ram_memories, ram_bases, ram_sizes,
|
||||
ppc460ex_sdram_bank_sizes);
|
||||
|
||||
/* FIXME: does 460EX have ECC interrupts? */
|
||||
ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
|
||||
ram_bases, ram_sizes, 1);
|
||||
|
||||
/* generate SPD EEPROM data */
|
||||
for (i = 0; i < SDRAM_NR_BANKS; i++) {
|
||||
generate_eeprom_spd(&smbus_eeprom_buf[i * 256], ram_sizes[i]);
|
||||
}
|
||||
generate_eeprom_serial(&smbus_eeprom_buf[4 * 256]);
|
||||
generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
|
||||
|
||||
/* IIC controllers */
|
||||
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]);
|
||||
i2c[0] = PPC4xx_I2C(dev);
|
||||
object_property_set_bool(OBJECT(dev), true, "realized", NULL);
|
||||
smbus_eeprom_init(i2c[0]->bus, 8, smbus_eeprom_buf, smbus_eeprom_size);
|
||||
g_free(smbus_eeprom_buf);
|
||||
|
||||
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]);
|
||||
i2c[1] = PPC4xx_I2C(dev);
|
||||
|
||||
/* External bus controller */
|
||||
ppc405_ebc_init(env);
|
||||
|
||||
/* CPR */
|
||||
ppc4xx_cpr_init(env);
|
||||
|
||||
/* PLB to AHB bridge */
|
||||
ppc4xx_ahb_init(env);
|
||||
|
||||
/* System DCRs */
|
||||
ppc4xx_sdr_init(env);
|
||||
|
||||
/* MAL */
|
||||
ppc4xx_mal_init(env, 4, 16, &uic[2][3]);
|
||||
|
||||
/* 256K of L2 cache as memory */
|
||||
ppc4xx_l2sram_init(env);
|
||||
/* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */
|
||||
memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 << 10,
|
||||
&error_abort);
|
||||
memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram);
|
||||
|
||||
/* USB */
|
||||
sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]);
|
||||
dev = qdev_create(NULL, "sysbus-ohci");
|
||||
qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
|
||||
qdev_prop_set_uint32(dev, "num-ports", 6);
|
||||
qdev_init_nofail(dev);
|
||||
sbdev = SYS_BUS_DEVICE(dev);
|
||||
sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
|
||||
sysbus_connect_irq(sbdev, 0, uic[2][30]);
|
||||
usb_create_simple(usb_bus_find(-1), "usb-kbd");
|
||||
usb_create_simple(usb_bus_find(-1), "usb-mouse");
|
||||
|
||||
/* PCI bus */
|
||||
ppc460ex_pcie_init(env);
|
||||
/* FIXME: is this correct? */
|
||||
dev = sysbus_create_varargs("ppc440-pcix-host", 0xc0ec00000,
|
||||
uic[1][0], uic[1][20], uic[1][21], uic[1][22],
|
||||
NULL);
|
||||
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
|
||||
if (!pci_bus) {
|
||||
error_report("couldn't create PCI controller!");
|
||||
exit(1);
|
||||
}
|
||||
memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(),
|
||||
0, 0x10000);
|
||||
memory_region_add_subregion(get_system_memory(), 0xc08000000, isa);
|
||||
|
||||
/* PCI devices */
|
||||
pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501");
|
||||
/* SoC has a single SATA port but we don't emulate that yet
|
||||
* However, firmware and usual clients have driver for SiI311x
|
||||
* so add one for convenience by default */
|
||||
if (defaults_enabled()) {
|
||||
pci_create_simple(pci_bus, -1, "sii3112");
|
||||
}
|
||||
|
||||
/* SoC has 4 UARTs
|
||||
* but board has only one wired and two are present in fdt */
|
||||
if (serial_hds[0] != NULL) {
|
||||
serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1],
|
||||
PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
|
||||
DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
if (serial_hds[1] != NULL) {
|
||||
serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1],
|
||||
PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
|
||||
DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
|
||||
/* Load U-Boot image. */
|
||||
if (!machine->kernel_filename) {
|
||||
success = sam460ex_load_uboot();
|
||||
if (success < 0) {
|
||||
error_report("qemu: could not load firmware");
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
/* Load kernel. */
|
||||
if (machine->kernel_filename) {
|
||||
success = load_uimage(machine->kernel_filename, &entry, &loadaddr,
|
||||
NULL, NULL, NULL);
|
||||
if (success < 0) {
|
||||
uint64_t elf_entry, elf_lowaddr;
|
||||
|
||||
success = load_elf(machine->kernel_filename, NULL, NULL, &elf_entry,
|
||||
&elf_lowaddr, NULL, 1, PPC_ELF_MACHINE, 0, 0);
|
||||
entry = elf_entry;
|
||||
loadaddr = elf_lowaddr;
|
||||
}
|
||||
/* XXX try again as binary */
|
||||
if (success < 0) {
|
||||
error_report("qemu: could not load kernel '%s'",
|
||||
machine->kernel_filename);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
/* Load initrd. */
|
||||
if (machine->initrd_filename) {
|
||||
initrd_size = load_image_targphys(machine->initrd_filename,
|
||||
RAMDISK_ADDR,
|
||||
machine->ram_size - RAMDISK_ADDR);
|
||||
if (initrd_size < 0) {
|
||||
error_report("qemu: could not load ram disk '%s' at %x",
|
||||
machine->initrd_filename, RAMDISK_ADDR);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
/* If we're loading a kernel directly, we must load the device tree too. */
|
||||
if (machine->kernel_filename) {
|
||||
int dt_size;
|
||||
|
||||
dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size,
|
||||
RAMDISK_ADDR, initrd_size,
|
||||
machine->kernel_cmdline);
|
||||
if (dt_size < 0) {
|
||||
error_report("couldn't load device tree");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
boot_info->dt_base = FDT_ADDR;
|
||||
boot_info->dt_size = dt_size;
|
||||
}
|
||||
|
||||
boot_info->entry = entry;
|
||||
}
|
||||
|
||||
static void sam460ex_machine_init(MachineClass *mc)
|
||||
{
|
||||
mc->desc = "aCube Sam460ex";
|
||||
mc->init = sam460ex_init;
|
||||
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
|
||||
mc->default_ram_size = 512 * M_BYTE;
|
||||
}
|
||||
|
||||
DEFINE_MACHINE("sam460ex", sam460ex_machine_init)
|
||||
BIN
pc-bios/canyonlands.dtb
Normal file
BIN
pc-bios/canyonlands.dtb
Normal file
Binary file not shown.
566
pc-bios/canyonlands.dts
Normal file
566
pc-bios/canyonlands.dts
Normal file
|
|
@ -0,0 +1,566 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC Canyonlands (460EX)
|
||||
*
|
||||
* Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,canyonlands";
|
||||
compatible = "amcc,canyonlands";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,460EX";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
next-level-cache = <&L2C0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC3: interrupt-controller3 {
|
||||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-460ex";
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-460ex";
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
CPM0: cpm {
|
||||
compatible = "ibm,cpm";
|
||||
dcr-access-method = "native";
|
||||
dcr-reg = <0x160 0x003>;
|
||||
unused-units = <0x00000100>;
|
||||
idle-doze = <0x02000000>;
|
||||
standby = <0xfeff791d>;
|
||||
};
|
||||
|
||||
L2C0: l2c {
|
||||
compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
|
||||
dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
|
||||
0x030 0x008>; /* L2 cache DCR's */
|
||||
cache-line-size = <32>; /* 32 bytes */
|
||||
cache-size = <262144>; /* L2, 256K */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <11 1>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-460ex", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
CRYPTO: crypto@180000 {
|
||||
compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
|
||||
reg = <4 0x00180000 0x80400>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1d 0x4>;
|
||||
};
|
||||
|
||||
HWRNG: hwrng@110000 {
|
||||
compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
|
||||
reg = <4 0x00110000 0x50>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <16>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = < /*TXEOB*/ 0x6 0x4
|
||||
/*RXEOB*/ 0x7 0x4
|
||||
/*SERR*/ 0x3 0x4
|
||||
/*TXDE*/ 0x4 0x4
|
||||
/*RXDE*/ 0x5 0x4>;
|
||||
};
|
||||
|
||||
USB0: ehci@bffd0400 {
|
||||
compatible = "ibm,usb-ehci-460ex", "usb-ehci";
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0x1d 4>;
|
||||
reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
|
||||
};
|
||||
|
||||
USB1: usb@bffd0000 {
|
||||
compatible = "ohci-le";
|
||||
reg = <4 0xbffd0000 0x60>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0x1e 4>;
|
||||
};
|
||||
|
||||
USBOTG0: usbotg@bff80000 {
|
||||
compatible = "amcc,dwc-otg";
|
||||
reg = <0x4 0xbff80000 0x10000>;
|
||||
interrupt-parent = <&USBOTG0>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0x0 0x1 0x2>;
|
||||
interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
|
||||
/* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
|
||||
/* DMA */ 0x2 &UIC0 0xc 0x4>;
|
||||
};
|
||||
|
||||
AHBDMA: dma@bffd0800 {
|
||||
compatible = "snps,dma-spear1340";
|
||||
reg = <4 0xbffd0800 0x400>;
|
||||
interrupt-parent = <&UIC3>;
|
||||
interrupts = <0x5 0x4>;
|
||||
#dma-cells = <3>;
|
||||
};
|
||||
|
||||
SATA0: sata@bffd1000 {
|
||||
compatible = "amcc,sata-460ex";
|
||||
reg = <4 0xbffd1000 0x800>;
|
||||
interrupt-parent = <&UIC3>;
|
||||
interrupts = <0x0 0x4>;
|
||||
dmas = <&AHBDMA 0 1 0>;
|
||||
dma-names = "sata-dma";
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-460ex", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-460ex", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <0x6 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0x00000000 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x001e0000>;
|
||||
};
|
||||
partition@1e0000 {
|
||||
label = "dtb";
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "ramdisk";
|
||||
reg = <0x00200000 0x01400000>;
|
||||
};
|
||||
partition@1600000 {
|
||||
label = "jffs2";
|
||||
reg = <0x01600000 0x00400000>;
|
||||
};
|
||||
partition@1a00000 {
|
||||
label = "user";
|
||||
reg = <0x01a00000 0x02560000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpld@2,0 {
|
||||
compatible = "amcc,ppc460ex-bcsr";
|
||||
reg = <2 0x0 0x9>;
|
||||
};
|
||||
|
||||
ndfc@3,0 {
|
||||
compatible = "ibm,ndfc";
|
||||
reg = <0x00000003 0x00000000 0x00002000>;
|
||||
ccr = <0x00001000>;
|
||||
bank-settings = <0x80002222>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
nand {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x00000000 0x00100000>;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "user";
|
||||
reg = <0x00000000 0x03f00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic-460ex", "ibm,iic";
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rtc@68 {
|
||||
compatible = "st,m41t80";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0x19 0x8>;
|
||||
};
|
||||
sttm@48 {
|
||||
compatible = "ad,ad7414";
|
||||
reg = <0x48>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x14 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-460ex", "ibm,iic";
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
GPIO0: gpio@ef600b00 {
|
||||
compatible = "ibm,ppc4xx-gpio";
|
||||
reg = <0xef600b00 0x00000048>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@ef600d00 {
|
||||
compatible = "ibm,zmii-460ex", "ibm,zmii";
|
||||
reg = <0xef600d00 0x0000000c>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef601500 {
|
||||
compatible = "ibm,rgmii-460ex", "ibm,rgmii";
|
||||
reg = <0xef601500 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@ef601350 {
|
||||
compatible = "ibm,tah-460ex", "ibm,tah";
|
||||
reg = <0xef601350 0x00000030>;
|
||||
};
|
||||
|
||||
TAH1: emac-tah@ef601450 {
|
||||
compatible = "ibm,tah-460ex", "ibm,tah";
|
||||
reg = <0xef601450 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600e00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x14 0x4>;
|
||||
reg = <0xef600e00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
tah-device = <&TAH0>;
|
||||
tah-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600f00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x15 0x4>;
|
||||
reg = <0xef600f00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <8>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
tah-device = <&TAH1>;
|
||||
tah-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
};
|
||||
|
||||
PCIX0: pci@c0ec00000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
|
||||
primary;
|
||||
large-inbound-windows;
|
||||
enable-msi-hole;
|
||||
reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0x00000000 0x00000000 /* no IACK cycles */
|
||||
0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
|
||||
0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
|
||||
0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0 to 0x3f */
|
||||
bus-range = <0x0 0x3f>;
|
||||
|
||||
/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
|
||||
interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
|
||||
};
|
||||
|
||||
PCIE0: pciex@d00000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08010000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x100 0x020>;
|
||||
sdr-base = <0x300>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 40 to 0x7f */
|
||||
bus-range = <0x40 0x7f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@d20000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08011000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x120 0x020>;
|
||||
sdr-base = <0x340>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 80 to 0xbf */
|
||||
bus-range = <0x80 0xbf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
MSI: ppc4xx-msi@C10000000 {
|
||||
compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
|
||||
reg = < 0xC 0x10000000 0x100>;
|
||||
sdr-base = <0x36C>;
|
||||
msi-data = <0x00000000>;
|
||||
msi-mask = <0x44440000>;
|
||||
interrupt-count = <3>;
|
||||
interrupts = <0 1 2 3>;
|
||||
interrupt-parent = <&UIC3>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0 &UIC3 0x18 1
|
||||
1 &UIC3 0x19 1
|
||||
2 &UIC3 0x1A 1
|
||||
3 &UIC3 0x1B 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in a new issue