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https://gitlab.com/qemu-project/qemu
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arm: Add PCIe host bridge in virt machine
Now that we have a working "generic" PCIe host bridge driver, we can plug it into ARM's virt machine to always have PCIe available to normal ARM VMs. I've successfully managed to expose a Bochs VGA device, XHCI and an e1000 into an AArch64 VM with this and they all lived happily ever after. Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Claudio Fontana <claudio.fontana@huawei.com> [PMM: Squashed in fix for off-by-one error in bus-range DT property from Laszlo Ersek <lersek@redhat.com>] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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4d8fde1126
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4ab29b8214
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@ -82,6 +82,8 @@ CONFIG_ZYNQ=y
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CONFIG_VERSATILE_PCI=y
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CONFIG_VERSATILE_I2C=y
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CONFIG_PCI_GENERIC=y
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CONFIG_SDHCI=y
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CONFIG_INTEGRATOR_DEBUG=y
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138
hw/arm/virt.c
138
hw/arm/virt.c
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@ -42,6 +42,7 @@
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#include "exec/address-spaces.h"
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#include "qemu/bitops.h"
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#include "qemu/error-report.h"
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#include "hw/pci-host/gpex.h"
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#define NUM_VIRTIO_TRANSPORTS 32
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@ -69,6 +70,7 @@ enum {
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VIRT_MMIO,
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VIRT_RTC,
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VIRT_FW_CFG,
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VIRT_PCIE,
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};
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typedef struct MemMapEntry {
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@ -129,13 +131,21 @@ static const MemMapEntry a15memmap[] = {
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[VIRT_FW_CFG] = { 0x09020000, 0x0000000a },
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[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
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/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
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/* 0x10000000 .. 0x40000000 reserved for PCI */
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/*
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* PCIE verbose map:
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*
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* MMIO window { 0x10000000, 0x2eff0000 },
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* PIO window { 0x3eff0000, 0x00010000 },
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* ECAM { 0x3f000000, 0x01000000 },
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*/
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[VIRT_PCIE] = { 0x10000000, 0x30000000 },
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[VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
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};
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static const int a15irqmap[] = {
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[VIRT_UART] = 1,
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[VIRT_RTC] = 2,
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[VIRT_PCIE] = 3, /* ... to 6 */
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[VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
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};
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@ -312,7 +322,7 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
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}
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}
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static void fdt_add_gic_node(const VirtBoardInfo *vbi)
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static uint32_t fdt_add_gic_node(const VirtBoardInfo *vbi)
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{
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uint32_t gic_phandle;
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@ -331,9 +341,11 @@ static void fdt_add_gic_node(const VirtBoardInfo *vbi)
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2, vbi->memmap[VIRT_GIC_CPU].base,
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2, vbi->memmap[VIRT_GIC_CPU].size);
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qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", gic_phandle);
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return gic_phandle;
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}
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static void create_gic(const VirtBoardInfo *vbi, qemu_irq *pic)
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static uint32_t create_gic(const VirtBoardInfo *vbi, qemu_irq *pic)
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{
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/* We create a standalone GIC v2 */
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DeviceState *gicdev;
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@ -380,7 +392,7 @@ static void create_gic(const VirtBoardInfo *vbi, qemu_irq *pic)
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pic[i] = qdev_get_gpio_in(gicdev, i);
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}
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fdt_add_gic_node(vbi);
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return fdt_add_gic_node(vbi);
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}
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static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic)
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@ -585,6 +597,119 @@ static void create_fw_cfg(const VirtBoardInfo *vbi)
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g_free(nodename);
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}
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static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle,
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int first_irq, const char *nodename)
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{
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int devfn, pin;
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uint32_t full_irq_map[4 * 4 * 8] = { 0 };
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uint32_t *irq_map = full_irq_map;
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for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
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for (pin = 0; pin < 4; pin++) {
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int irq_type = GIC_FDT_IRQ_TYPE_SPI;
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int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
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int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
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int i;
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uint32_t map[] = {
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devfn << 8, 0, 0, /* devfn */
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pin + 1, /* PCI pin */
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gic_phandle, irq_type, irq_nr, irq_level }; /* GIC irq */
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/* Convert map to big endian */
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for (i = 0; i < 8; i++) {
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irq_map[i] = cpu_to_be32(map[i]);
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}
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irq_map += 8;
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}
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}
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qemu_fdt_setprop(vbi->fdt, nodename, "interrupt-map",
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full_irq_map, sizeof(full_irq_map));
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qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupt-map-mask",
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0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
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0x7 /* PCI irq */);
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}
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static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
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uint32_t gic_phandle)
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{
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hwaddr base = vbi->memmap[VIRT_PCIE].base;
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hwaddr size = vbi->memmap[VIRT_PCIE].size;
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hwaddr end = base + size;
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hwaddr size_mmio;
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hwaddr size_ioport = 64 * 1024;
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int nr_pcie_buses = 16;
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hwaddr size_ecam = PCIE_MMCFG_SIZE_MIN * nr_pcie_buses;
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hwaddr base_mmio = base;
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hwaddr base_ioport;
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hwaddr base_ecam;
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int irq = vbi->irqmap[VIRT_PCIE];
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MemoryRegion *mmio_alias;
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MemoryRegion *mmio_reg;
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MemoryRegion *ecam_alias;
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MemoryRegion *ecam_reg;
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DeviceState *dev;
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char *nodename;
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int i;
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base_ecam = QEMU_ALIGN_DOWN(end - size_ecam, size_ecam);
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base_ioport = QEMU_ALIGN_DOWN(base_ecam - size_ioport, size_ioport);
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size_mmio = base_ioport - base;
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dev = qdev_create(NULL, TYPE_GPEX_HOST);
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qdev_init_nofail(dev);
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/* Map only the first size_ecam bytes of ECAM space */
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ecam_alias = g_new0(MemoryRegion, 1);
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ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
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memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
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ecam_reg, 0, size_ecam);
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memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
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/* Map the MMIO window into system address space so as to expose
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* the section of PCI MMIO space which starts at the same base address
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* (ie 1:1 mapping for that part of PCI MMIO space visible through
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* the window).
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*/
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mmio_alias = g_new0(MemoryRegion, 1);
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mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
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memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
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mmio_reg, base_mmio, size_mmio);
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memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
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/* Map IO port space */
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_ioport);
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for (i = 0; i < GPEX_NUM_IRQS; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
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}
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nodename = g_strdup_printf("/pcie@%" PRIx64, base);
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qemu_fdt_add_subnode(vbi->fdt, nodename);
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qemu_fdt_setprop_string(vbi->fdt, nodename,
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"compatible", "pci-host-ecam-generic");
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qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "pci");
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qemu_fdt_setprop_cell(vbi->fdt, nodename, "#address-cells", 3);
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qemu_fdt_setprop_cell(vbi->fdt, nodename, "#size-cells", 2);
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qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0,
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nr_pcie_buses - 1);
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qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
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2, base_ecam, 2, size_ecam);
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qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges",
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1, FDT_PCI_RANGE_IOPORT, 2, 0,
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2, base_ioport, 2, size_ioport,
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1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
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2, base_mmio, 2, size_mmio);
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qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 1);
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create_pcie_irq_map(vbi, gic_phandle, irq, nodename);
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g_free(nodename);
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}
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static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
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{
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const VirtBoardInfo *board = (const VirtBoardInfo *)binfo;
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@ -602,6 +727,7 @@ static void machvirt_init(MachineState *machine)
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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const char *cpu_model = machine->cpu_model;
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VirtBoardInfo *vbi;
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uint32_t gic_phandle;
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if (!cpu_model) {
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cpu_model = "cortex-a15";
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@ -663,12 +789,14 @@ static void machvirt_init(MachineState *machine)
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create_flash(vbi);
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create_gic(vbi, pic);
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gic_phandle = create_gic(vbi, pic);
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create_uart(vbi, pic);
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create_rtc(vbi, pic);
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create_pcie(vbi, pic, gic_phandle);
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/* Create mmio transports, so the user can create virtio backends
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* (which will be automatically plugged in to the transports). If
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* no backend is created the transport will just sit harmlessly idle.
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@ -110,4 +110,13 @@ int qemu_fdt_setprop_sized_cells_from_array(void *fdt,
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qdt_tmp); \
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})
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#define FDT_PCI_RANGE_RELOCATABLE 0x80000000
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#define FDT_PCI_RANGE_PREFETCHABLE 0x40000000
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#define FDT_PCI_RANGE_ALIASED 0x20000000
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#define FDT_PCI_RANGE_TYPE_MASK 0x03000000
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#define FDT_PCI_RANGE_MMIO_64BIT 0x03000000
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#define FDT_PCI_RANGE_MMIO 0x02000000
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#define FDT_PCI_RANGE_IOPORT 0x01000000
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#define FDT_PCI_RANGE_CONFIG 0x00000000
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#endif /* __DEVICE_TREE_H__ */
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