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https://gitlab.com/qemu-project/qemu
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hw/arm/allwinner-r40: add SDRAM controller device
Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner R40 SDRAM controller. This driver only support 256M, 512M and 1024M memory now. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
qianfan Zhao
Peter Maydell
parent
a954543092
commit
4a52ef61d9
7 changed files with 674 additions and 3 deletions
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@ -31,6 +31,7 @@
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#include "hw/loader.h"
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#include "sysemu/sysemu.h"
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#include "hw/arm/allwinner-r40.h"
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#include "hw/misc/allwinner-r40-dramc.h"
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/* Memory map */
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const hwaddr allwinner_r40_memmap[] = {
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@ -53,6 +54,9 @@ const hwaddr allwinner_r40_memmap[] = {
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[AW_R40_DEV_UART6] = 0x01c29800,
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[AW_R40_DEV_UART7] = 0x01c29c00,
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[AW_R40_DEV_TWI0] = 0x01c2ac00,
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[AW_R40_DEV_DRAMCOM] = 0x01c62000,
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[AW_R40_DEV_DRAMCTL] = 0x01c63000,
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[AW_R40_DEV_DRAMPHY] = 0x01c65000,
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[AW_R40_DEV_GIC_DIST] = 0x01c81000,
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[AW_R40_DEV_GIC_CPU] = 0x01c82000,
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[AW_R40_DEV_GIC_HYP] = 0x01c84000,
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@ -129,8 +133,6 @@ static struct AwR40Unimplemented r40_unimplemented[] = {
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{ "gpu", 0x01c40000, 64 * KiB },
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{ "gmac", 0x01c50000, 64 * KiB },
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{ "hstmr", 0x01c60000, 4 * KiB },
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{ "dram-com", 0x01c62000, 4 * KiB },
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{ "dram-ctl", 0x01c63000, 4 * KiB },
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{ "tcon-top", 0x01c70000, 4 * KiB },
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{ "lcd0", 0x01c71000, 4 * KiB },
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{ "lcd1", 0x01c72000, 4 * KiB },
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@ -273,6 +275,12 @@ static void allwinner_r40_init(Object *obj)
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}
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object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
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object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_R40_DRAMC);
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object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
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"ram-addr");
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object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
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"ram-size");
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}
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static void allwinner_r40_realize(DeviceState *dev, Error **errp)
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@ -425,6 +433,15 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp)
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
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qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TWI0));
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/* DRAMC */
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sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0,
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s->memmap[AW_R40_DEV_DRAMCOM]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1,
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s->memmap[AW_R40_DEV_DRAMCTL]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2,
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s->memmap[AW_R40_DEV_DRAMPHY]);
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/* Unimplemented devices */
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for (i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) {
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create_unimplemented_device(r40_unimplemented[i].device_name,
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@ -85,6 +85,13 @@ static void bpim2u_init(MachineState *machine)
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object_property_set_int(OBJECT(r40), "clk1-freq", 24 * 1000 * 1000,
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&error_abort);
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/* DRAMC */
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r40->ram_size = machine->ram_size / MiB;
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object_property_set_uint(OBJECT(r40), "ram-addr",
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r40->memmap[AW_R40_DEV_SDRAM], &error_abort);
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object_property_set_int(OBJECT(r40), "ram-size",
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r40->ram_size, &error_abort);
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/* Mark R40 object realized */
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qdev_realize(DEVICE(r40), NULL, &error_abort);
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513
hw/misc/allwinner-r40-dramc.c
Normal file
513
hw/misc/allwinner-r40-dramc.c
Normal file
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@ -0,0 +1,513 @@
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/*
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* Allwinner R40 SDRAM Controller emulation
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*
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* CCopyright (C) 2023 qianfan Zhao <qianfanguijin@163.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/error-report.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "exec/address-spaces.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "qemu/bitops.h"
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#include "hw/misc/allwinner-r40-dramc.h"
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#include "trace.h"
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#define REG_INDEX(offset) (offset / sizeof(uint32_t))
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/* DRAMCOM register offsets */
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enum {
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REG_DRAMCOM_CR = 0x0000, /* Control Register */
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};
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/* DRAMCOMM register flags */
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enum {
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REG_DRAMCOM_CR_DUAL_RANK = (1 << 0),
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};
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/* DRAMCTL register offsets */
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enum {
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REG_DRAMCTL_PIR = 0x0000, /* PHY Initialization Register */
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REG_DRAMCTL_PGSR = 0x0010, /* PHY General Status Register */
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REG_DRAMCTL_STATR = 0x0018, /* Status Register */
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REG_DRAMCTL_PGCR = 0x0100, /* PHY general configuration registers */
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};
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/* DRAMCTL register flags */
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enum {
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REG_DRAMCTL_PGSR_INITDONE = (1 << 0),
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REG_DRAMCTL_PGSR_READ_TIMEOUT = (1 << 13),
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REG_DRAMCTL_PGCR_ENABLE_READ_TIMEOUT = (1 << 25),
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};
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enum {
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REG_DRAMCTL_STATR_ACTIVE = (1 << 0),
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};
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#define DRAM_MAX_ROW_BITS 16
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#define DRAM_MAX_COL_BITS 13 /* 8192 */
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#define DRAM_MAX_BANK 3
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static uint64_t dram_autodetect_cells[DRAM_MAX_ROW_BITS]
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[DRAM_MAX_BANK]
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[DRAM_MAX_COL_BITS];
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struct VirtualDDRChip {
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uint32_t ram_size;
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uint8_t bank_bits;
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uint8_t row_bits;
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uint8_t col_bits;
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};
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/*
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* Only power of 2 RAM sizes from 256MiB up to 2048MiB are supported,
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* 2GiB memory is not supported due to dual rank feature.
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*/
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static const struct VirtualDDRChip dummy_ddr_chips[] = {
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{
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.ram_size = 256,
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.bank_bits = 3,
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.row_bits = 12,
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.col_bits = 13,
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}, {
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.ram_size = 512,
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.bank_bits = 3,
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.row_bits = 13,
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.col_bits = 13,
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}, {
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.ram_size = 1024,
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.bank_bits = 3,
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.row_bits = 14,
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.col_bits = 13,
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}, {
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0
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}
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};
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static const struct VirtualDDRChip *get_match_ddr(uint32_t ram_size)
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{
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const struct VirtualDDRChip *ddr;
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for (ddr = &dummy_ddr_chips[0]; ddr->ram_size; ddr++) {
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if (ddr->ram_size == ram_size) {
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return ddr;
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}
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}
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return NULL;
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}
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static uint64_t *address_to_autodetect_cells(AwR40DramCtlState *s,
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const struct VirtualDDRChip *ddr,
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uint32_t offset)
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{
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int row_index = 0, bank_index = 0, col_index = 0;
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uint32_t row_addr, bank_addr, col_addr;
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row_addr = extract32(offset, s->set_col_bits + s->set_bank_bits,
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s->set_row_bits);
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bank_addr = extract32(offset, s->set_col_bits, s->set_bank_bits);
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col_addr = extract32(offset, 0, s->set_col_bits);
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for (int i = 0; i < ddr->row_bits; i++) {
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if (row_addr & BIT(i)) {
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row_index = i;
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}
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}
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for (int i = 0; i < ddr->bank_bits; i++) {
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if (bank_addr & BIT(i)) {
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bank_index = i;
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}
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}
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for (int i = 0; i < ddr->col_bits; i++) {
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if (col_addr & BIT(i)) {
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col_index = i;
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}
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}
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trace_allwinner_r40_dramc_offset_to_cell(offset, row_index, bank_index,
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col_index);
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return &dram_autodetect_cells[row_index][bank_index][col_index];
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}
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static void allwinner_r40_dramc_map_rows(AwR40DramCtlState *s, uint8_t row_bits,
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uint8_t bank_bits, uint8_t col_bits)
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{
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const struct VirtualDDRChip *ddr = get_match_ddr(s->ram_size);
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bool enable_detect_cells;
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trace_allwinner_r40_dramc_map_rows(row_bits, bank_bits, col_bits);
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if (!ddr) {
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return;
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}
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s->set_row_bits = row_bits;
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s->set_bank_bits = bank_bits;
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s->set_col_bits = col_bits;
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enable_detect_cells = ddr->bank_bits != bank_bits
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|| ddr->row_bits != row_bits
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|| ddr->col_bits != col_bits;
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if (enable_detect_cells) {
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trace_allwinner_r40_dramc_detect_cells_enable();
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} else {
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trace_allwinner_r40_dramc_detect_cells_disable();
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}
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memory_region_set_enabled(&s->detect_cells, enable_detect_cells);
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}
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static uint64_t allwinner_r40_dramcom_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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const AwR40DramCtlState *s = AW_R40_DRAMC(opaque);
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const uint32_t idx = REG_INDEX(offset);
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if (idx >= AW_R40_DRAMCOM_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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}
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trace_allwinner_r40_dramcom_read(offset, s->dramcom[idx], size);
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return s->dramcom[idx];
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}
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static void allwinner_r40_dramcom_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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AwR40DramCtlState *s = AW_R40_DRAMC(opaque);
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const uint32_t idx = REG_INDEX(offset);
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trace_allwinner_r40_dramcom_write(offset, val, size);
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if (idx >= AW_R40_DRAMCOM_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return;
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}
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switch (offset) {
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case REG_DRAMCOM_CR: /* Control Register */
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if (!(val & REG_DRAMCOM_CR_DUAL_RANK)) {
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allwinner_r40_dramc_map_rows(s, ((val >> 4) & 0xf) + 1,
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((val >> 2) & 0x1) + 2,
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(((val >> 8) & 0xf) + 3));
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}
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break;
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};
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s->dramcom[idx] = (uint32_t) val;
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}
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static uint64_t allwinner_r40_dramctl_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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const AwR40DramCtlState *s = AW_R40_DRAMC(opaque);
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const uint32_t idx = REG_INDEX(offset);
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if (idx >= AW_R40_DRAMCTL_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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}
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trace_allwinner_r40_dramctl_read(offset, s->dramctl[idx], size);
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return s->dramctl[idx];
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}
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static void allwinner_r40_dramctl_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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AwR40DramCtlState *s = AW_R40_DRAMC(opaque);
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const uint32_t idx = REG_INDEX(offset);
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trace_allwinner_r40_dramctl_write(offset, val, size);
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if (idx >= AW_R40_DRAMCTL_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return;
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}
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switch (offset) {
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case REG_DRAMCTL_PIR: /* PHY Initialization Register */
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s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE;
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s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE;
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break;
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}
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s->dramctl[idx] = (uint32_t) val;
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}
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static uint64_t allwinner_r40_dramphy_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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const AwR40DramCtlState *s = AW_R40_DRAMC(opaque);
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const uint32_t idx = REG_INDEX(offset);
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if (idx >= AW_R40_DRAMPHY_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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}
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trace_allwinner_r40_dramphy_read(offset, s->dramphy[idx], size);
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return s->dramphy[idx];
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}
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static void allwinner_r40_dramphy_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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AwR40DramCtlState *s = AW_R40_DRAMC(opaque);
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const uint32_t idx = REG_INDEX(offset);
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trace_allwinner_r40_dramphy_write(offset, val, size);
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if (idx >= AW_R40_DRAMPHY_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return;
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}
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s->dramphy[idx] = (uint32_t) val;
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}
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static const MemoryRegionOps allwinner_r40_dramcom_ops = {
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.read = allwinner_r40_dramcom_read,
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.write = allwinner_r40_dramcom_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl.min_access_size = 4,
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};
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static const MemoryRegionOps allwinner_r40_dramctl_ops = {
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.read = allwinner_r40_dramctl_read,
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.write = allwinner_r40_dramctl_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl.min_access_size = 4,
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};
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static const MemoryRegionOps allwinner_r40_dramphy_ops = {
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.read = allwinner_r40_dramphy_read,
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.write = allwinner_r40_dramphy_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl.min_access_size = 4,
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};
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static uint64_t allwinner_r40_detect_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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AwR40DramCtlState *s = AW_R40_DRAMC(opaque);
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const struct VirtualDDRChip *ddr = get_match_ddr(s->ram_size);
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uint64_t data = 0;
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if (ddr) {
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data = *address_to_autodetect_cells(s, ddr, (uint32_t)offset);
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}
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trace_allwinner_r40_dramc_detect_cell_read(offset, data);
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return data;
|
||||
}
|
||||
|
||||
static void allwinner_r40_detect_write(void *opaque, hwaddr offset,
|
||||
uint64_t data, unsigned size)
|
||||
{
|
||||
AwR40DramCtlState *s = AW_R40_DRAMC(opaque);
|
||||
const struct VirtualDDRChip *ddr = get_match_ddr(s->ram_size);
|
||||
|
||||
if (ddr) {
|
||||
uint64_t *cell = address_to_autodetect_cells(s, ddr, (uint32_t)offset);
|
||||
trace_allwinner_r40_dramc_detect_cell_write(offset, data);
|
||||
*cell = data;
|
||||
}
|
||||
}
|
||||
|
||||
static const MemoryRegionOps allwinner_r40_detect_ops = {
|
||||
.read = allwinner_r40_detect_read,
|
||||
.write = allwinner_r40_detect_write,
|
||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||
.valid = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4,
|
||||
},
|
||||
.impl.min_access_size = 4,
|
||||
};
|
||||
|
||||
/*
|
||||
* mctl_r40_detect_rank_count in u-boot will write the high 1G of DDR
|
||||
* to detect wether the board support dual_rank or not. Create a virtual memory
|
||||
* if the board's ram_size less or equal than 1G, and set read time out flag of
|
||||
* REG_DRAMCTL_PGSR when the user touch this high dram.
|
||||
*/
|
||||
static uint64_t allwinner_r40_dualrank_detect_read(void *opaque, hwaddr offset,
|
||||
unsigned size)
|
||||
{
|
||||
AwR40DramCtlState *s = AW_R40_DRAMC(opaque);
|
||||
uint32_t reg;
|
||||
|
||||
reg = s->dramctl[REG_INDEX(REG_DRAMCTL_PGCR)];
|
||||
if (reg & REG_DRAMCTL_PGCR_ENABLE_READ_TIMEOUT) { /* Enable read time out */
|
||||
/*
|
||||
* this driver only support one rank, mark READ_TIMEOUT when try
|
||||
* read the second rank.
|
||||
*/
|
||||
s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)]
|
||||
|= REG_DRAMCTL_PGSR_READ_TIMEOUT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const MemoryRegionOps allwinner_r40_dualrank_detect_ops = {
|
||||
.read = allwinner_r40_dualrank_detect_read,
|
||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||
.valid = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4,
|
||||
},
|
||||
.impl.min_access_size = 4,
|
||||
};
|
||||
|
||||
static void allwinner_r40_dramc_reset(DeviceState *dev)
|
||||
{
|
||||
AwR40DramCtlState *s = AW_R40_DRAMC(dev);
|
||||
|
||||
/* Set default values for registers */
|
||||
memset(&s->dramcom, 0, sizeof(s->dramcom));
|
||||
memset(&s->dramctl, 0, sizeof(s->dramctl));
|
||||
memset(&s->dramphy, 0, sizeof(s->dramphy));
|
||||
}
|
||||
|
||||
static void allwinner_r40_dramc_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
AwR40DramCtlState *s = AW_R40_DRAMC(dev);
|
||||
|
||||
if (!get_match_ddr(s->ram_size)) {
|
||||
error_report("%s: ram-size %u MiB is not supported",
|
||||
__func__, s->ram_size);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* detect_cells */
|
||||
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s), 3, s->ram_addr, 10);
|
||||
memory_region_set_enabled(&s->detect_cells, false);
|
||||
|
||||
/*
|
||||
* We only support DRAM size up to 1G now, so prepare a high memory page
|
||||
* after 1G for dualrank detect. index = 4
|
||||
*/
|
||||
memory_region_init_io(&s->dram_high, OBJECT(s),
|
||||
&allwinner_r40_dualrank_detect_ops, s,
|
||||
"DRAMHIGH", KiB);
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->dram_high);
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(s), 4, s->ram_addr + GiB);
|
||||
}
|
||||
|
||||
static void allwinner_r40_dramc_init(Object *obj)
|
||||
{
|
||||
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
||||
AwR40DramCtlState *s = AW_R40_DRAMC(obj);
|
||||
|
||||
/* DRAMCOM registers, index 0 */
|
||||
memory_region_init_io(&s->dramcom_iomem, OBJECT(s),
|
||||
&allwinner_r40_dramcom_ops, s,
|
||||
"DRAMCOM", 4 * KiB);
|
||||
sysbus_init_mmio(sbd, &s->dramcom_iomem);
|
||||
|
||||
/* DRAMCTL registers, index 1 */
|
||||
memory_region_init_io(&s->dramctl_iomem, OBJECT(s),
|
||||
&allwinner_r40_dramctl_ops, s,
|
||||
"DRAMCTL", 4 * KiB);
|
||||
sysbus_init_mmio(sbd, &s->dramctl_iomem);
|
||||
|
||||
/* DRAMPHY registers. index 2 */
|
||||
memory_region_init_io(&s->dramphy_iomem, OBJECT(s),
|
||||
&allwinner_r40_dramphy_ops, s,
|
||||
"DRAMPHY", 4 * KiB);
|
||||
sysbus_init_mmio(sbd, &s->dramphy_iomem);
|
||||
|
||||
/* R40 support max 2G memory but we only support up to 1G now. index 3 */
|
||||
memory_region_init_io(&s->detect_cells, OBJECT(s),
|
||||
&allwinner_r40_detect_ops, s,
|
||||
"DRAMCELLS", 1 * GiB);
|
||||
sysbus_init_mmio(sbd, &s->detect_cells);
|
||||
}
|
||||
|
||||
static Property allwinner_r40_dramc_properties[] = {
|
||||
DEFINE_PROP_UINT64("ram-addr", AwR40DramCtlState, ram_addr, 0x0),
|
||||
DEFINE_PROP_UINT32("ram-size", AwR40DramCtlState, ram_size, 256), /* MiB */
|
||||
DEFINE_PROP_END_OF_LIST()
|
||||
};
|
||||
|
||||
static const VMStateDescription allwinner_r40_dramc_vmstate = {
|
||||
.name = "allwinner-r40-dramc",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32_ARRAY(dramcom, AwR40DramCtlState,
|
||||
AW_R40_DRAMCOM_REGS_NUM),
|
||||
VMSTATE_UINT32_ARRAY(dramctl, AwR40DramCtlState,
|
||||
AW_R40_DRAMCTL_REGS_NUM),
|
||||
VMSTATE_UINT32_ARRAY(dramphy, AwR40DramCtlState,
|
||||
AW_R40_DRAMPHY_REGS_NUM),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static void allwinner_r40_dramc_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->reset = allwinner_r40_dramc_reset;
|
||||
dc->vmsd = &allwinner_r40_dramc_vmstate;
|
||||
dc->realize = allwinner_r40_dramc_realize;
|
||||
device_class_set_props(dc, allwinner_r40_dramc_properties);
|
||||
}
|
||||
|
||||
static const TypeInfo allwinner_r40_dramc_info = {
|
||||
.name = TYPE_AW_R40_DRAMC,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_init = allwinner_r40_dramc_init,
|
||||
.instance_size = sizeof(AwR40DramCtlState),
|
||||
.class_init = allwinner_r40_dramc_class_init,
|
||||
};
|
||||
|
||||
static void allwinner_r40_dramc_register(void)
|
||||
{
|
||||
type_register_static(&allwinner_r40_dramc_info);
|
||||
}
|
||||
|
||||
type_init(allwinner_r40_dramc_register)
|
||||
|
|
@ -45,6 +45,7 @@ softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c
|
|||
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-sysctrl.c'))
|
||||
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sid.c'))
|
||||
softmmu_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40-ccu.c'))
|
||||
softmmu_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40-dramc.c'))
|
||||
softmmu_ss.add(when: 'CONFIG_AXP2XX_PMU', if_true: files('axp2xx.c'))
|
||||
softmmu_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c'))
|
||||
softmmu_ss.add(when: 'CONFIG_NSERIES', if_true: files('cbus.c'))
|
||||
|
|
|
|||
|
|
@ -15,6 +15,20 @@ allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write
|
|||
allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
|
||||
allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
|
||||
|
||||
# allwinner-r40-dramc.c
|
||||
allwinner_r40_dramc_detect_cells_disable(void) "Disable detect cells"
|
||||
allwinner_r40_dramc_detect_cells_enable(void) "Enable detect cells"
|
||||
allwinner_r40_dramc_map_rows(uint8_t row_bits, uint8_t bank_bits, uint8_t col_bits) "DRAM layout: row_bits %d, bank_bits %d, col_bits %d"
|
||||
allwinner_r40_dramc_offset_to_cell(uint64_t offset, int row, int bank, int col) "offset 0x%" PRIx64 " row %d bank %d col %d"
|
||||
allwinner_r40_dramc_detect_cell_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 ""
|
||||
allwinner_r40_dramc_detect_cell_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 ""
|
||||
allwinner_r40_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
|
||||
allwinner_r40_dramcom_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
|
||||
allwinner_r40_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
|
||||
allwinner_r40_dramctl_write(uint64_t offset, uint64_t data, unsigned size) "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
|
||||
allwinner_r40_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
|
||||
allwinner_r40_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
|
||||
|
||||
# allwinner-sid.c
|
||||
allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
|
||||
allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include "hw/intc/arm_gic.h"
|
||||
#include "hw/sd/allwinner-sdhost.h"
|
||||
#include "hw/misc/allwinner-r40-ccu.h"
|
||||
#include "hw/misc/allwinner-r40-dramc.h"
|
||||
#include "hw/i2c/allwinner-i2c.h"
|
||||
#include "target/arm/cpu.h"
|
||||
#include "sysemu/block-backend.h"
|
||||
|
|
@ -54,7 +55,10 @@ enum {
|
|||
AW_R40_DEV_GIC_CPU,
|
||||
AW_R40_DEV_GIC_HYP,
|
||||
AW_R40_DEV_GIC_VCPU,
|
||||
AW_R40_DEV_SDRAM
|
||||
AW_R40_DEV_SDRAM,
|
||||
AW_R40_DEV_DRAMCOM,
|
||||
AW_R40_DEV_DRAMCTL,
|
||||
AW_R40_DEV_DRAMPHY,
|
||||
};
|
||||
|
||||
#define AW_R40_NUM_CPUS (4)
|
||||
|
|
@ -86,11 +90,18 @@ struct AwR40State {
|
|||
DeviceState parent_obj;
|
||||
/*< public >*/
|
||||
|
||||
/** Physical base address for start of RAM */
|
||||
hwaddr ram_addr;
|
||||
|
||||
/** Total RAM size in megabytes */
|
||||
uint32_t ram_size;
|
||||
|
||||
ARMCPU cpus[AW_R40_NUM_CPUS];
|
||||
const hwaddr *memmap;
|
||||
AwA10PITState timer;
|
||||
AwSdHostState mmc[AW_R40_NUM_MMCS];
|
||||
AwR40ClockCtlState ccu;
|
||||
AwR40DramCtlState dramc;
|
||||
AWI2CState i2c0;
|
||||
GICState gic;
|
||||
MemoryRegion sram_a1;
|
||||
|
|
|
|||
108
include/hw/misc/allwinner-r40-dramc.h
Normal file
108
include/hw/misc/allwinner-r40-dramc.h
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
/*
|
||||
* Allwinner R40 SDRAM Controller emulation
|
||||
*
|
||||
* Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com>
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef HW_MISC_ALLWINNER_R40_DRAMC_H
|
||||
#define HW_MISC_ALLWINNER_R40_DRAMC_H
|
||||
|
||||
#include "qom/object.h"
|
||||
#include "hw/sysbus.h"
|
||||
#include "exec/hwaddr.h"
|
||||
|
||||
/**
|
||||
* Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Highest register address used by DRAMCOM module */
|
||||
#define AW_R40_DRAMCOM_REGS_MAXADDR (0x804)
|
||||
|
||||
/** Total number of known DRAMCOM registers */
|
||||
#define AW_R40_DRAMCOM_REGS_NUM (AW_R40_DRAMCOM_REGS_MAXADDR / \
|
||||
sizeof(uint32_t))
|
||||
|
||||
/** Highest register address used by DRAMCTL module */
|
||||
#define AW_R40_DRAMCTL_REGS_MAXADDR (0x88c)
|
||||
|
||||
/** Total number of known DRAMCTL registers */
|
||||
#define AW_R40_DRAMCTL_REGS_NUM (AW_R40_DRAMCTL_REGS_MAXADDR / \
|
||||
sizeof(uint32_t))
|
||||
|
||||
/** Highest register address used by DRAMPHY module */
|
||||
#define AW_R40_DRAMPHY_REGS_MAXADDR (0x4)
|
||||
|
||||
/** Total number of known DRAMPHY registers */
|
||||
#define AW_R40_DRAMPHY_REGS_NUM (AW_R40_DRAMPHY_REGS_MAXADDR / \
|
||||
sizeof(uint32_t))
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* Object model
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TYPE_AW_R40_DRAMC "allwinner-r40-dramc"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(AwR40DramCtlState, AW_R40_DRAMC)
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* Allwinner R40 SDRAM Controller object instance state.
|
||||
*/
|
||||
struct AwR40DramCtlState {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
/*< public >*/
|
||||
|
||||
/** Physical base address for start of RAM */
|
||||
hwaddr ram_addr;
|
||||
|
||||
/** Total RAM size in megabytes */
|
||||
uint32_t ram_size;
|
||||
|
||||
uint8_t set_row_bits;
|
||||
uint8_t set_bank_bits;
|
||||
uint8_t set_col_bits;
|
||||
|
||||
/**
|
||||
* @name Memory Regions
|
||||
* @{
|
||||
*/
|
||||
MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */
|
||||
MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */
|
||||
MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */
|
||||
MemoryRegion dram_high; /**< The high 1G dram for dualrank detect */
|
||||
MemoryRegion detect_cells; /**< DRAM memory cells for auto detect */
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Hardware Registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t dramcom[AW_R40_DRAMCOM_REGS_NUM]; /**< DRAMCOM registers */
|
||||
uint32_t dramctl[AW_R40_DRAMCTL_REGS_NUM]; /**< DRAMCTL registers */
|
||||
uint32_t dramphy[AW_R40_DRAMPHY_REGS_NUM] ;/**< DRAMPHY registers */
|
||||
|
||||
/** @} */
|
||||
|
||||
};
|
||||
|
||||
#endif /* HW_MISC_ALLWINNER_R40_DRAMC_H */
|
||||
Loading…
Reference in a new issue